powerplay/hwmgr/smu7_hwmgr.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _SMU7_HWMGR_H
0025 #define _SMU7_HWMGR_H
0026
0027 #include "hwmgr.h"
0028 #include "ppatomctrl.h"
0029
0030 #define SMU7_MAX_HARDWARE_POWERLEVELS   2
0031
0032 #define SMU7_VOLTAGE_CONTROL_NONE                   0x0
0033 #define SMU7_VOLTAGE_CONTROL_BY_GPIO                0x1
0034 #define SMU7_VOLTAGE_CONTROL_BY_SVID2               0x2
0035 #define SMU7_VOLTAGE_CONTROL_MERGED                 0x3
0036
0037 enum gpu_pt_config_reg_type {
0038     GPU_CONFIGREG_MMR = 0,
0039     GPU_CONFIGREG_SMC_IND,
0040     GPU_CONFIGREG_DIDT_IND,
0041     GPU_CONFIGREG_GC_CAC_IND,
0042     GPU_CONFIGREG_CACHE,
0043     GPU_CONFIGREG_MAX
0044 };
0045
0046 struct gpu_pt_config_reg {
0047     uint32_t                           offset;
0048     uint32_t                           mask;
0049     uint32_t                           shift;
0050     uint32_t                           value;
0051     enum gpu_pt_config_reg_type       type;
0052 };
0053
0054 struct smu7_performance_level {
0055     uint32_t  memory_clock;
0056     uint32_t  engine_clock;
0057     uint16_t  pcie_gen;
0058     uint16_t  pcie_lane;
0059 };
0060
0061 struct smu7_thermal_temperature_setting {
0062     long temperature_low;
0063     long temperature_high;
0064     long temperature_shutdown;
0065 };
0066
0067 struct smu7_uvd_clocks {
0068     uint32_t  vclk;
0069     uint32_t  dclk;
0070 };
0071
0072 struct smu7_vce_clocks {
0073     uint32_t  evclk;
0074     uint32_t  ecclk;
0075 };
0076
0077 struct smu7_power_state {
0078     uint32_t                  magic;
0079     struct smu7_uvd_clocks    uvd_clks;
0080     struct smu7_vce_clocks    vce_clks;
0081     uint32_t                  sam_clk;
0082     uint16_t                  performance_level_count;
0083     bool                      dc_compatible;
0084     uint32_t                  sclk_threshold;
0085     struct smu7_performance_level  performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS];
0086 };
0087
0088 struct smu7_dpm_level {
0089     bool    enabled;
0090     uint32_t    value;
0091     uint32_t    param1;
0092 };
0093
0094 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5
0095 #define MAX_REGULAR_DPM_NUMBER 8
0096 #define SMU7_MINIMUM_ENGINE_CLOCK 2500
0097
0098 struct smu7_single_dpm_table {
0099     uint32_t        count;
0100     struct smu7_dpm_level   dpm_levels[MAX_REGULAR_DPM_NUMBER];
0101 };
0102
0103 struct smu7_dpm_table {
0104     struct smu7_single_dpm_table  sclk_table;
0105     struct smu7_single_dpm_table  mclk_table;
0106     struct smu7_single_dpm_table  pcie_speed_table;
0107     struct smu7_single_dpm_table  vddc_table;
0108     struct smu7_single_dpm_table  vddci_table;
0109     struct smu7_single_dpm_table  mvdd_table;
0110 };
0111
0112 struct smu7_clock_registers {
0113     uint32_t  vCG_SPLL_FUNC_CNTL;
0114     uint32_t  vCG_SPLL_FUNC_CNTL_2;
0115     uint32_t  vCG_SPLL_FUNC_CNTL_3;
0116     uint32_t  vCG_SPLL_FUNC_CNTL_4;
0117     uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
0118     uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
0119     uint32_t  vDLL_CNTL;
0120     uint32_t  vMCLK_PWRMGT_CNTL;
0121     uint32_t  vMPLL_AD_FUNC_CNTL;
0122     uint32_t  vMPLL_DQ_FUNC_CNTL;
0123     uint32_t  vMPLL_FUNC_CNTL;
0124     uint32_t  vMPLL_FUNC_CNTL_1;
0125     uint32_t  vMPLL_FUNC_CNTL_2;
0126     uint32_t  vMPLL_SS1;
0127     uint32_t  vMPLL_SS2;
0128 };
0129
0130 #define DISABLE_MC_LOADMICROCODE   1
0131 #define DISABLE_MC_CFGPROGRAMMING  2
0132
0133 struct smu7_voltage_smio_registers {
0134     uint32_t vS0_VID_LOWER_SMIO_CNTL;
0135 };
0136
0137 #define SMU7_MAX_LEAKAGE_COUNT  8
0138
0139 struct smu7_leakage_voltage {
0140     uint16_t  count;
0141     uint16_t  leakage_id[SMU7_MAX_LEAKAGE_COUNT];
0142     uint16_t  actual_voltage[SMU7_MAX_LEAKAGE_COUNT];
0143 };
0144
0145 struct smu7_vbios_boot_state {
0146     uint16_t    mvdd_bootup_value;
0147     uint16_t    vddc_bootup_value;
0148     uint16_t    vddci_bootup_value;
0149     uint16_t    vddgfx_bootup_value;
0150     uint32_t    sclk_bootup_value;
0151     uint32_t    mclk_bootup_value;
0152     uint16_t    pcie_gen_bootup_value;
0153     uint16_t    pcie_lane_bootup_value;
0154 };
0155
0156 struct smu7_display_timing {
0157     uint32_t  min_clock_in_sr;
0158     uint32_t  num_existing_displays;
0159     uint32_t  vrefresh;
0160 };
0161
0162 struct smu7_dpmlevel_enable_mask {
0163     uint32_t  uvd_dpm_enable_mask;
0164     uint32_t  vce_dpm_enable_mask;
0165     uint32_t  acp_dpm_enable_mask;
0166     uint32_t  samu_dpm_enable_mask;
0167     uint32_t  sclk_dpm_enable_mask;
0168     uint32_t  mclk_dpm_enable_mask;
0169     uint32_t  pcie_dpm_enable_mask;
0170 };
0171
0172 struct smu7_pcie_perf_range {
0173     uint16_t  max;
0174     uint16_t  min;
0175 };
0176
0177 struct smu7_odn_clock_voltage_dependency_table {
0178     uint32_t count;
0179     phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
0180 };
0181
0182 struct smu7_odn_dpm_table {
0183     struct phm_odn_clock_levels     odn_core_clock_dpm_levels;
0184     struct phm_odn_clock_levels     odn_memory_clock_dpm_levels;
0185     struct smu7_odn_clock_voltage_dependency_table  vdd_dependency_on_sclk;
0186     struct smu7_odn_clock_voltage_dependency_table  vdd_dependency_on_mclk;
0187     uint32_t                    odn_mclk_min_limit;
0188     uint32_t min_vddc;
0189     uint32_t max_vddc;
0190 };
0191
0192 struct profile_mode_setting {
0193     uint8_t bupdate_sclk;
0194     uint8_t sclk_up_hyst;
0195     uint8_t sclk_down_hyst;
0196     uint16_t sclk_activity;
0197     uint8_t bupdate_mclk;
0198     uint8_t mclk_up_hyst;
0199     uint8_t mclk_down_hyst;
0200     uint16_t mclk_activity;
0201 };
0202
0203 struct smu7_mclk_latency_entries {
0204     uint32_t  frequency;
0205     uint32_t  latency;
0206 };
0207
0208 struct smu7_mclk_latency_table {
0209     uint32_t  count;
0210     struct smu7_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
0211 };
0212
0213 struct smu7_hwmgr {
0214     struct smu7_dpm_table           dpm_table;
0215     struct smu7_dpm_table           golden_dpm_table;
0216     struct smu7_odn_dpm_table       odn_dpm_table;
0217     struct smu7_mclk_latency_table      mclk_latency_table;
0218
0219     uint32_t                        voting_rights_clients[8];
0220     uint32_t                        static_screen_threshold_unit;
0221     uint32_t                        static_screen_threshold;
0222     uint32_t                        voltage_control;
0223     uint32_t                        vdd_gfx_control;
0224     uint32_t                        vddc_vddgfx_delta;
0225     uint32_t                        active_auto_throttle_sources;
0226
0227     struct smu7_clock_registers            clock_registers;
0228
0229     bool                           is_memory_gddr5;
0230     uint16_t                       acpi_vddc;
0231     bool                           pspp_notify_required;
0232     uint16_t                       force_pcie_gen;
0233     uint16_t                       acpi_pcie_gen;
0234     uint32_t                       pcie_gen_cap;
0235     uint32_t                       pcie_lane_cap;
0236     uint32_t                       pcie_spc_cap;
0237     struct smu7_leakage_voltage          vddc_leakage;
0238     struct smu7_leakage_voltage          vddci_leakage;
0239     struct smu7_leakage_voltage          vddcgfx_leakage;
0240
0241     uint32_t                             mvdd_control;
0242     uint32_t                             vddc_mask_low;
0243     uint32_t                             mvdd_mask_low;
0244     uint16_t                            max_vddc_in_pptable;
0245     uint16_t                            min_vddc_in_pptable;
0246     uint16_t                            max_vddci_in_pptable;
0247     uint16_t                            min_vddci_in_pptable;
0248     bool                                is_uvd_enabled;
0249     struct smu7_vbios_boot_state        vbios_boot_state;
0250
0251     bool                           pcie_performance_request;
0252     bool                           battery_state;
0253     bool                           mclk_ignore_signal;
0254     bool                           is_tlu_enabled;
0255     bool                           disable_handshake;
0256     bool                           smc_voltage_control_enabled;
0257     bool                           vbi_time_out_support;
0258
0259     uint32_t                       soft_regs_start;
0260     /* ---- Stuff originally coming from Evergreen ---- */
0261     uint32_t                             vddci_control;
0262     struct pp_atomctrl_voltage_table     vddc_voltage_table;
0263     struct pp_atomctrl_voltage_table     vddci_voltage_table;
0264     struct pp_atomctrl_voltage_table     mvdd_voltage_table;
0265     struct pp_atomctrl_voltage_table     vddgfx_voltage_table;
0266
0267     uint32_t                             mgcg_cgtt_local2;
0268     uint32_t                             mgcg_cgtt_local3;
0269     uint32_t                             gpio_debug;
0270     uint32_t                             mc_micro_code_feature;
0271     uint32_t                             highest_mclk;
0272     uint16_t                             acpi_vddci;
0273     uint8_t                              mvdd_high_index;
0274     uint8_t                              mvdd_low_index;
0275     bool                                 dll_default_on;
0276     bool                                 performance_request_registered;
0277
0278     /* ---- Low Power Features ---- */
0279     bool                           ulv_supported;
0280
0281     /* ---- CAC Stuff ---- */
0282     uint32_t                       cac_table_start;
0283     bool                           cac_configuration_required;
0284     bool                           driver_calculate_cac_leakage;
0285     bool                           cac_enabled;
0286
0287     /* ---- DPM2 Parameters ---- */
0288     uint32_t                       power_containment_features;
0289     bool                           enable_dte_feature;
0290     bool                           enable_tdc_limit_feature;
0291     bool                           enable_pkg_pwr_tracking_feature;
0292     bool                           disable_uvd_power_tune_feature;
0293
0294
0295     uint32_t                       dte_tj_offset;
0296     uint32_t                       fast_watermark_threshold;
0297
0298     /* ---- Phase Shedding ---- */
0299     uint8_t                           vddc_phase_shed_control;
0300
0301     /* ---- DI/DT ---- */
0302     struct smu7_display_timing        display_timing;
0303
0304     /* ---- Thermal Temperature Setting ---- */
0305     struct smu7_thermal_temperature_setting  thermal_temp_setting;
0306     struct smu7_dpmlevel_enable_mask     dpm_level_enable_mask;
0307     uint32_t                                  need_update_smu7_dpm_table;
0308     uint32_t                                  sclk_dpm_key_disabled;
0309     uint32_t                                  mclk_dpm_key_disabled;
0310     uint32_t                                  pcie_dpm_key_disabled;
0311     uint32_t                                  min_engine_clocks;
0312     struct smu7_pcie_perf_range          pcie_gen_performance;
0313     struct smu7_pcie_perf_range          pcie_lane_performance;
0314     struct smu7_pcie_perf_range          pcie_gen_power_saving;
0315     struct smu7_pcie_perf_range          pcie_lane_power_saving;
0316     bool                                      use_pcie_performance_levels;
0317     bool                                      use_pcie_power_saving_levels;
0318     uint32_t                                  mclk_dpm0_activity_target;
0319     uint32_t                                  low_sclk_interrupt_threshold;
0320     uint32_t                                  last_mclk_dpm_enable_mask;
0321     bool                                      uvd_enabled;
0322
0323     /* ---- Power Gating States ---- */
0324     bool                           uvd_power_gated;
0325     bool                           vce_power_gated;
0326     bool                           need_long_memory_training;
0327
0328     /* Application power optimization parameters */
0329     bool                               update_up_hyst;
0330     bool                               update_down_hyst;
0331     uint32_t                           down_hyst;
0332     uint32_t                           up_hyst;
0333     uint32_t disable_dpm_mask;
0334     bool apply_optimized_settings;
0335
0336     uint32_t                              avfs_vdroop_override_setting;
0337     bool                                  apply_avfs_cks_off_voltage;
0338     uint32_t                              frame_time_x2;
0339     uint32_t                              last_sent_vbi_timeout;
0340     uint16_t                              mem_latency_high;
0341     uint16_t                              mem_latency_low;
0342     uint32_t                              vr_config;
0343     struct profile_mode_setting           current_profile_setting;
0344
0345     uint32_t                              ro_range_minimum;
0346     uint32_t                              ro_range_maximum;
0347
0348     bool                                  disable_edc_leakage_controller;
0349     AtomCtrl_HiLoLeakageOffsetTable       edc_hilo_leakage_offset_from_vbios;
0350     AtomCtrl_EDCLeakgeTable               edc_leakage_table;
0351 };
0352
0353 /* To convert to Q8.8 format for firmware */
0354 #define SMU7_Q88_FORMAT_CONVERSION_UNIT             256
0355
0356 enum SMU7_I2CLineID {
0357     SMU7_I2CLineID_DDC1 = 0x90,
0358     SMU7_I2CLineID_DDC2 = 0x91,
0359     SMU7_I2CLineID_DDC3 = 0x92,
0360     SMU7_I2CLineID_DDC4 = 0x93,
0361     SMU7_I2CLineID_DDC5 = 0x94,
0362     SMU7_I2CLineID_DDC6 = 0x95,
0363     SMU7_I2CLineID_SCLSDA = 0x96,
0364     SMU7_I2CLineID_DDCVGA = 0x97
0365 };
0366
0367 #define SMU7_I2C_DDC1DATA          0
0368 #define SMU7_I2C_DDC1CLK           1
0369 #define SMU7_I2C_DDC2DATA          2
0370 #define SMU7_I2C_DDC2CLK           3
0371 #define SMU7_I2C_DDC3DATA          4
0372 #define SMU7_I2C_DDC3CLK           5
0373 #define SMU7_I2C_SDA               40
0374 #define SMU7_I2C_SCL               41
0375 #define SMU7_I2C_DDC4DATA          65
0376 #define SMU7_I2C_DDC4CLK           66
0377 #define SMU7_I2C_DDC5DATA          0x48
0378 #define SMU7_I2C_DDC5CLK           0x49
0379 #define SMU7_I2C_DDC6DATA          0x4a
0380 #define SMU7_I2C_DDC6CLK           0x4b
0381 #define SMU7_I2C_DDCVGADATA        0x4c
0382 #define SMU7_I2C_DDCVGACLK         0x4d
0383
0384 #define SMU7_UNUSED_GPIO_PIN       0x7F
0385 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
0386         uint32_t clock_insr);
0387 #endif
0388