powerplay/hwmgr/smu7_baco.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "smu7_baco.h"
0025 #include "tonga_baco.h"
0026 #include "fiji_baco.h"
0027 #include "polaris_baco.h"
0028 #include "ci_baco.h"
0029
0030 #include "bif/bif_5_0_d.h"
0031 #include "bif/bif_5_0_sh_mask.h"
0032
0033 #include "smu/smu_7_1_2_d.h"
0034 #include "smu/smu_7_1_2_sh_mask.h"
0035
0036 int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
0037 {
0038     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0039     uint32_t reg;
0040
0041     *cap = false;
0042     if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
0043         return 0;
0044
0045     reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
0046
0047     if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
0048         *cap = true;
0049
0050     return 0;
0051 }
0052
0053 int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
0054 {
0055     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0056     uint32_t reg;
0057
0058     reg = RREG32(mmBACO_CNTL);
0059
0060     if (reg & BACO_CNTL__BACO_MODE_MASK)
0061         /* gfx has already entered BACO state */
0062         *state = BACO_STATE_IN;
0063     else
0064         *state = BACO_STATE_OUT;
0065     return 0;
0066 }
0067
0068 int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
0069 {
0070     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0071
0072     switch (adev->asic_type) {
0073     case CHIP_TOPAZ:
0074     case CHIP_TONGA:
0075         return tonga_baco_set_state(hwmgr, state);
0076     case CHIP_FIJI:
0077         return fiji_baco_set_state(hwmgr, state);
0078     case CHIP_POLARIS10:
0079     case CHIP_POLARIS11:
0080     case CHIP_POLARIS12:
0081     case CHIP_VEGAM:
0082         return polaris_baco_set_state(hwmgr, state);
0083 #ifdef CONFIG_DRM_AMDGPU_CIK
0084     case CHIP_BONAIRE:
0085     case CHIP_HAWAII:
0086         return ci_baco_set_state(hwmgr, state);
0087 #endif
0088     default:
0089         return -EINVAL;
0090     }
0091 }