powerplay/hwmgr/smu10_hwmgr.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU10_HWMGR_H
0025 #define SMU10_HWMGR_H
0026
0027 #include "hwmgr.h"
0028 #include "smu10_inc.h"
0029 #include "smu10_driver_if.h"
0030 #include "rv_ppsmc.h"
0031
0032
0033 #define SMU10_MAX_HARDWARE_POWERLEVELS               8
0034 #define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS   15
0035
0036 #define DPMFlags_SCLK_Enabled                     0x00000001
0037 #define DPMFlags_UVD_Enabled                      0x00000002
0038 #define DPMFlags_VCE_Enabled                      0x00000004
0039 #define DPMFlags_ACP_Enabled                      0x00000008
0040 #define DPMFlags_ForceHighestValid                0x40000000
0041
0042 /* Do not change the following, it is also defined in SMU8.h */
0043 #define SMU_EnabledFeatureScoreboard_AcpDpmOn     0x00000001
0044 #define SMU_EnabledFeatureScoreboard_SclkDpmOn    0x00200000
0045 #define SMU_EnabledFeatureScoreboard_UvdDpmOn     0x01000000
0046 #define SMU_EnabledFeatureScoreboard_VceDpmOn     0x02000000
0047
0048 #define SMU_PHYID_SHIFT      8
0049
0050 #define SMU10_PCIE_POWERGATING_TARGET_GFX            0
0051 #define SMU10_PCIE_POWERGATING_TARGET_DDI            1
0052 #define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE     2
0053 #define SMU10_PCIE_POWERGATING_TARGET_PHY            3
0054
0055 enum VQ_TYPE {
0056     CLOCK_TYPE_DCLK = 0L,
0057     CLOCK_TYPE_ECLK,
0058     CLOCK_TYPE_SCLK,
0059     CLOCK_TYPE_CCLK,
0060     VQ_GFX_CU
0061 };
0062
0063 #define SUSTAINABLE_SCLK_MASK  0x00ffffff
0064 #define SUSTAINABLE_SCLK_SHIFT 0
0065 #define SUSTAINABLE_CU_MASK    0xff000000
0066 #define SUSTAINABLE_CU_SHIFT   24
0067
0068 struct smu10_dpm_entry {
0069     uint32_t soft_min_clk;
0070     uint32_t hard_min_clk;
0071     uint32_t soft_max_clk;
0072     uint32_t hard_max_clk;
0073 };
0074
0075 struct smu10_power_level {
0076     uint32_t engine_clock;
0077     uint8_t vddc_index;
0078     uint8_t ds_divider_index;
0079     uint8_t ss_divider_index;
0080     uint8_t allow_gnb_slow;
0081     uint8_t force_nbp_state;
0082     uint8_t display_wm;
0083     uint8_t vce_wm;
0084     uint8_t num_simd_to_powerdown;
0085     uint8_t hysteresis_up;
0086     uint8_t rsv[3];
0087 };
0088
0089 /*used for the nbpsFlags field in smu10_power state*/
0090 #define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1<<0)
0091 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1<<1)
0092 #define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1<<2)
0093
0094 #define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE    (1<<0)
0095
0096 struct smu10_uvd_clocks {
0097     uint32_t vclk;
0098     uint32_t dclk;
0099     uint32_t vclk_low_divider;
0100     uint32_t vclk_high_divider;
0101     uint32_t dclk_low_divider;
0102     uint32_t dclk_high_divider;
0103 };
0104
0105 struct pp_disable_nbpslo_flags {
0106     union {
0107         struct {
0108             uint32_t entry : 1;
0109             uint32_t display : 1;
0110             uint32_t driver: 1;
0111             uint32_t vce : 1;
0112             uint32_t uvd : 1;
0113             uint32_t acp : 1;
0114             uint32_t reserved: 26;
0115         } bits;
0116         uint32_t u32All;
0117     };
0118 };
0119
0120
0121 enum smu10_pstate_previous_action {
0122     DO_NOTHING = 1,
0123     FORCE_HIGH,
0124     CANCEL_FORCE_HIGH
0125 };
0126
0127 struct smu10_power_state {
0128     unsigned int magic;
0129     uint32_t level;
0130     struct smu10_uvd_clocks uvd_clocks;
0131     uint32_t evclk;
0132     uint32_t ecclk;
0133     uint32_t samclk;
0134     uint32_t acpclk;
0135     bool need_dfs_bypass;
0136
0137     uint32_t nbps_flags;
0138     uint32_t bapm_flags;
0139     uint8_t dpm0_pg_nbps_low;
0140     uint8_t dpm0_pg_nbps_high;
0141     uint8_t dpm_x_nbps_low;
0142     uint8_t dpm_x_nbps_high;
0143
0144     enum smu10_pstate_previous_action action;
0145
0146     struct smu10_power_level levels[SMU10_MAX_HARDWARE_POWERLEVELS];
0147     struct pp_disable_nbpslo_flags nbpslo_flags;
0148 };
0149
0150 #define SMU10_NUM_NBPSTATES        4
0151 #define SMU10_NUM_NBPMEMORYCLOCK   2
0152
0153
0154 struct smu10_display_phy_info_entry {
0155     uint8_t                   phy_present;
0156     uint8_t                   active_lane_mapping;
0157     uint8_t                   display_config_type;
0158     uint8_t                   active_num_of_lanes;
0159 };
0160
0161 #define SMU10_MAX_DISPLAYPHY_IDS       10
0162
0163 struct smu10_display_phy_info {
0164     bool                         display_phy_access_initialized;
0165     struct smu10_display_phy_info_entry  entries[SMU10_MAX_DISPLAYPHY_IDS];
0166 };
0167
0168 #define MAX_DISPLAY_CLOCK_LEVEL 8
0169
0170 struct smu10_system_info{
0171     uint8_t                      htc_tmp_lmt;
0172     uint8_t                      htc_hyst_lmt;
0173 };
0174
0175 #define MAX_REGULAR_DPM_NUMBER 8
0176
0177 struct smu10_mclk_latency_entries {
0178     uint32_t  frequency;
0179     uint32_t  latency;
0180 };
0181
0182 struct smu10_mclk_latency_table {
0183     uint32_t  count;
0184     struct smu10_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
0185 };
0186
0187 struct smu10_clock_voltage_dependency_record {
0188     uint32_t clk;
0189     uint32_t vol;
0190 };
0191
0192
0193 struct smu10_voltage_dependency_table {
0194     uint32_t count;
0195     struct smu10_clock_voltage_dependency_record entries[];
0196 };
0197
0198 struct smu10_clock_voltage_information {
0199     struct smu10_voltage_dependency_table    *vdd_dep_on_dcefclk;
0200     struct smu10_voltage_dependency_table    *vdd_dep_on_socclk;
0201     struct smu10_voltage_dependency_table    *vdd_dep_on_fclk;
0202     struct smu10_voltage_dependency_table    *vdd_dep_on_mclk;
0203     struct smu10_voltage_dependency_table    *vdd_dep_on_dispclk;
0204     struct smu10_voltage_dependency_table    *vdd_dep_on_dppclk;
0205     struct smu10_voltage_dependency_table    *vdd_dep_on_phyclk;
0206 };
0207
0208 struct smu10_hwmgr {
0209     uint32_t disable_driver_thermal_policy;
0210     uint32_t thermal_auto_throttling_treshold;
0211     struct smu10_system_info sys_info;
0212     struct smu10_mclk_latency_table mclk_latency_table;
0213
0214     uint32_t ddi_power_gating_disabled;
0215
0216     struct smu10_display_phy_info_entry            display_phy_info;
0217     uint32_t dce_slow_sclk_threshold;
0218
0219     bool disp_clk_bypass;
0220     bool disp_clk_bypass_pending;
0221     uint32_t bapm_enabled;
0222
0223     bool video_start;
0224     bool battery_state;
0225
0226     uint32_t is_nb_dpm_enabled;
0227     uint32_t is_voltage_island_enabled;
0228     uint32_t disable_smu_acp_s3_handshake;
0229     uint32_t disable_notify_smu_vpu_recovery;
0230     bool                           in_vpu_recovery;
0231     bool pg_acp_init;
0232     uint8_t disp_config;
0233
0234     /* PowerTune */
0235     uint32_t power_containment_features;
0236     bool cac_enabled;
0237     bool disable_uvd_power_tune_feature;
0238     bool enable_bapm_feature;
0239     bool enable_tdc_limit_feature;
0240
0241
0242     /* SMC SRAM Address of firmware header tables */
0243     uint32_t sram_end;
0244     uint32_t dpm_table_start;
0245     uint32_t soft_regs_start;
0246
0247     /* start of SMU7_Fusion_DpmTable */
0248
0249     uint8_t uvd_level_count;
0250     uint8_t vce_level_count;
0251     uint8_t acp_level_count;
0252     uint8_t samu_level_count;
0253
0254     uint32_t fps_high_threshold;
0255     uint32_t fps_low_threshold;
0256
0257     uint32_t dpm_flags;
0258     struct smu10_dpm_entry sclk_dpm;
0259     struct smu10_dpm_entry uvd_dpm;
0260     struct smu10_dpm_entry vce_dpm;
0261     struct smu10_dpm_entry acp_dpm;
0262     bool acp_power_up_no_dsp;
0263
0264     uint32_t max_sclk_level;
0265     uint32_t num_of_clk_entries;
0266
0267     /* CPU Power State */
0268     uint32_t                          separation_time;
0269     bool                              cc6_disable;
0270     bool                              pstate_disable;
0271     bool                              cc6_setting_changed;
0272
0273     uint32_t                             ulTotalActiveCUs;
0274
0275     bool                           isp_tileA_power_gated;
0276     bool                           isp_tileB_power_gated;
0277     uint32_t                       isp_actual_hard_min_freq;
0278     uint32_t                       soc_actual_hard_min_freq;
0279     uint32_t                       dcf_actual_hard_min_freq;
0280
0281     uint32_t                        f_actual_hard_min_freq;
0282     uint32_t                        fabric_actual_soft_min_freq;
0283     uint32_t                        vclk_soft_min;
0284     uint32_t                        dclk_soft_min;
0285     uint32_t                        gfx_actual_soft_min_freq;
0286     uint32_t                        gfx_actual_soft_max_freq;
0287     uint32_t                        gfx_min_freq_limit;
0288     uint32_t                        gfx_max_freq_limit; /* in 10Khz*/
0289
0290     bool                           vcn_power_gated;
0291     bool                           vcn_dpg_mode;
0292
0293     bool                           gfx_off_controled_by_driver;
0294     bool                           water_marks_exist;
0295     Watermarks_t                      water_marks_table;
0296     struct smu10_clock_voltage_information   clock_vol_info;
0297     DpmClocks_t                       clock_table;
0298
0299     uint32_t active_process_mask;
0300     bool need_min_deep_sleep_dcefclk;
0301     uint32_t                             deep_sleep_dcefclk;
0302     uint32_t                             num_active_display;
0303
0304     bool                            fine_grain_enabled;
0305 };
0306
0307 struct pp_hwmgr;
0308
0309 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
0310
0311 /* UMD PState SMU10 Msg Parameters in MHz */
0312 #define SMU10_UMD_PSTATE_GFXCLK                 700
0313 #define SMU10_UMD_PSTATE_SOCCLK                 626
0314 #define SMU10_UMD_PSTATE_FCLK                   933
0315 #define SMU10_UMD_PSTATE_VCE                    0x03C00320
0316 #define SMU10_UMD_PSTATE_PROFILE_VCE            0x02AD0229
0317
0318 #define SMU10_UMD_PSTATE_PEAK_SOCCLK            757
0319 #define SMU10_UMD_PSTATE_PEAK_FCLK              1200
0320
0321 #define SMU10_UMD_PSTATE_MIN_FCLK               400
0322 #define SMU10_UMD_PSTATE_MIN_SOCCLK             200
0323 #define SMU10_UMD_PSTATE_MIN_VCE                0x0190012C
0324
0325 #endif