powerplay/hwmgr/ppatomfwctrl.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef PP_ATOMFWCTRL_H
0025 #define PP_ATOMFWCTRL_H
0026
0027 #include "hwmgr.h"
0028
0029 typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
0030
0031 #define GetIndexIntoMasterCmdTable(FieldName) \
0032     (offsetof(struct atom_master_list_of_command_functions_v2_1, FieldName) / sizeof(uint16_t))
0033 #define GetIndexIntoMasterDataTable(FieldName) \
0034     (offsetof(struct atom_master_list_of_data_tables_v2_1, FieldName) / sizeof(uint16_t))
0035
0036 #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
0037
0038 struct pp_atomfwctrl_voltage_table_entry {
0039     uint16_t value;
0040     uint32_t  smio_low;
0041 };
0042
0043 struct pp_atomfwctrl_voltage_table {
0044     uint32_t count;
0045     uint32_t mask_low;
0046     uint32_t phase_delay;
0047     uint8_t psi0_enable;
0048     uint8_t psi1_enable;
0049     uint8_t max_vid_step;
0050     uint8_t telemetry_offset;
0051     uint8_t telemetry_slope;
0052     struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
0053 };
0054
0055 struct pp_atomfwctrl_gpio_pin_assignment {
0056     uint16_t us_gpio_pin_aindex;
0057     uint8_t uc_gpio_pin_bit_shift;
0058 };
0059
0060 struct pp_atomfwctrl_clock_dividers_soc15 {
0061     uint32_t   ulClock;           /* the actual clock */
0062     uint32_t   ulDid;             /* DFS divider */
0063     uint32_t   ulPll_fb_mult;     /* Feedback Multiplier:  bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
0064     uint32_t   ulPll_ss_fbsmult;  /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
0065     uint16_t   usPll_ss_slew_frac;
0066     uint8_t    ucPll_ss_enable;
0067     uint8_t    ucReserve;
0068     uint32_t   ulReserve[2];
0069 };
0070
0071 struct pp_atomfwctrl_avfs_parameters {
0072     uint32_t   ulMaxVddc;
0073     uint32_t   ulMinVddc;
0074
0075     uint32_t   ulMeanNsigmaAcontant0;
0076     uint32_t   ulMeanNsigmaAcontant1;
0077     uint32_t   ulMeanNsigmaAcontant2;
0078     uint16_t   usMeanNsigmaDcTolSigma;
0079     uint16_t   usMeanNsigmaPlatformMean;
0080     uint16_t   usMeanNsigmaPlatformSigma;
0081     uint32_t   ulGbVdroopTableCksoffA0;
0082     uint32_t   ulGbVdroopTableCksoffA1;
0083     uint32_t   ulGbVdroopTableCksoffA2;
0084     uint32_t   ulGbVdroopTableCksonA0;
0085     uint32_t   ulGbVdroopTableCksonA1;
0086     uint32_t   ulGbVdroopTableCksonA2;
0087
0088     uint32_t   ulGbFuseTableCksoffM1;
0089     uint32_t   ulGbFuseTableCksoffM2;
0090     uint32_t   ulGbFuseTableCksoffB;
0091
0092     uint32_t   ulGbFuseTableCksonM1;
0093     uint32_t   ulGbFuseTableCksonM2;
0094     uint32_t   ulGbFuseTableCksonB;
0095
0096     uint8_t    ucEnableGbVdroopTableCkson;
0097     uint8_t    ucEnableGbFuseTableCkson;
0098     uint16_t   usPsmAgeComfactor;
0099
0100     uint32_t   ulDispclk2GfxclkM1;
0101     uint32_t   ulDispclk2GfxclkM2;
0102     uint32_t   ulDispclk2GfxclkB;
0103     uint32_t   ulDcefclk2GfxclkM1;
0104     uint32_t   ulDcefclk2GfxclkM2;
0105     uint32_t   ulDcefclk2GfxclkB;
0106     uint32_t   ulPixelclk2GfxclkM1;
0107     uint32_t   ulPixelclk2GfxclkM2;
0108     uint32_t   ulPixelclk2GfxclkB;
0109     uint32_t   ulPhyclk2GfxclkM1;
0110     uint32_t   ulPhyclk2GfxclkM2;
0111     uint32_t   ulPhyclk2GfxclkB;
0112     uint32_t   ulAcgGbVdroopTableA0;
0113     uint32_t   ulAcgGbVdroopTableA1;
0114     uint32_t   ulAcgGbVdroopTableA2;
0115     uint32_t   ulAcgGbFuseTableM1;
0116     uint32_t   ulAcgGbFuseTableM2;
0117     uint32_t   ulAcgGbFuseTableB;
0118     uint32_t   ucAcgEnableGbVdroopTable;
0119     uint32_t   ucAcgEnableGbFuseTable;
0120 };
0121
0122 struct pp_atomfwctrl_gpio_parameters {
0123     uint8_t   ucAcDcGpio;
0124     uint8_t   ucAcDcPolarity;
0125     uint8_t   ucVR0HotGpio;
0126     uint8_t   ucVR0HotPolarity;
0127     uint8_t   ucVR1HotGpio;
0128     uint8_t   ucVR1HotPolarity;
0129     uint8_t   ucFwCtfGpio;
0130     uint8_t   ucFwCtfPolarity;
0131 };
0132
0133 struct pp_atomfwctrl_bios_boot_up_values {
0134     uint32_t   ulRevision;
0135     uint32_t   ulGfxClk;
0136     uint32_t   ulUClk;
0137     uint32_t   ulSocClk;
0138     uint32_t   ulDCEFClk;
0139     uint32_t   ulEClk;
0140     uint32_t   ulVClk;
0141     uint32_t   ulDClk;
0142     uint32_t   ulFClk;
0143     uint16_t   usVddc;
0144     uint16_t   usVddci;
0145     uint16_t   usMvddc;
0146     uint16_t   usVddGfx;
0147     uint8_t    ucCoolingID;
0148 };
0149
0150 struct pp_atomfwctrl_smc_dpm_parameters
0151 {
0152   uint8_t  liquid1_i2c_address;
0153   uint8_t  liquid2_i2c_address;
0154   uint8_t  vr_i2c_address;
0155   uint8_t  plx_i2c_address;
0156   uint8_t  liquid_i2c_linescl;
0157   uint8_t  liquid_i2c_linesda;
0158   uint8_t  vr_i2c_linescl;
0159   uint8_t  vr_i2c_linesda;
0160   uint8_t  plx_i2c_linescl;
0161   uint8_t  plx_i2c_linesda;
0162   uint8_t  vrsensorpresent;
0163   uint8_t  liquidsensorpresent;
0164   uint16_t maxvoltagestepgfx;
0165   uint16_t maxvoltagestepsoc;
0166   uint8_t  vddgfxvrmapping;
0167   uint8_t  vddsocvrmapping;
0168   uint8_t  vddmem0vrmapping;
0169   uint8_t  vddmem1vrmapping;
0170   uint8_t  gfxulvphasesheddingmask;
0171   uint8_t  soculvphasesheddingmask;
0172
0173   uint16_t gfxmaxcurrent;
0174   uint8_t  gfxoffset;
0175   uint8_t  padding_telemetrygfx;
0176   uint16_t socmaxcurrent;
0177   uint8_t  socoffset;
0178   uint8_t  padding_telemetrysoc;
0179   uint16_t mem0maxcurrent;
0180   uint8_t  mem0offset;
0181   uint8_t  padding_telemetrymem0;
0182   uint16_t mem1maxcurrent;
0183   uint8_t  mem1offset;
0184   uint8_t  padding_telemetrymem1;
0185
0186   uint8_t  acdcgpio;
0187   uint8_t  acdcpolarity;
0188   uint8_t  vr0hotgpio;
0189   uint8_t  vr0hotpolarity;
0190   uint8_t  vr1hotgpio;
0191   uint8_t  vr1hotpolarity;
0192   uint8_t  padding1;
0193   uint8_t  padding2;
0194
0195   uint8_t  ledpin0;
0196   uint8_t  ledpin1;
0197   uint8_t  ledpin2;
0198
0199     uint8_t  pllgfxclkspreadenabled;
0200     uint8_t  pllgfxclkspreadpercent;
0201     uint16_t pllgfxclkspreadfreq;
0202
0203   uint8_t  uclkspreadenabled;
0204   uint8_t  uclkspreadpercent;
0205   uint16_t uclkspreadfreq;
0206
0207   uint8_t socclkspreadenabled;
0208   uint8_t socclkspreadpercent;
0209   uint16_t socclkspreadfreq;
0210
0211     uint8_t  acggfxclkspreadenabled;
0212     uint8_t  acggfxclkspreadpercent;
0213     uint16_t acggfxclkspreadfreq;
0214
0215     uint8_t Vr2_I2C_address;
0216 };
0217
0218 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
0219         uint32_t clock_type, uint32_t clock_value,
0220         struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
0221 int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
0222 bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
0223         struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
0224
0225 int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
0226         uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
0227 bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
0228         uint8_t voltage_type, uint8_t voltage_mode);
0229
0230 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
0231         struct pp_atomfwctrl_avfs_parameters *param);
0232 int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
0233         struct pp_atomfwctrl_gpio_parameters *param);
0234
0235 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
0236             struct pp_atomfwctrl_bios_boot_up_values *boot_values);
0237 int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
0238             struct pp_atomfwctrl_smc_dpm_parameters *param);
0239 int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
0240                     uint8_t clk_id, uint8_t syspll_id,
0241                     uint32_t *frequency);
0242
0243 #endif
0244