powerplay/hwmgr/ppatomctrl.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef PP_ATOMVOLTAGECTRL_H
0025 #define PP_ATOMVOLTAGECTRL_H
0026
0027 #include "hwmgr.h"
0028
0029 /* As returned from PowerConnectorDetectionTable. */
0030 #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE  0x80
0031 #define PP_ATOM_POWER_BUDGET_SHOW_WARNING       0x40
0032 #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER        0x20
0033 #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR    0x0F
0034
0035 /* New functions for Evergreen and beyond. */
0036 #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
0037
0038 struct pp_atomctrl_clock_dividers {
0039     uint32_t pll_post_divider;
0040     uint32_t pll_feedback_divider;
0041     uint32_t pll_ref_divider;
0042     bool  enable_post_divider;
0043 };
0044
0045 typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
0046
0047 union pp_atomctrl_tcipll_fb_divider {
0048     struct {
0049         uint32_t ul_fb_div_frac : 14;
0050         uint32_t ul_fb_div : 12;
0051         uint32_t un_used : 6;
0052     };
0053     uint32_t ul_fb_divider;
0054 };
0055
0056 typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
0057
0058 struct pp_atomctrl_clock_dividers_rv730 {
0059     uint32_t pll_post_divider;
0060     pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
0061     uint32_t pll_ref_divider;
0062     bool  enable_post_divider;
0063     bool  enable_dithen;
0064     uint32_t vco_mode;
0065 };
0066 typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
0067
0068
0069 struct pp_atomctrl_clock_dividers_kong {
0070     uint32_t    pll_post_divider;
0071     uint32_t    real_clock;
0072 };
0073 typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
0074
0075 struct pp_atomctrl_clock_dividers_ci {
0076     uint32_t    pll_post_divider;               /* post divider value */
0077     uint32_t    real_clock;
0078     pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /* Output Parameter: PLL FB divider */
0079     uint8_t   uc_pll_ref_div;                      /* Output Parameter: PLL ref divider */
0080     uint8_t   uc_pll_post_div;                      /* Output Parameter: PLL post divider */
0081     uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
0082 };
0083 typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
0084
0085 struct pp_atomctrl_clock_dividers_vi {
0086     uint32_t    pll_post_divider;               /* post divider value */
0087     uint32_t    real_clock;
0088     pp_atomctrl_tcipll_fb_divider   ul_fb_div;         /*Output Parameter: PLL FB divider */
0089     uint8_t   uc_pll_ref_div;                      /*Output Parameter: PLL ref divider */
0090     uint8_t   uc_pll_post_div;                     /*Output Parameter: PLL post divider */
0091     uint8_t   uc_pll_cntl_flag;                    /*Output Flags: control flag */
0092 };
0093 typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
0094
0095 struct pp_atomctrl_clock_dividers_ai {
0096     u16 usSclk_fcw_frac;
0097     u16  usSclk_fcw_int;
0098     u8   ucSclkPostDiv;
0099     u8   ucSclkVcoMode;
0100     u8   ucSclkPllRange;
0101     u8   ucSscEnable;
0102     u16  usSsc_fcw1_frac;
0103     u16  usSsc_fcw1_int;
0104     u16  usReserved;
0105     u16  usPcc_fcw_int;
0106     u16  usSsc_fcw_slew_frac;
0107     u16  usPcc_fcw_slew_frac;
0108 };
0109 typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
0110
0111
0112 union pp_atomctrl_s_mpll_fb_divider {
0113     struct {
0114         uint32_t cl_kf : 12;
0115         uint32_t clk_frac : 12;
0116         uint32_t un_used : 8;
0117     };
0118     uint32_t ul_fb_divider;
0119 };
0120 typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
0121
0122 enum pp_atomctrl_spread_spectrum_mode {
0123     pp_atomctrl_spread_spectrum_mode_down = 0,
0124     pp_atomctrl_spread_spectrum_mode_center
0125 };
0126 typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
0127
0128 struct pp_atomctrl_memory_clock_param {
0129     pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
0130     uint32_t mpll_post_divider;
0131     uint32_t bw_ctrl;
0132     uint32_t dll_speed;
0133     uint32_t vco_mode;
0134     uint32_t yclk_sel;
0135     uint32_t qdr;
0136     uint32_t half_rate;
0137 };
0138 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
0139
0140 struct pp_atomctrl_memory_clock_param_ai {
0141     uint32_t ulClock;
0142     uint32_t ulPostDiv;
0143     uint16_t ulMclk_fcw_frac;
0144     uint16_t ulMclk_fcw_int;
0145 };
0146 typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai;
0147
0148 struct pp_atomctrl_internal_ss_info {
0149     uint32_t speed_spectrum_percentage;                      /* in 1/100 percentage */
0150     uint32_t speed_spectrum_rate;                            /* in KHz */
0151     pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
0152 };
0153 typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
0154
0155 #ifndef NUMBER_OF_M3ARB_PARAMS
0156 #define NUMBER_OF_M3ARB_PARAMS 3
0157 #endif
0158
0159 #ifndef NUMBER_OF_M3ARB_PARAM_SETS
0160 #define NUMBER_OF_M3ARB_PARAM_SETS 10
0161 #endif
0162
0163 struct pp_atomctrl_kong_system_info {
0164     uint32_t            ul_bootup_uma_clock;          /* in 10kHz unit */
0165     uint16_t            us_max_nb_voltage;            /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
0166     uint16_t            us_min_nb_voltage;            /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */
0167     uint16_t            us_bootup_nb_voltage;         /* boot up NB voltage */
0168     uint8_t         uc_htc_tmp_lmt;               /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */
0169     uint8_t         uc_tj_offset;                /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */
0170     /* 0: default 1: uvd 2: fs-3d */
0171     uint32_t          ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */
0172 };
0173 typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
0174
0175 struct pp_atomctrl_memory_info {
0176     uint8_t memory_vendor;
0177     uint8_t memory_type;
0178 };
0179 typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
0180
0181 #define MAX_AC_TIMING_ENTRIES 16
0182
0183 struct pp_atomctrl_memory_clock_range_table {
0184     uint8_t   num_entries;
0185     uint8_t   rsv[3];
0186
0187     uint32_t mclk[MAX_AC_TIMING_ENTRIES];
0188 };
0189 typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
0190
0191 struct pp_atomctrl_voltage_table_entry {
0192     uint16_t value;
0193     uint32_t smio_low;
0194 };
0195
0196 typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
0197
0198 struct pp_atomctrl_voltage_table {
0199     uint32_t count;
0200     uint32_t mask_low;
0201     uint32_t phase_delay;   /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */
0202     pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
0203 };
0204
0205 typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
0206
0207 #define VBIOS_MC_REGISTER_ARRAY_SIZE           32
0208 #define VBIOS_MAX_AC_TIMING_ENTRIES            20
0209
0210 struct pp_atomctrl_mc_reg_entry {
0211     uint32_t           mclk_max;
0212     uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
0213 };
0214 typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
0215
0216 struct pp_atomctrl_mc_register_address {
0217     uint16_t s1;
0218     uint8_t  uc_pre_reg_data;
0219 };
0220
0221 typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
0222
0223 #define MAX_SCLK_RANGE 8
0224
0225 struct pp_atom_ctrl_sclk_range_table_entry{
0226     uint8_t  ucVco_setting;
0227     uint8_t  ucPostdiv;
0228     uint16_t usFcw_pcc;
0229     uint16_t usFcw_trans_upper;
0230     uint16_t usRcw_trans_lower;
0231 };
0232
0233
0234 struct pp_atom_ctrl_sclk_range_table{
0235     struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
0236 };
0237
0238 struct pp_atomctrl_mc_reg_table {
0239     uint8_t                         last;                    /* number of registers */
0240     uint8_t                         num_entries;             /* number of AC timing entries */
0241     pp_atomctrl_mc_reg_entry        mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
0242     pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
0243 };
0244 typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
0245
0246 struct pp_atomctrl_gpio_pin_assignment {
0247     uint16_t                   us_gpio_pin_aindex;
0248     uint8_t                    uc_gpio_pin_bit_shift;
0249 };
0250 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
0251
0252 struct pp_atom_ctrl__avfs_parameters {
0253     uint32_t  ulAVFS_meanNsigma_Acontant0;
0254     uint32_t  ulAVFS_meanNsigma_Acontant1;
0255     uint32_t  ulAVFS_meanNsigma_Acontant2;
0256     uint16_t usAVFS_meanNsigma_DC_tol_sigma;
0257     uint16_t usAVFS_meanNsigma_Platform_mean;
0258     uint16_t usAVFS_meanNsigma_Platform_sigma;
0259     uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a0;
0260     uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a1;
0261     uint32_t  ulGB_VDROOP_TABLE_CKSOFF_a2;
0262     uint32_t  ulGB_VDROOP_TABLE_CKSON_a0;
0263     uint32_t  ulGB_VDROOP_TABLE_CKSON_a1;
0264     uint32_t  ulGB_VDROOP_TABLE_CKSON_a2;
0265     uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
0266     uint16_t  usAVFSGB_FUSE_TABLE_CKSOFF_m2;
0267     uint32_t  ulAVFSGB_FUSE_TABLE_CKSOFF_b;
0268     uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_m1;
0269     uint16_t  usAVFSGB_FUSE_TABLE_CKSON_m2;
0270     uint32_t  ulAVFSGB_FUSE_TABLE_CKSON_b;
0271     uint16_t  usMaxVoltage_0_25mv;
0272     uint8_t  ucEnableGB_VDROOP_TABLE_CKSOFF;
0273     uint8_t  ucEnableGB_VDROOP_TABLE_CKSON;
0274     uint8_t  ucEnableGB_FUSE_TABLE_CKSOFF;
0275     uint8_t  ucEnableGB_FUSE_TABLE_CKSON;
0276     uint16_t usPSM_Age_ComFactor;
0277     uint8_t  ucEnableApplyAVFS_CKS_OFF_Voltage;
0278     uint8_t  ucReserved;
0279 };
0280
0281 struct _AtomCtrl_HiLoLeakageOffsetTable
0282 {
0283     USHORT usHiLoLeakageThreshold;
0284     USHORT usEdcDidtLoDpm7TableOffset;
0285     USHORT usEdcDidtHiDpm7TableOffset;
0286 };
0287 typedef struct _AtomCtrl_HiLoLeakageOffsetTable AtomCtrl_HiLoLeakageOffsetTable;
0288
0289 struct _AtomCtrl_EDCLeakgeTable
0290 {
0291     ULONG DIDT_REG[24];
0292 };
0293 typedef struct _AtomCtrl_EDCLeakgeTable AtomCtrl_EDCLeakgeTable;
0294
0295 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
0296 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
0297 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
0298 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
0299
0300 bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr);
0301 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
0302 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
0303 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
0304 extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
0305 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
0306 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
0307 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
0308 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
0309 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
0310 extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
0311 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
0312 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
0313         uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
0314 extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
0315         uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
0316 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
0317                          uint32_t clock_value,
0318                          pp_atomctrl_clock_dividers_kong *dividers);
0319 extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
0320         uint16_t end_index, uint32_t *efuse);
0321 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
0322         uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
0323 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
0324 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
0325                                 uint8_t level);
0326 extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
0327                 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
0328 extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
0329
0330 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
0331
0332 extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
0333                 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
0334                 uint16_t *load_line);
0335
0336 extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
0337                     uint16_t *vddc, uint16_t *vddci,
0338                     uint16_t virtual_voltage_id,
0339                     uint16_t efuse_voltage_id);
0340 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
0341
0342 extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
0343                             uint32_t *min_vddc);
0344
0345 extern int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
0346                               AtomCtrl_HiLoLeakageOffsetTable *table);
0347
0348 extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
0349                       AtomCtrl_EDCLeakgeTable *table,
0350                       uint16_t offset);
0351
0352 extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail);
0353 #endif
0354