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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "pp_debug.h"
0024 #include <linux/module.h>
0025 #include <linux/slab.h>
0026 #include <linux/delay.h>
0027 #include "atom.h"
0028 #include "ppatomctrl.h"
0029 #include "atombios.h"
0030 #include "cgs_common.h"
0031 #include "ppevvmath.h"
0032 
0033 #define MEM_ID_MASK           0xff000000
0034 #define MEM_ID_SHIFT          24
0035 #define CLOCK_RANGE_MASK      0x00ffffff
0036 #define CLOCK_RANGE_SHIFT     0
0037 #define LOW_NIBBLE_MASK       0xf
0038 #define DATA_EQU_PREV         0
0039 #define DATA_FROM_TABLE       4
0040 
0041 union voltage_object_info {
0042     struct _ATOM_VOLTAGE_OBJECT_INFO v1;
0043     struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
0044     struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
0045 };
0046 
0047 static int atomctrl_retrieve_ac_timing(
0048         uint8_t index,
0049         ATOM_INIT_REG_BLOCK *reg_block,
0050         pp_atomctrl_mc_reg_table *table)
0051 {
0052     uint32_t i, j;
0053     uint8_t tmem_id;
0054     ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
0055         ((uint8_t *)reg_block + (2 * sizeof(uint16_t)) + le16_to_cpu(reg_block->usRegIndexTblSize));
0056 
0057     uint8_t num_ranges = 0;
0058 
0059     while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK &&
0060             num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES) {
0061         tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
0062 
0063         if (index == tmem_id) {
0064             table->mc_reg_table_entry[num_ranges].mclk_max =
0065                 (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >>
0066                         CLOCK_RANGE_SHIFT);
0067 
0068             for (i = 0, j = 1; i < table->last; i++) {
0069                 if ((table->mc_reg_address[i].uc_pre_reg_data &
0070                             LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
0071                     table->mc_reg_table_entry[num_ranges].mc_data[i] =
0072                         (uint32_t)*((uint32_t *)reg_data + j);
0073                     j++;
0074                 } else if ((table->mc_reg_address[i].uc_pre_reg_data &
0075                             LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
0076                     table->mc_reg_table_entry[num_ranges].mc_data[i] =
0077                         table->mc_reg_table_entry[num_ranges].mc_data[i-1];
0078                 }
0079             }
0080             num_ranges++;
0081         }
0082 
0083         reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
0084             ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ;
0085     }
0086 
0087     PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK),
0088             "Invalid VramInfo table.", return -1);
0089     table->num_entries = num_ranges;
0090 
0091     return 0;
0092 }
0093 
0094 /**
0095  * atomctrl_set_mc_reg_address_table - Get memory clock AC timing registers index from VBIOS table
0096  * VBIOS set end of memory clock AC timing registers by ucPreRegDataLength bit6 = 1
0097  * @reg_block: the address ATOM_INIT_REG_BLOCK
0098  * @table: the address of MCRegTable
0099  * Return:   0
0100  */
0101 static int atomctrl_set_mc_reg_address_table(
0102         ATOM_INIT_REG_BLOCK *reg_block,
0103         pp_atomctrl_mc_reg_table *table)
0104 {
0105     uint8_t i = 0;
0106     uint8_t num_entries = (uint8_t)((le16_to_cpu(reg_block->usRegIndexTblSize))
0107             / sizeof(ATOM_INIT_REG_INDEX_FORMAT));
0108     ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
0109 
0110     num_entries--;        /* subtract 1 data end mark entry */
0111 
0112     PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE),
0113             "Invalid VramInfo table.", return -1);
0114 
0115     /* ucPreRegDataLength bit6 = 1 is the end of memory clock AC timing registers */
0116     while ((!(format->ucPreRegDataLength & ACCESS_PLACEHOLDER)) &&
0117             (i < num_entries)) {
0118         table->mc_reg_address[i].s1 =
0119             (uint16_t)(le16_to_cpu(format->usRegIndex));
0120         table->mc_reg_address[i].uc_pre_reg_data =
0121             format->ucPreRegDataLength;
0122 
0123         i++;
0124         format = (ATOM_INIT_REG_INDEX_FORMAT *)
0125             ((uint8_t *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
0126     }
0127 
0128     table->last = i;
0129     return 0;
0130 }
0131 
0132 int atomctrl_initialize_mc_reg_table(
0133         struct pp_hwmgr *hwmgr,
0134         uint8_t module_index,
0135         pp_atomctrl_mc_reg_table *table)
0136 {
0137     ATOM_VRAM_INFO_HEADER_V2_1 *vram_info;
0138     ATOM_INIT_REG_BLOCK *reg_block;
0139     int result = 0;
0140     u8 frev, crev;
0141     u16 size;
0142 
0143     vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *)
0144         smu_atom_get_data_table(hwmgr->adev,
0145                 GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
0146 
0147     if (module_index >= vram_info->ucNumOfVRAMModule) {
0148         pr_err("Invalid VramInfo table.");
0149         result = -1;
0150     } else if (vram_info->sHeader.ucTableFormatRevision < 2) {
0151         pr_err("Invalid VramInfo table.");
0152         result = -1;
0153     }
0154 
0155     if (0 == result) {
0156         reg_block = (ATOM_INIT_REG_BLOCK *)
0157             ((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));
0158         result = atomctrl_set_mc_reg_address_table(reg_block, table);
0159     }
0160 
0161     if (0 == result) {
0162         result = atomctrl_retrieve_ac_timing(module_index,
0163                     reg_block, table);
0164     }
0165 
0166     return result;
0167 }
0168 
0169 int atomctrl_initialize_mc_reg_table_v2_2(
0170         struct pp_hwmgr *hwmgr,
0171         uint8_t module_index,
0172         pp_atomctrl_mc_reg_table *table)
0173 {
0174     ATOM_VRAM_INFO_HEADER_V2_2 *vram_info;
0175     ATOM_INIT_REG_BLOCK *reg_block;
0176     int result = 0;
0177     u8 frev, crev;
0178     u16 size;
0179 
0180     vram_info = (ATOM_VRAM_INFO_HEADER_V2_2 *)
0181         smu_atom_get_data_table(hwmgr->adev,
0182                 GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev);
0183 
0184     if (module_index >= vram_info->ucNumOfVRAMModule) {
0185         pr_err("Invalid VramInfo table.");
0186         result = -1;
0187     } else if (vram_info->sHeader.ucTableFormatRevision < 2) {
0188         pr_err("Invalid VramInfo table.");
0189         result = -1;
0190     }
0191 
0192     if (0 == result) {
0193         reg_block = (ATOM_INIT_REG_BLOCK *)
0194             ((uint8_t *)vram_info + le16_to_cpu(vram_info->usMemClkPatchTblOffset));
0195         result = atomctrl_set_mc_reg_address_table(reg_block, table);
0196     }
0197 
0198     if (0 == result) {
0199         result = atomctrl_retrieve_ac_timing(module_index,
0200                     reg_block, table);
0201     }
0202 
0203     return result;
0204 }
0205 
0206 /*
0207  * Set DRAM timings based on engine clock and memory clock.
0208  */
0209 int atomctrl_set_engine_dram_timings_rv770(
0210         struct pp_hwmgr *hwmgr,
0211         uint32_t engine_clock,
0212         uint32_t memory_clock)
0213 {
0214     struct amdgpu_device *adev = hwmgr->adev;
0215 
0216     SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters;
0217 
0218     /* They are both in 10KHz Units. */
0219     engine_clock_parameters.ulTargetEngineClock =
0220         cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) |
0221                 ((COMPUTE_ENGINE_PLL_PARAM << 24)));
0222 
0223     /* in 10 khz units.*/
0224     engine_clock_parameters.sReserved.ulClock =
0225         cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK);
0226 
0227     return amdgpu_atom_execute_table(adev->mode_info.atom_context,
0228             GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
0229             (uint32_t *)&engine_clock_parameters);
0230 }
0231 
0232 /*
0233  * Private Function to get the PowerPlay Table Address.
0234  * WARNING: The tabled returned by this function is in
0235  * dynamically allocated memory.
0236  * The caller has to release if by calling kfree.
0237  */
0238 static ATOM_VOLTAGE_OBJECT_INFO *get_voltage_info_table(void *device)
0239 {
0240     int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
0241     u8 frev, crev;
0242     u16 size;
0243     union voltage_object_info *voltage_info;
0244 
0245     voltage_info = (union voltage_object_info *)
0246         smu_atom_get_data_table(device, index,
0247             &size, &frev, &crev);
0248 
0249     if (voltage_info != NULL)
0250         return (ATOM_VOLTAGE_OBJECT_INFO *) &(voltage_info->v3);
0251     else
0252         return NULL;
0253 }
0254 
0255 static const ATOM_VOLTAGE_OBJECT_V3 *atomctrl_lookup_voltage_type_v3(
0256         const ATOM_VOLTAGE_OBJECT_INFO_V3_1 * voltage_object_info_table,
0257         uint8_t voltage_type, uint8_t voltage_mode)
0258 {
0259     unsigned int size = le16_to_cpu(voltage_object_info_table->sHeader.usStructureSize);
0260     unsigned int offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
0261     uint8_t *start = (uint8_t *)voltage_object_info_table;
0262 
0263     while (offset < size) {
0264         const ATOM_VOLTAGE_OBJECT_V3 *voltage_object =
0265             (const ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
0266 
0267         if (voltage_type == voltage_object->asGpioVoltageObj.sHeader.ucVoltageType &&
0268             voltage_mode == voltage_object->asGpioVoltageObj.sHeader.ucVoltageMode)
0269             return voltage_object;
0270 
0271         offset += le16_to_cpu(voltage_object->asGpioVoltageObj.sHeader.usSize);
0272     }
0273 
0274     return NULL;
0275 }
0276 
0277 /**
0278  * atomctrl_get_memory_pll_dividers_si
0279  *
0280  * @hwmgr:           input parameter: pointer to HwMgr
0281  * @clock_value:     input parameter: memory clock
0282  * @mpll_param:      output parameter: memory clock parameters
0283  * @strobe_mode:     input parameter: 1 for strobe mode,  0 for performance mode
0284  */
0285 int atomctrl_get_memory_pll_dividers_si(
0286         struct pp_hwmgr *hwmgr,
0287         uint32_t clock_value,
0288         pp_atomctrl_memory_clock_param *mpll_param,
0289         bool strobe_mode)
0290 {
0291     struct amdgpu_device *adev = hwmgr->adev;
0292     COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters;
0293     int result;
0294 
0295     mpll_parameters.ulClock = cpu_to_le32(clock_value);
0296     mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0);
0297 
0298     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0299          GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
0300         (uint32_t *)&mpll_parameters);
0301 
0302     if (0 == result) {
0303         mpll_param->mpll_fb_divider.clk_frac =
0304             le16_to_cpu(mpll_parameters.ulFbDiv.usFbDivFrac);
0305         mpll_param->mpll_fb_divider.cl_kf =
0306             le16_to_cpu(mpll_parameters.ulFbDiv.usFbDiv);
0307         mpll_param->mpll_post_divider =
0308             (uint32_t)mpll_parameters.ucPostDiv;
0309         mpll_param->vco_mode =
0310             (uint32_t)(mpll_parameters.ucPllCntlFlag &
0311                     MPLL_CNTL_FLAG_VCO_MODE_MASK);
0312         mpll_param->yclk_sel =
0313             (uint32_t)((mpll_parameters.ucPllCntlFlag &
0314                         MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0);
0315         mpll_param->qdr =
0316             (uint32_t)((mpll_parameters.ucPllCntlFlag &
0317                         MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0);
0318         mpll_param->half_rate =
0319             (uint32_t)((mpll_parameters.ucPllCntlFlag &
0320                         MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0);
0321         mpll_param->dll_speed =
0322             (uint32_t)(mpll_parameters.ucDllSpeed);
0323         mpll_param->bw_ctrl =
0324             (uint32_t)(mpll_parameters.ucBWCntl);
0325     }
0326 
0327     return result;
0328 }
0329 
0330 /**
0331  * atomctrl_get_memory_pll_dividers_vi
0332  *
0333  * @hwmgr:                 input parameter: pointer to HwMgr
0334  * @clock_value:           input parameter: memory clock
0335  * @mpll_param:            output parameter: memory clock parameters
0336  */
0337 int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
0338         uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param)
0339 {
0340     struct amdgpu_device *adev = hwmgr->adev;
0341     COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters;
0342     int result;
0343 
0344     mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
0345 
0346     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0347             GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
0348             (uint32_t *)&mpll_parameters);
0349 
0350     if (!result)
0351         mpll_param->mpll_post_divider =
0352                 (uint32_t)mpll_parameters.ulClock.ucPostDiv;
0353 
0354     return result;
0355 }
0356 
0357 int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
0358                     uint32_t clock_value,
0359                     pp_atomctrl_memory_clock_param_ai *mpll_param)
0360 {
0361     struct amdgpu_device *adev = hwmgr->adev;
0362     COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0};
0363     int result;
0364 
0365     mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
0366 
0367     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0368             GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
0369             (uint32_t *)&mpll_parameters);
0370 
0371     /* VEGAM's mpll takes sometime to finish computing */
0372     udelay(10);
0373 
0374     if (!result) {
0375         mpll_param->ulMclk_fcw_int =
0376             le16_to_cpu(mpll_parameters.usMclk_fcw_int);
0377         mpll_param->ulMclk_fcw_frac =
0378             le16_to_cpu(mpll_parameters.usMclk_fcw_frac);
0379         mpll_param->ulClock =
0380             le32_to_cpu(mpll_parameters.ulClock.ulClock);
0381         mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
0382     }
0383 
0384     return result;
0385 }
0386 
0387 int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
0388                       uint32_t clock_value,
0389                       pp_atomctrl_clock_dividers_kong *dividers)
0390 {
0391     struct amdgpu_device *adev = hwmgr->adev;
0392     COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters;
0393     int result;
0394 
0395     pll_parameters.ulClock = cpu_to_le32(clock_value);
0396 
0397     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0398          GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
0399         (uint32_t *)&pll_parameters);
0400 
0401     if (0 == result) {
0402         dividers->pll_post_divider = pll_parameters.ucPostDiv;
0403         dividers->real_clock = le32_to_cpu(pll_parameters.ulClock);
0404     }
0405 
0406     return result;
0407 }
0408 
0409 int atomctrl_get_engine_pll_dividers_vi(
0410         struct pp_hwmgr *hwmgr,
0411         uint32_t clock_value,
0412         pp_atomctrl_clock_dividers_vi *dividers)
0413 {
0414     struct amdgpu_device *adev = hwmgr->adev;
0415     COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
0416     int result;
0417 
0418     pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
0419     pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
0420 
0421     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0422          GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
0423         (uint32_t *)&pll_patameters);
0424 
0425     if (0 == result) {
0426         dividers->pll_post_divider =
0427             pll_patameters.ulClock.ucPostDiv;
0428         dividers->real_clock =
0429             le32_to_cpu(pll_patameters.ulClock.ulClock);
0430 
0431         dividers->ul_fb_div.ul_fb_div_frac =
0432             le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
0433         dividers->ul_fb_div.ul_fb_div =
0434             le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv);
0435 
0436         dividers->uc_pll_ref_div =
0437             pll_patameters.ucPllRefDiv;
0438         dividers->uc_pll_post_div =
0439             pll_patameters.ucPllPostDiv;
0440         dividers->uc_pll_cntl_flag =
0441             pll_patameters.ucPllCntlFlag;
0442     }
0443 
0444     return result;
0445 }
0446 
0447 int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
0448         uint32_t clock_value,
0449         pp_atomctrl_clock_dividers_ai *dividers)
0450 {
0451     struct amdgpu_device *adev = hwmgr->adev;
0452     COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters;
0453     int result;
0454 
0455     pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
0456     pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK;
0457 
0458     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0459          GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
0460         (uint32_t *)&pll_patameters);
0461 
0462     if (0 == result) {
0463         dividers->usSclk_fcw_frac     = le16_to_cpu(pll_patameters.usSclk_fcw_frac);
0464         dividers->usSclk_fcw_int      = le16_to_cpu(pll_patameters.usSclk_fcw_int);
0465         dividers->ucSclkPostDiv       = pll_patameters.ucSclkPostDiv;
0466         dividers->ucSclkVcoMode       = pll_patameters.ucSclkVcoMode;
0467         dividers->ucSclkPllRange      = pll_patameters.ucSclkPllRange;
0468         dividers->ucSscEnable         = pll_patameters.ucSscEnable;
0469         dividers->usSsc_fcw1_frac     = le16_to_cpu(pll_patameters.usSsc_fcw1_frac);
0470         dividers->usSsc_fcw1_int      = le16_to_cpu(pll_patameters.usSsc_fcw1_int);
0471         dividers->usPcc_fcw_int       = le16_to_cpu(pll_patameters.usPcc_fcw_int);
0472         dividers->usSsc_fcw_slew_frac = le16_to_cpu(pll_patameters.usSsc_fcw_slew_frac);
0473         dividers->usPcc_fcw_slew_frac = le16_to_cpu(pll_patameters.usPcc_fcw_slew_frac);
0474     }
0475     return result;
0476 }
0477 
0478 int atomctrl_get_dfs_pll_dividers_vi(
0479         struct pp_hwmgr *hwmgr,
0480         uint32_t clock_value,
0481         pp_atomctrl_clock_dividers_vi *dividers)
0482 {
0483     struct amdgpu_device *adev = hwmgr->adev;
0484     COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters;
0485     int result;
0486 
0487     pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value);
0488     pll_patameters.ulClock.ucPostDiv =
0489         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK;
0490 
0491     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0492          GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL),
0493         (uint32_t *)&pll_patameters);
0494 
0495     if (0 == result) {
0496         dividers->pll_post_divider =
0497             pll_patameters.ulClock.ucPostDiv;
0498         dividers->real_clock =
0499             le32_to_cpu(pll_patameters.ulClock.ulClock);
0500 
0501         dividers->ul_fb_div.ul_fb_div_frac =
0502             le16_to_cpu(pll_patameters.ulFbDiv.usFbDivFrac);
0503         dividers->ul_fb_div.ul_fb_div =
0504             le16_to_cpu(pll_patameters.ulFbDiv.usFbDiv);
0505 
0506         dividers->uc_pll_ref_div =
0507             pll_patameters.ucPllRefDiv;
0508         dividers->uc_pll_post_div =
0509             pll_patameters.ucPllPostDiv;
0510         dividers->uc_pll_cntl_flag =
0511             pll_patameters.ucPllCntlFlag;
0512     }
0513 
0514     return result;
0515 }
0516 
0517 /*
0518  * Get the reference clock in 10KHz
0519  */
0520 uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
0521 {
0522     ATOM_FIRMWARE_INFO *fw_info;
0523     u8 frev, crev;
0524     u16 size;
0525     uint32_t clock;
0526 
0527     fw_info = (ATOM_FIRMWARE_INFO *)
0528         smu_atom_get_data_table(hwmgr->adev,
0529             GetIndexIntoMasterTable(DATA, FirmwareInfo),
0530             &size, &frev, &crev);
0531 
0532     if (fw_info == NULL)
0533         clock = 2700;
0534     else
0535         clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));
0536 
0537     return clock;
0538 }
0539 
0540 /*
0541  * Returns true if the given voltage type is controlled by GPIO pins.
0542  * voltage_type is one of SET_VOLTAGE_TYPE_ASIC_VDDC,
0543  * SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
0544  * voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
0545  */
0546 bool atomctrl_is_voltage_controlled_by_gpio_v3(
0547         struct pp_hwmgr *hwmgr,
0548         uint8_t voltage_type,
0549         uint8_t voltage_mode)
0550 {
0551     ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
0552         (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
0553     bool ret;
0554 
0555     PP_ASSERT_WITH_CODE((NULL != voltage_info),
0556             "Could not find Voltage Table in BIOS.", return false;);
0557 
0558     ret = (NULL != atomctrl_lookup_voltage_type_v3
0559             (voltage_info, voltage_type, voltage_mode)) ? true : false;
0560 
0561     return ret;
0562 }
0563 
0564 int atomctrl_get_voltage_table_v3(
0565         struct pp_hwmgr *hwmgr,
0566         uint8_t voltage_type,
0567         uint8_t voltage_mode,
0568         pp_atomctrl_voltage_table *voltage_table)
0569 {
0570     ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
0571         (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
0572     const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
0573     unsigned int i;
0574 
0575     PP_ASSERT_WITH_CODE((NULL != voltage_info),
0576             "Could not find Voltage Table in BIOS.", return -1;);
0577 
0578     voltage_object = atomctrl_lookup_voltage_type_v3
0579         (voltage_info, voltage_type, voltage_mode);
0580 
0581     if (voltage_object == NULL)
0582         return -1;
0583 
0584     PP_ASSERT_WITH_CODE(
0585             (voltage_object->asGpioVoltageObj.ucGpioEntryNum <=
0586             PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES),
0587             "Too many voltage entries!",
0588             return -1;
0589             );
0590 
0591     for (i = 0; i < voltage_object->asGpioVoltageObj.ucGpioEntryNum; i++) {
0592         voltage_table->entries[i].value =
0593             le16_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].usVoltageValue);
0594         voltage_table->entries[i].smio_low =
0595             le32_to_cpu(voltage_object->asGpioVoltageObj.asVolGpioLut[i].ulVoltageId);
0596     }
0597 
0598     voltage_table->mask_low    =
0599         le32_to_cpu(voltage_object->asGpioVoltageObj.ulGpioMaskVal);
0600     voltage_table->count      =
0601         voltage_object->asGpioVoltageObj.ucGpioEntryNum;
0602     voltage_table->phase_delay =
0603         voltage_object->asGpioVoltageObj.ucPhaseDelay;
0604 
0605     return 0;
0606 }
0607 
0608 static bool atomctrl_lookup_gpio_pin(
0609         ATOM_GPIO_PIN_LUT * gpio_lookup_table,
0610         const uint32_t pinId,
0611         pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
0612 {
0613     unsigned int size = le16_to_cpu(gpio_lookup_table->sHeader.usStructureSize);
0614     unsigned int offset = offsetof(ATOM_GPIO_PIN_LUT, asGPIO_Pin[0]);
0615     uint8_t *start = (uint8_t *)gpio_lookup_table;
0616 
0617     while (offset < size) {
0618         const ATOM_GPIO_PIN_ASSIGNMENT *pin_assignment =
0619             (const ATOM_GPIO_PIN_ASSIGNMENT *)(start + offset);
0620 
0621         if (pinId == pin_assignment->ucGPIO_ID) {
0622             gpio_pin_assignment->uc_gpio_pin_bit_shift =
0623                 pin_assignment->ucGpioPinBitShift;
0624             gpio_pin_assignment->us_gpio_pin_aindex =
0625                 le16_to_cpu(pin_assignment->usGpioPin_AIndex);
0626             return true;
0627         }
0628 
0629         offset += offsetof(ATOM_GPIO_PIN_ASSIGNMENT, ucGPIO_ID) + 1;
0630     }
0631 
0632     return false;
0633 }
0634 
0635 /*
0636  * Private Function to get the PowerPlay Table Address.
0637  * WARNING: The tabled returned by this function is in
0638  * dynamically allocated memory.
0639  * The caller has to release if by calling kfree.
0640  */
0641 static ATOM_GPIO_PIN_LUT *get_gpio_lookup_table(void *device)
0642 {
0643     u8 frev, crev;
0644     u16 size;
0645     void *table_address;
0646 
0647     table_address = (ATOM_GPIO_PIN_LUT *)
0648         smu_atom_get_data_table(device,
0649                 GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT),
0650                 &size, &frev, &crev);
0651 
0652     PP_ASSERT_WITH_CODE((NULL != table_address),
0653             "Error retrieving BIOS Table Address!", return NULL;);
0654 
0655     return (ATOM_GPIO_PIN_LUT *)table_address;
0656 }
0657 
0658 /*
0659  * Returns 1 if the given pin id find in lookup table.
0660  */
0661 bool atomctrl_get_pp_assign_pin(
0662         struct pp_hwmgr *hwmgr,
0663         const uint32_t pinId,
0664         pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment)
0665 {
0666     bool bRet = false;
0667     ATOM_GPIO_PIN_LUT *gpio_lookup_table =
0668         get_gpio_lookup_table(hwmgr->adev);
0669 
0670     PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table),
0671             "Could not find GPIO lookup Table in BIOS.", return false);
0672 
0673     bRet = atomctrl_lookup_gpio_pin(gpio_lookup_table, pinId,
0674         gpio_pin_assignment);
0675 
0676     return bRet;
0677 }
0678 
0679 int atomctrl_calculate_voltage_evv_on_sclk(
0680         struct pp_hwmgr *hwmgr,
0681         uint8_t voltage_type,
0682         uint32_t sclk,
0683         uint16_t virtual_voltage_Id,
0684         uint16_t *voltage,
0685         uint16_t dpm_level,
0686         bool debug)
0687 {
0688     ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo;
0689     struct amdgpu_device *adev = hwmgr->adev;
0690     EFUSE_LINEAR_FUNC_PARAM sRO_fuse;
0691     EFUSE_LINEAR_FUNC_PARAM sCACm_fuse;
0692     EFUSE_LINEAR_FUNC_PARAM sCACb_fuse;
0693     EFUSE_LOGISTIC_FUNC_PARAM sKt_Beta_fuse;
0694     EFUSE_LOGISTIC_FUNC_PARAM sKv_m_fuse;
0695     EFUSE_LOGISTIC_FUNC_PARAM sKv_b_fuse;
0696     EFUSE_INPUT_PARAMETER sInput_FuseValues;
0697     READ_EFUSE_VALUE_PARAMETER sOutput_FuseValues;
0698 
0699     uint32_t ul_RO_fused, ul_CACb_fused, ul_CACm_fused, ul_Kt_Beta_fused, ul_Kv_m_fused, ul_Kv_b_fused;
0700     fInt fSM_A0, fSM_A1, fSM_A2, fSM_A3, fSM_A4, fSM_A5, fSM_A6, fSM_A7;
0701     fInt fMargin_RO_a, fMargin_RO_b, fMargin_RO_c, fMargin_fixed, fMargin_FMAX_mean, fMargin_Plat_mean, fMargin_FMAX_sigma, fMargin_Plat_sigma, fMargin_DC_sigma;
0702     fInt fLkg_FT, repeat;
0703     fInt fMicro_FMAX, fMicro_CR, fSigma_FMAX, fSigma_CR, fSigma_DC, fDC_SCLK, fSquared_Sigma_DC, fSquared_Sigma_CR, fSquared_Sigma_FMAX;
0704     fInt fRLL_LoadLine, fDerateTDP, fVDDC_base, fA_Term, fC_Term, fB_Term, fRO_DC_margin;
0705     fInt fRO_fused, fCACm_fused, fCACb_fused, fKv_m_fused, fKv_b_fused, fKt_Beta_fused, fFT_Lkg_V0NORM;
0706     fInt fSclk_margin, fSclk, fEVV_V;
0707     fInt fV_min, fV_max, fT_prod, fLKG_Factor, fT_FT, fV_FT, fV_x, fTDP_Power, fTDP_Power_right, fTDP_Power_left, fTDP_Current, fV_NL;
0708     uint32_t ul_FT_Lkg_V0NORM;
0709     fInt fLn_MaxDivMin, fMin, fAverage, fRange;
0710     fInt fRoots[2];
0711     fInt fStepSize = GetScaledFraction(625, 100000);
0712 
0713     int result;
0714 
0715     getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *)
0716             smu_atom_get_data_table(hwmgr->adev,
0717                     GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
0718                     NULL, NULL, NULL);
0719 
0720     if (!getASICProfilingInfo)
0721         return -1;
0722 
0723     if (getASICProfilingInfo->asHeader.ucTableFormatRevision < 3 ||
0724         (getASICProfilingInfo->asHeader.ucTableFormatRevision == 3 &&
0725          getASICProfilingInfo->asHeader.ucTableContentRevision < 4))
0726         return -1;
0727 
0728     /*-----------------------------------------------------------
0729      *GETTING MULTI-STEP PARAMETERS RELATED TO CURRENT DPM LEVEL
0730      *-----------------------------------------------------------
0731      */
0732     fRLL_LoadLine = Divide(getASICProfilingInfo->ulLoadLineSlop, 1000);
0733 
0734     switch (dpm_level) {
0735     case 1:
0736         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM1), 1000);
0737         break;
0738     case 2:
0739         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM2), 1000);
0740         break;
0741     case 3:
0742         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM3), 1000);
0743         break;
0744     case 4:
0745         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM4), 1000);
0746         break;
0747     case 5:
0748         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM5), 1000);
0749         break;
0750     case 6:
0751         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM6), 1000);
0752         break;
0753     case 7:
0754         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM7), 1000);
0755         break;
0756     default:
0757         pr_err("DPM Level not supported\n");
0758         fDerateTDP = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulTdpDerateDPM0), 1000);
0759     }
0760 
0761     /*-------------------------
0762      * DECODING FUSE VALUES
0763      * ------------------------
0764      */
0765     /*Decode RO_Fused*/
0766     sRO_fuse = getASICProfilingInfo->sRoFuse;
0767 
0768     sInput_FuseValues.usEfuseIndex = sRO_fuse.usEfuseIndex;
0769     sInput_FuseValues.ucBitShift = sRO_fuse.ucEfuseBitLSB;
0770     sInput_FuseValues.ucBitLength = sRO_fuse.ucEfuseLength;
0771 
0772     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0773 
0774     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0775             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0776             (uint32_t *)&sOutput_FuseValues);
0777 
0778     if (result)
0779         return result;
0780 
0781     /* Finally, the actual fuse value */
0782     ul_RO_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0783     fMin = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseMin), 1);
0784     fRange = GetScaledFraction(le32_to_cpu(sRO_fuse.ulEfuseEncodeRange), 1);
0785     fRO_fused = fDecodeLinearFuse(ul_RO_fused, fMin, fRange, sRO_fuse.ucEfuseLength);
0786 
0787     sCACm_fuse = getASICProfilingInfo->sCACm;
0788 
0789     sInput_FuseValues.usEfuseIndex = sCACm_fuse.usEfuseIndex;
0790     sInput_FuseValues.ucBitShift = sCACm_fuse.ucEfuseBitLSB;
0791     sInput_FuseValues.ucBitLength = sCACm_fuse.ucEfuseLength;
0792 
0793     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0794 
0795     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0796             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0797             (uint32_t *)&sOutput_FuseValues);
0798 
0799     if (result)
0800         return result;
0801 
0802     ul_CACm_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0803     fMin = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseMin), 1000);
0804     fRange = GetScaledFraction(le32_to_cpu(sCACm_fuse.ulEfuseEncodeRange), 1000);
0805 
0806     fCACm_fused = fDecodeLinearFuse(ul_CACm_fused, fMin, fRange, sCACm_fuse.ucEfuseLength);
0807 
0808     sCACb_fuse = getASICProfilingInfo->sCACb;
0809 
0810     sInput_FuseValues.usEfuseIndex = sCACb_fuse.usEfuseIndex;
0811     sInput_FuseValues.ucBitShift = sCACb_fuse.ucEfuseBitLSB;
0812     sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength;
0813     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0814 
0815     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0816             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0817             (uint32_t *)&sOutput_FuseValues);
0818 
0819     if (result)
0820         return result;
0821 
0822     ul_CACb_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0823     fMin = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseMin), 1000);
0824     fRange = GetScaledFraction(le32_to_cpu(sCACb_fuse.ulEfuseEncodeRange), 1000);
0825 
0826     fCACb_fused = fDecodeLinearFuse(ul_CACb_fused, fMin, fRange, sCACb_fuse.ucEfuseLength);
0827 
0828     sKt_Beta_fuse = getASICProfilingInfo->sKt_b;
0829 
0830     sInput_FuseValues.usEfuseIndex = sKt_Beta_fuse.usEfuseIndex;
0831     sInput_FuseValues.ucBitShift = sKt_Beta_fuse.ucEfuseBitLSB;
0832     sInput_FuseValues.ucBitLength = sKt_Beta_fuse.ucEfuseLength;
0833 
0834     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0835 
0836     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0837             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0838             (uint32_t *)&sOutput_FuseValues);
0839 
0840     if (result)
0841         return result;
0842 
0843     ul_Kt_Beta_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0844     fAverage = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeAverage), 1000);
0845     fRange = GetScaledFraction(le32_to_cpu(sKt_Beta_fuse.ulEfuseEncodeRange), 1000);
0846 
0847     fKt_Beta_fused = fDecodeLogisticFuse(ul_Kt_Beta_fused,
0848             fAverage, fRange, sKt_Beta_fuse.ucEfuseLength);
0849 
0850     sKv_m_fuse = getASICProfilingInfo->sKv_m;
0851 
0852     sInput_FuseValues.usEfuseIndex = sKv_m_fuse.usEfuseIndex;
0853     sInput_FuseValues.ucBitShift = sKv_m_fuse.ucEfuseBitLSB;
0854     sInput_FuseValues.ucBitLength = sKv_m_fuse.ucEfuseLength;
0855 
0856     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0857 
0858     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0859             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0860             (uint32_t *)&sOutput_FuseValues);
0861     if (result)
0862         return result;
0863 
0864     ul_Kv_m_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0865     fAverage = GetScaledFraction(le32_to_cpu(sKv_m_fuse.ulEfuseEncodeAverage), 1000);
0866     fRange = GetScaledFraction((le32_to_cpu(sKv_m_fuse.ulEfuseEncodeRange) & 0x7fffffff), 1000);
0867     fRange = fMultiply(fRange, ConvertToFraction(-1));
0868 
0869     fKv_m_fused = fDecodeLogisticFuse(ul_Kv_m_fused,
0870             fAverage, fRange, sKv_m_fuse.ucEfuseLength);
0871 
0872     sKv_b_fuse = getASICProfilingInfo->sKv_b;
0873 
0874     sInput_FuseValues.usEfuseIndex = sKv_b_fuse.usEfuseIndex;
0875     sInput_FuseValues.ucBitShift = sKv_b_fuse.ucEfuseBitLSB;
0876     sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength;
0877     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0878 
0879     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0880             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0881             (uint32_t *)&sOutput_FuseValues);
0882 
0883     if (result)
0884         return result;
0885 
0886     ul_Kv_b_fused = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0887     fAverage = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeAverage), 1000);
0888     fRange = GetScaledFraction(le32_to_cpu(sKv_b_fuse.ulEfuseEncodeRange), 1000);
0889 
0890     fKv_b_fused = fDecodeLogisticFuse(ul_Kv_b_fused,
0891             fAverage, fRange, sKv_b_fuse.ucEfuseLength);
0892 
0893     /* Decoding the Leakage - No special struct container */
0894     /*
0895      * usLkgEuseIndex=56
0896      * ucLkgEfuseBitLSB=6
0897      * ucLkgEfuseLength=10
0898      * ulLkgEncodeLn_MaxDivMin=69077
0899      * ulLkgEncodeMax=1000000
0900      * ulLkgEncodeMin=1000
0901      * ulEfuseLogisticAlpha=13
0902      */
0903 
0904     sInput_FuseValues.usEfuseIndex = getASICProfilingInfo->usLkgEuseIndex;
0905     sInput_FuseValues.ucBitShift = getASICProfilingInfo->ucLkgEfuseBitLSB;
0906     sInput_FuseValues.ucBitLength = getASICProfilingInfo->ucLkgEfuseLength;
0907 
0908     sOutput_FuseValues.sEfuse = sInput_FuseValues;
0909 
0910     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
0911             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
0912             (uint32_t *)&sOutput_FuseValues);
0913 
0914     if (result)
0915         return result;
0916 
0917     ul_FT_Lkg_V0NORM = le32_to_cpu(sOutput_FuseValues.ulEfuseValue);
0918     fLn_MaxDivMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeLn_MaxDivMin), 10000);
0919     fMin = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLkgEncodeMin), 10000);
0920 
0921     fFT_Lkg_V0NORM = fDecodeLeakageID(ul_FT_Lkg_V0NORM,
0922             fLn_MaxDivMin, fMin, getASICProfilingInfo->ucLkgEfuseLength);
0923     fLkg_FT = fFT_Lkg_V0NORM;
0924 
0925     /*-------------------------------------------
0926      * PART 2 - Grabbing all required values
0927      *-------------------------------------------
0928      */
0929     fSM_A0 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A0), 1000000),
0930             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A0_sign)));
0931     fSM_A1 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A1), 1000000),
0932             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A1_sign)));
0933     fSM_A2 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A2), 100000),
0934             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A2_sign)));
0935     fSM_A3 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A3), 1000000),
0936             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A3_sign)));
0937     fSM_A4 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A4), 1000000),
0938             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A4_sign)));
0939     fSM_A5 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A5), 1000),
0940             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A5_sign)));
0941     fSM_A6 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A6), 1000),
0942             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A6_sign)));
0943     fSM_A7 = fMultiply(GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulSM_A7), 1000),
0944             ConvertToFraction(uPow(-1, getASICProfilingInfo->ucSM_A7_sign)));
0945 
0946     fMargin_RO_a = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_a));
0947     fMargin_RO_b = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_b));
0948     fMargin_RO_c = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_RO_c));
0949 
0950     fMargin_fixed = ConvertToFraction(le32_to_cpu(getASICProfilingInfo->ulMargin_fixed));
0951 
0952     fMargin_FMAX_mean = GetScaledFraction(
0953         le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_mean), 10000);
0954     fMargin_Plat_mean = GetScaledFraction(
0955         le32_to_cpu(getASICProfilingInfo->ulMargin_plat_mean), 10000);
0956     fMargin_FMAX_sigma = GetScaledFraction(
0957         le32_to_cpu(getASICProfilingInfo->ulMargin_Fmax_sigma), 10000);
0958     fMargin_Plat_sigma = GetScaledFraction(
0959         le32_to_cpu(getASICProfilingInfo->ulMargin_plat_sigma), 10000);
0960 
0961     fMargin_DC_sigma = GetScaledFraction(
0962         le32_to_cpu(getASICProfilingInfo->ulMargin_DC_sigma), 100);
0963     fMargin_DC_sigma = fDivide(fMargin_DC_sigma, ConvertToFraction(1000));
0964 
0965     fCACm_fused = fDivide(fCACm_fused, ConvertToFraction(100));
0966     fCACb_fused = fDivide(fCACb_fused, ConvertToFraction(100));
0967     fKt_Beta_fused = fDivide(fKt_Beta_fused, ConvertToFraction(100));
0968     fKv_m_fused =  fNegate(fDivide(fKv_m_fused, ConvertToFraction(100)));
0969     fKv_b_fused = fDivide(fKv_b_fused, ConvertToFraction(10));
0970 
0971     fSclk = GetScaledFraction(sclk, 100);
0972 
0973     fV_max = fDivide(GetScaledFraction(
0974                  le32_to_cpu(getASICProfilingInfo->ulMaxVddc), 1000), ConvertToFraction(4));
0975     fT_prod = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulBoardCoreTemp), 10);
0976     fLKG_Factor = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulEvvLkgFactor), 100);
0977     fT_FT = GetScaledFraction(le32_to_cpu(getASICProfilingInfo->ulLeakageTemp), 10);
0978     fV_FT = fDivide(GetScaledFraction(
0979                 le32_to_cpu(getASICProfilingInfo->ulLeakageVoltage), 1000), ConvertToFraction(4));
0980     fV_min = fDivide(GetScaledFraction(
0981                  le32_to_cpu(getASICProfilingInfo->ulMinVddc), 1000), ConvertToFraction(4));
0982 
0983     /*-----------------------
0984      * PART 3
0985      *-----------------------
0986      */
0987 
0988     fA_Term = fAdd(fMargin_RO_a, fAdd(fMultiply(fSM_A4, fSclk), fSM_A5));
0989     fB_Term = fAdd(fAdd(fMultiply(fSM_A2, fSclk), fSM_A6), fMargin_RO_b);
0990     fC_Term = fAdd(fMargin_RO_c,
0991             fAdd(fMultiply(fSM_A0, fLkg_FT),
0992             fAdd(fMultiply(fSM_A1, fMultiply(fLkg_FT, fSclk)),
0993             fAdd(fMultiply(fSM_A3, fSclk),
0994             fSubtract(fSM_A7, fRO_fused)))));
0995 
0996     fVDDC_base = fSubtract(fRO_fused,
0997             fSubtract(fMargin_RO_c,
0998                     fSubtract(fSM_A3, fMultiply(fSM_A1, fSclk))));
0999     fVDDC_base = fDivide(fVDDC_base, fAdd(fMultiply(fSM_A0, fSclk), fSM_A2));
1000 
1001     repeat = fSubtract(fVDDC_base,
1002             fDivide(fMargin_DC_sigma, ConvertToFraction(1000)));
1003 
1004     fRO_DC_margin = fAdd(fMultiply(fMargin_RO_a,
1005             fGetSquare(repeat)),
1006             fAdd(fMultiply(fMargin_RO_b, repeat),
1007             fMargin_RO_c));
1008 
1009     fDC_SCLK = fSubtract(fRO_fused,
1010             fSubtract(fRO_DC_margin,
1011             fSubtract(fSM_A3,
1012             fMultiply(fSM_A2, repeat))));
1013     fDC_SCLK = fDivide(fDC_SCLK, fAdd(fMultiply(fSM_A0, repeat), fSM_A1));
1014 
1015     fSigma_DC = fSubtract(fSclk, fDC_SCLK);
1016 
1017     fMicro_FMAX = fMultiply(fSclk, fMargin_FMAX_mean);
1018     fMicro_CR = fMultiply(fSclk, fMargin_Plat_mean);
1019     fSigma_FMAX = fMultiply(fSclk, fMargin_FMAX_sigma);
1020     fSigma_CR = fMultiply(fSclk, fMargin_Plat_sigma);
1021 
1022     fSquared_Sigma_DC = fGetSquare(fSigma_DC);
1023     fSquared_Sigma_CR = fGetSquare(fSigma_CR);
1024     fSquared_Sigma_FMAX = fGetSquare(fSigma_FMAX);
1025 
1026     fSclk_margin = fAdd(fMicro_FMAX,
1027             fAdd(fMicro_CR,
1028             fAdd(fMargin_fixed,
1029             fSqrt(fAdd(fSquared_Sigma_FMAX,
1030             fAdd(fSquared_Sigma_DC, fSquared_Sigma_CR))))));
1031     /*
1032      fA_Term = fSM_A4 * (fSclk + fSclk_margin) + fSM_A5;
1033      fB_Term = fSM_A2 * (fSclk + fSclk_margin) + fSM_A6;
1034      fC_Term = fRO_DC_margin + fSM_A0 * fLkg_FT + fSM_A1 * fLkg_FT * (fSclk + fSclk_margin) + fSM_A3 * (fSclk + fSclk_margin) + fSM_A7 - fRO_fused;
1035      */
1036 
1037     fA_Term = fAdd(fMultiply(fSM_A4, fAdd(fSclk, fSclk_margin)), fSM_A5);
1038     fB_Term = fAdd(fMultiply(fSM_A2, fAdd(fSclk, fSclk_margin)), fSM_A6);
1039     fC_Term = fAdd(fRO_DC_margin,
1040             fAdd(fMultiply(fSM_A0, fLkg_FT),
1041             fAdd(fMultiply(fMultiply(fSM_A1, fLkg_FT),
1042             fAdd(fSclk, fSclk_margin)),
1043             fAdd(fMultiply(fSM_A3,
1044             fAdd(fSclk, fSclk_margin)),
1045             fSubtract(fSM_A7, fRO_fused)))));
1046 
1047     SolveQuadracticEqn(fA_Term, fB_Term, fC_Term, fRoots);
1048 
1049     if (GreaterThan(fRoots[0], fRoots[1]))
1050         fEVV_V = fRoots[1];
1051     else
1052         fEVV_V = fRoots[0];
1053 
1054     if (GreaterThan(fV_min, fEVV_V))
1055         fEVV_V = fV_min;
1056     else if (GreaterThan(fEVV_V, fV_max))
1057         fEVV_V = fSubtract(fV_max, fStepSize);
1058 
1059     fEVV_V = fRoundUpByStepSize(fEVV_V, fStepSize, 0);
1060 
1061     /*-----------------
1062      * PART 4
1063      *-----------------
1064      */
1065 
1066     fV_x = fV_min;
1067 
1068     while (GreaterThan(fAdd(fV_max, fStepSize), fV_x)) {
1069         fTDP_Power_left = fMultiply(fMultiply(fMultiply(fAdd(
1070                 fMultiply(fCACm_fused, fV_x), fCACb_fused), fSclk),
1071                 fGetSquare(fV_x)), fDerateTDP);
1072 
1073         fTDP_Power_right = fMultiply(fFT_Lkg_V0NORM, fMultiply(fLKG_Factor,
1074                 fMultiply(fExponential(fMultiply(fAdd(fMultiply(fKv_m_fused,
1075                 fT_prod), fKv_b_fused), fV_x)), fV_x)));
1076         fTDP_Power_right = fMultiply(fTDP_Power_right, fExponential(fMultiply(
1077                 fKt_Beta_fused, fT_prod)));
1078         fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
1079                 fAdd(fMultiply(fKv_m_fused, fT_prod), fKv_b_fused), fV_FT)));
1080         fTDP_Power_right = fDivide(fTDP_Power_right, fExponential(fMultiply(
1081                 fKt_Beta_fused, fT_FT)));
1082 
1083         fTDP_Power = fAdd(fTDP_Power_left, fTDP_Power_right);
1084 
1085         fTDP_Current = fDivide(fTDP_Power, fV_x);
1086 
1087         fV_NL = fAdd(fV_x, fDivide(fMultiply(fTDP_Current, fRLL_LoadLine),
1088                 ConvertToFraction(10)));
1089 
1090         fV_NL = fRoundUpByStepSize(fV_NL, fStepSize, 0);
1091 
1092         if (GreaterThan(fV_max, fV_NL) &&
1093             (GreaterThan(fV_NL, fEVV_V) ||
1094             Equal(fV_NL, fEVV_V))) {
1095             fV_NL = fMultiply(fV_NL, ConvertToFraction(1000));
1096 
1097             *voltage = (uint16_t)fV_NL.partial.real;
1098             break;
1099         } else
1100             fV_x = fAdd(fV_x, fStepSize);
1101     }
1102 
1103     return result;
1104 }
1105 
1106 /**
1107  * atomctrl_get_voltage_evv_on_sclk: gets voltage via call to ATOM COMMAND table.
1108  * @hwmgr:              input: pointer to hwManager
1109  * @voltage_type:       input: type of EVV voltage VDDC or VDDGFX
1110  * @sclk:               input: in 10Khz unit. DPM state SCLK frequency
1111  *               which is define in PPTable SCLK/VDDC dependence
1112  *           table associated with this virtual_voltage_Id
1113  * @virtual_voltage_Id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
1114  * @voltage:            output: real voltage level in unit of mv
1115  */
1116 int atomctrl_get_voltage_evv_on_sclk(
1117         struct pp_hwmgr *hwmgr,
1118         uint8_t voltage_type,
1119         uint32_t sclk, uint16_t virtual_voltage_Id,
1120         uint16_t *voltage)
1121 {
1122     struct amdgpu_device *adev = hwmgr->adev;
1123     GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1124     int result;
1125 
1126     get_voltage_info_param_space.ucVoltageType   =
1127         voltage_type;
1128     get_voltage_info_param_space.ucVoltageMode   =
1129         ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1130     get_voltage_info_param_space.usVoltageLevel  =
1131         cpu_to_le16(virtual_voltage_Id);
1132     get_voltage_info_param_space.ulSCLKFreq      =
1133         cpu_to_le32(sclk);
1134 
1135     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1136             GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1137             (uint32_t *)&get_voltage_info_param_space);
1138 
1139     *voltage = result ? 0 :
1140             le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
1141                 (&get_voltage_info_param_space))->usVoltageLevel);
1142 
1143     return result;
1144 }
1145 
1146 /**
1147  * atomctrl_get_voltage_evv: gets voltage via call to ATOM COMMAND table.
1148  * @hwmgr:              input: pointer to hwManager
1149  * @virtual_voltage_id: input: voltage id which match per voltage DPM state: 0xff01, 0xff02.. 0xff08
1150  * @voltage:           output: real voltage level in unit of mv
1151  */
1152 int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
1153                  uint16_t virtual_voltage_id,
1154                  uint16_t *voltage)
1155 {
1156     struct amdgpu_device *adev = hwmgr->adev;
1157     GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space;
1158     int result;
1159     int entry_id;
1160 
1161     /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
1162     for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
1163         if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
1164             /* found */
1165             break;
1166         }
1167     }
1168 
1169     if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
1170             pr_debug("Can't find requested voltage id in vddc_dependency_on_sclk table!\n");
1171             return -EINVAL;
1172     }
1173 
1174     get_voltage_info_param_space.ucVoltageType = VOLTAGE_TYPE_VDDC;
1175     get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1176     get_voltage_info_param_space.usVoltageLevel = virtual_voltage_id;
1177     get_voltage_info_param_space.ulSCLKFreq =
1178         cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
1179 
1180     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1181             GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1182             (uint32_t *)&get_voltage_info_param_space);
1183 
1184     if (0 != result)
1185         return result;
1186 
1187     *voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
1188                 (&get_voltage_info_param_space))->usVoltageLevel);
1189 
1190     return result;
1191 }
1192 
1193 /*
1194  * Get the mpll reference clock in 10KHz
1195  */
1196 uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
1197 {
1198     ATOM_COMMON_TABLE_HEADER *fw_info;
1199     uint32_t clock;
1200     u8 frev, crev;
1201     u16 size;
1202 
1203     fw_info = (ATOM_COMMON_TABLE_HEADER *)
1204         smu_atom_get_data_table(hwmgr->adev,
1205                 GetIndexIntoMasterTable(DATA, FirmwareInfo),
1206                 &size, &frev, &crev);
1207 
1208     if (fw_info == NULL)
1209         clock = 2700;
1210     else {
1211         if ((fw_info->ucTableFormatRevision == 2) &&
1212             (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V2_1))) {
1213             ATOM_FIRMWARE_INFO_V2_1 *fwInfo_2_1 =
1214                 (ATOM_FIRMWARE_INFO_V2_1 *)fw_info;
1215             clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock));
1216         } else {
1217             ATOM_FIRMWARE_INFO *fwInfo_0_0 =
1218                 (ATOM_FIRMWARE_INFO *)fw_info;
1219             clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock));
1220         }
1221     }
1222 
1223     return clock;
1224 }
1225 
1226 /*
1227  * Get the asic internal spread spectrum table
1228  */
1229 static ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device)
1230 {
1231     ATOM_ASIC_INTERNAL_SS_INFO *table = NULL;
1232     u8 frev, crev;
1233     u16 size;
1234 
1235     table = (ATOM_ASIC_INTERNAL_SS_INFO *)
1236         smu_atom_get_data_table(device,
1237             GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info),
1238             &size, &frev, &crev);
1239 
1240     return table;
1241 }
1242 
1243 bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr)
1244 {
1245     ATOM_ASIC_INTERNAL_SS_INFO *table =
1246         asic_internal_ss_get_ss_table(hwmgr->adev);
1247 
1248     if (table)
1249         return true;
1250     else
1251         return false;
1252 }
1253 
1254 /*
1255  * Get the asic internal spread spectrum assignment
1256  */
1257 static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
1258         const uint8_t clockSource,
1259         const uint32_t clockSpeed,
1260         pp_atomctrl_internal_ss_info *ssEntry)
1261 {
1262     ATOM_ASIC_INTERNAL_SS_INFO *table;
1263     ATOM_ASIC_SS_ASSIGNMENT *ssInfo;
1264     int entry_found = 0;
1265 
1266     memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info));
1267 
1268     table = asic_internal_ss_get_ss_table(hwmgr->adev);
1269 
1270     if (NULL == table)
1271         return -1;
1272 
1273     ssInfo = &table->asSpreadSpectrum[0];
1274 
1275     while (((uint8_t *)ssInfo - (uint8_t *)table) <
1276         le16_to_cpu(table->sHeader.usStructureSize)) {
1277         if ((clockSource == ssInfo->ucClockIndication) &&
1278             ((uint32_t)clockSpeed <= le32_to_cpu(ssInfo->ulTargetClockRange))) {
1279             entry_found = 1;
1280             break;
1281         }
1282 
1283         ssInfo = (ATOM_ASIC_SS_ASSIGNMENT *)((uint8_t *)ssInfo +
1284                 sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1285     }
1286 
1287     if (entry_found) {
1288         ssEntry->speed_spectrum_percentage =
1289             le16_to_cpu(ssInfo->usSpreadSpectrumPercentage);
1290         ssEntry->speed_spectrum_rate = le16_to_cpu(ssInfo->usSpreadRateInKhz);
1291 
1292         if (((GET_DATA_TABLE_MAJOR_REVISION(table) == 2) &&
1293             (GET_DATA_TABLE_MINOR_REVISION(table) >= 2)) ||
1294             (GET_DATA_TABLE_MAJOR_REVISION(table) == 3)) {
1295             ssEntry->speed_spectrum_rate /= 100;
1296         }
1297 
1298         switch (ssInfo->ucSpreadSpectrumMode) {
1299         case 0:
1300             ssEntry->speed_spectrum_mode =
1301                 pp_atomctrl_spread_spectrum_mode_down;
1302             break;
1303         case 1:
1304             ssEntry->speed_spectrum_mode =
1305                 pp_atomctrl_spread_spectrum_mode_center;
1306             break;
1307         default:
1308             ssEntry->speed_spectrum_mode =
1309                 pp_atomctrl_spread_spectrum_mode_down;
1310             break;
1311         }
1312     }
1313 
1314     return entry_found ? 0 : 1;
1315 }
1316 
1317 /*
1318  * Get the memory clock spread spectrum info
1319  */
1320 int atomctrl_get_memory_clock_spread_spectrum(
1321         struct pp_hwmgr *hwmgr,
1322         const uint32_t memory_clock,
1323         pp_atomctrl_internal_ss_info *ssInfo)
1324 {
1325     return asic_internal_ss_get_ss_asignment(hwmgr,
1326             ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo);
1327 }
1328 
1329 /*
1330  * Get the engine clock spread spectrum info
1331  */
1332 int atomctrl_get_engine_clock_spread_spectrum(
1333         struct pp_hwmgr *hwmgr,
1334         const uint32_t engine_clock,
1335         pp_atomctrl_internal_ss_info *ssInfo)
1336 {
1337     return asic_internal_ss_get_ss_asignment(hwmgr,
1338             ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo);
1339 }
1340 
1341 int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
1342         uint16_t end_index, uint32_t *efuse)
1343 {
1344     struct amdgpu_device *adev = hwmgr->adev;
1345     uint32_t mask;
1346     int result;
1347     READ_EFUSE_VALUE_PARAMETER efuse_param;
1348 
1349     if ((end_index - start_index)  == 31)
1350         mask = 0xFFFFFFFF;
1351     else
1352         mask = (1 << ((end_index - start_index) + 1)) - 1;
1353 
1354     efuse_param.sEfuse.usEfuseIndex = cpu_to_le16((start_index / 32) * 4);
1355     efuse_param.sEfuse.ucBitShift = (uint8_t)
1356             (start_index - ((start_index / 32) * 32));
1357     efuse_param.sEfuse.ucBitLength  = (uint8_t)
1358             ((end_index - start_index) + 1);
1359 
1360     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1361             GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
1362             (uint32_t *)&efuse_param);
1363     *efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask;
1364 
1365     return result;
1366 }
1367 
1368 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
1369                   uint8_t level)
1370 {
1371     struct amdgpu_device *adev = hwmgr->adev;
1372     DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters;
1373     int result;
1374 
1375     memory_clock_parameters.asDPMMCReg.ulClock.ulClockFreq =
1376         memory_clock & SET_CLOCK_FREQ_MASK;
1377     memory_clock_parameters.asDPMMCReg.ulClock.ulComputeClockFlag =
1378         ADJUST_MC_SETTING_PARAM;
1379     memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level;
1380 
1381     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1382          GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings),
1383         (uint32_t *)&memory_clock_parameters);
1384 
1385     return result;
1386 }
1387 
1388 int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
1389                 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
1390 {
1391     struct amdgpu_device *adev = hwmgr->adev;
1392     int result;
1393     GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space;
1394 
1395     get_voltage_info_param_space.ucVoltageType = voltage_type;
1396     get_voltage_info_param_space.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1397     get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id);
1398     get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk);
1399 
1400     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1401             GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
1402             (uint32_t *)&get_voltage_info_param_space);
1403 
1404     *voltage = result ? 0 :
1405         le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel);
1406 
1407     return result;
1408 }
1409 
1410 int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table)
1411 {
1412 
1413     int i;
1414     u8 frev, crev;
1415     u16 size;
1416 
1417     ATOM_SMU_INFO_V2_1 *psmu_info =
1418         (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
1419             GetIndexIntoMasterTable(DATA, SMU_Info),
1420             &size, &frev, &crev);
1421 
1422 
1423     for (i = 0; i < psmu_info->ucSclkEntryNum; i++) {
1424         table->entry[i].ucVco_setting = psmu_info->asSclkFcwRangeEntry[i].ucVco_setting;
1425         table->entry[i].ucPostdiv = psmu_info->asSclkFcwRangeEntry[i].ucPostdiv;
1426         table->entry[i].usFcw_pcc =
1427             le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_pcc);
1428         table->entry[i].usFcw_trans_upper =
1429             le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucFcw_trans_upper);
1430         table->entry[i].usRcw_trans_lower =
1431             le16_to_cpu(psmu_info->asSclkFcwRangeEntry[i].ucRcw_trans_lower);
1432     }
1433 
1434     return 0;
1435 }
1436 
1437 int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail)
1438 {
1439     ATOM_SMU_INFO_V2_1 *psmu_info =
1440         (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
1441             GetIndexIntoMasterTable(DATA, SMU_Info),
1442             NULL, NULL, NULL);
1443     if (!psmu_info)
1444         return -1;
1445 
1446     *shared_rail = psmu_info->ucSharePowerSource;
1447 
1448     return 0;
1449 }
1450 
1451 int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
1452                   struct pp_atom_ctrl__avfs_parameters *param)
1453 {
1454     ATOM_ASIC_PROFILING_INFO_V3_6 *profile = NULL;
1455 
1456     if (param == NULL)
1457         return -EINVAL;
1458 
1459     profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *)
1460             smu_atom_get_data_table(hwmgr->adev,
1461                     GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
1462                     NULL, NULL, NULL);
1463     if (!profile)
1464         return -1;
1465 
1466     param->ulAVFS_meanNsigma_Acontant0 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant0);
1467     param->ulAVFS_meanNsigma_Acontant1 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant1);
1468     param->ulAVFS_meanNsigma_Acontant2 = le32_to_cpu(profile->ulAVFS_meanNsigma_Acontant2);
1469     param->usAVFS_meanNsigma_DC_tol_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_DC_tol_sigma);
1470     param->usAVFS_meanNsigma_Platform_mean = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_mean);
1471     param->usAVFS_meanNsigma_Platform_sigma = le16_to_cpu(profile->usAVFS_meanNsigma_Platform_sigma);
1472     param->ulGB_VDROOP_TABLE_CKSOFF_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a0);
1473     param->ulGB_VDROOP_TABLE_CKSOFF_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a1);
1474     param->ulGB_VDROOP_TABLE_CKSOFF_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSOFF_a2);
1475     param->ulGB_VDROOP_TABLE_CKSON_a0 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a0);
1476     param->ulGB_VDROOP_TABLE_CKSON_a1 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a1);
1477     param->ulGB_VDROOP_TABLE_CKSON_a2 = le32_to_cpu(profile->ulGB_VDROOP_TABLE_CKSON_a2);
1478     param->ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1479     param->usAVFSGB_FUSE_TABLE_CKSOFF_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1480     param->ulAVFSGB_FUSE_TABLE_CKSOFF_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1481     param->ulAVFSGB_FUSE_TABLE_CKSON_m1 = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_m1);
1482     param->usAVFSGB_FUSE_TABLE_CKSON_m2 = le16_to_cpu(profile->usAVFSGB_FUSE_TABLE_CKSON_m2);
1483     param->ulAVFSGB_FUSE_TABLE_CKSON_b = le32_to_cpu(profile->ulAVFSGB_FUSE_TABLE_CKSON_b);
1484     param->usMaxVoltage_0_25mv = le16_to_cpu(profile->usMaxVoltage_0_25mv);
1485     param->ucEnableGB_VDROOP_TABLE_CKSOFF = profile->ucEnableGB_VDROOP_TABLE_CKSOFF;
1486     param->ucEnableGB_VDROOP_TABLE_CKSON = profile->ucEnableGB_VDROOP_TABLE_CKSON;
1487     param->ucEnableGB_FUSE_TABLE_CKSOFF = profile->ucEnableGB_FUSE_TABLE_CKSOFF;
1488     param->ucEnableGB_FUSE_TABLE_CKSON = profile->ucEnableGB_FUSE_TABLE_CKSON;
1489     param->usPSM_Age_ComFactor = le16_to_cpu(profile->usPSM_Age_ComFactor);
1490     param->ucEnableApplyAVFS_CKS_OFF_Voltage = profile->ucEnableApplyAVFS_CKS_OFF_Voltage;
1491 
1492     return 0;
1493 }
1494 
1495 int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
1496                 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
1497                 uint16_t *load_line)
1498 {
1499     ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info =
1500         (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
1501 
1502     const ATOM_VOLTAGE_OBJECT_V3 *voltage_object;
1503 
1504     PP_ASSERT_WITH_CODE((NULL != voltage_info),
1505             "Could not find Voltage Table in BIOS.", return -EINVAL);
1506 
1507     voltage_object = atomctrl_lookup_voltage_type_v3
1508         (voltage_info, voltage_type,  VOLTAGE_OBJ_SVID2);
1509 
1510     *svd_gpio_id = voltage_object->asSVID2Obj.ucSVDGpioId;
1511     *svc_gpio_id = voltage_object->asSVID2Obj.ucSVCGpioId;
1512     *load_line = voltage_object->asSVID2Obj.usLoadLine_PSI;
1513 
1514     return 0;
1515 }
1516 
1517 int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
1518 {
1519     struct amdgpu_device *adev = hwmgr->adev;
1520     SET_VOLTAGE_PS_ALLOCATION allocation;
1521     SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters =
1522             (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage;
1523     int result;
1524 
1525     voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1526 
1527     result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
1528             GetIndexIntoMasterTable(COMMAND, SetVoltage),
1529             (uint32_t *)voltage_parameters);
1530 
1531     *virtual_voltage_id = voltage_parameters->usVoltageLevel;
1532 
1533     return result;
1534 }
1535 
1536 int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
1537                     uint16_t *vddc, uint16_t *vddci,
1538                     uint16_t virtual_voltage_id,
1539                     uint16_t efuse_voltage_id)
1540 {
1541     int i, j;
1542     int ix;
1543     u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1544     ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1545 
1546     *vddc = 0;
1547     *vddci = 0;
1548 
1549     ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1550 
1551     profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1552             smu_atom_get_data_table(hwmgr->adev,
1553                     ix,
1554                     NULL, NULL, NULL);
1555     if (!profile)
1556         return -EINVAL;
1557 
1558     if ((profile->asHeader.ucTableFormatRevision >= 2) &&
1559         (profile->asHeader.ucTableContentRevision >= 1) &&
1560         (profile->asHeader.usStructureSize >= sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))) {
1561         leakage_bin = (u16 *)((char *)profile + profile->usLeakageBinArrayOffset);
1562         vddc_id_buf = (u16 *)((char *)profile + profile->usElbVDDC_IdArrayOffset);
1563         vddc_buf = (u16 *)((char *)profile + profile->usElbVDDC_LevelArrayOffset);
1564         if (profile->ucElbVDDC_Num > 0) {
1565             for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1566                 if (vddc_id_buf[i] == virtual_voltage_id) {
1567                     for (j = 0; j < profile->ucLeakageBinNum; j++) {
1568                         if (efuse_voltage_id <= leakage_bin[j]) {
1569                             *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1570                             break;
1571                         }
1572                     }
1573                     break;
1574                 }
1575             }
1576         }
1577 
1578         vddci_id_buf = (u16 *)((char *)profile + profile->usElbVDDCI_IdArrayOffset);
1579         vddci_buf   = (u16 *)((char *)profile + profile->usElbVDDCI_LevelArrayOffset);
1580         if (profile->ucElbVDDCI_Num > 0) {
1581             for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1582                 if (vddci_id_buf[i] == virtual_voltage_id) {
1583                     for (j = 0; j < profile->ucLeakageBinNum; j++) {
1584                         if (efuse_voltage_id <= leakage_bin[j]) {
1585                             *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1586                             break;
1587                         }
1588                     }
1589                     break;
1590                 }
1591             }
1592         }
1593     }
1594 
1595     return 0;
1596 }
1597 
1598 void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
1599                             uint32_t *min_vddc)
1600 {
1601     void *profile;
1602 
1603     profile = smu_atom_get_data_table(hwmgr->adev,
1604                     GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo),
1605                     NULL, NULL, NULL);
1606 
1607     if (profile) {
1608         switch (hwmgr->chip_id) {
1609         case CHIP_TONGA:
1610         case CHIP_FIJI:
1611             *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMaxVddc) / 4;
1612             *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMinVddc) / 4;
1613             return;
1614         case CHIP_POLARIS11:
1615         case CHIP_POLARIS10:
1616         case CHIP_POLARIS12:
1617             *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMaxVddc) / 100;
1618             *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMinVddc) / 100;
1619             return;
1620         default:
1621             break;
1622         }
1623     }
1624     *max_vddc = 0;
1625     *min_vddc = 0;
1626 }
1627 
1628 int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr,
1629                            AtomCtrl_HiLoLeakageOffsetTable *table)
1630 {
1631     ATOM_GFX_INFO_V2_3 *gfxinfo = smu_atom_get_data_table(hwmgr->adev,
1632                     GetIndexIntoMasterTable(DATA, GFX_Info),
1633                     NULL, NULL, NULL);
1634     if (!gfxinfo)
1635         return -ENOENT;
1636 
1637     table->usHiLoLeakageThreshold = gfxinfo->usHiLoLeakageThreshold;
1638     table->usEdcDidtLoDpm7TableOffset = gfxinfo->usEdcDidtLoDpm7TableOffset;
1639     table->usEdcDidtHiDpm7TableOffset = gfxinfo->usEdcDidtHiDpm7TableOffset;
1640 
1641     return 0;
1642 }
1643 
1644 static AtomCtrl_EDCLeakgeTable *get_edc_leakage_table(struct pp_hwmgr *hwmgr,
1645                               uint16_t offset)
1646 {
1647     void *table_address;
1648     char *temp;
1649 
1650     table_address = smu_atom_get_data_table(hwmgr->adev,
1651             GetIndexIntoMasterTable(DATA, GFX_Info),
1652             NULL, NULL, NULL);
1653     if (!table_address)
1654         return NULL;
1655 
1656     temp = (char *)table_address;
1657     table_address += offset;
1658 
1659     return (AtomCtrl_EDCLeakgeTable *)temp;
1660 }
1661 
1662 int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr,
1663                    AtomCtrl_EDCLeakgeTable *table,
1664                    uint16_t offset)
1665 {
1666     uint32_t length, i;
1667     AtomCtrl_EDCLeakgeTable *leakage_table =
1668         get_edc_leakage_table(hwmgr, offset);
1669 
1670     if (!leakage_table)
1671         return -ENOENT;
1672 
1673     length = sizeof(leakage_table->DIDT_REG) /
1674          sizeof(leakage_table->DIDT_REG[0]);
1675     for (i = 0; i < length; i++)
1676         table->DIDT_REG[i] = leakage_table->DIDT_REG[i];
1677 
1678     return 0;
1679 }
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