powerplay/hwmgr/hwmgr.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "pp_debug.h"
0025 #include <linux/delay.h>
0026 #include <linux/kernel.h>
0027 #include <linux/slab.h>
0028 #include <linux/types.h>
0029 #include <linux/pci.h>
0030 #include <drm/amdgpu_drm.h>
0031 #include "power_state.h"
0032 #include "hwmgr.h"
0033 #include "ppsmc.h"
0034 #include "amd_acpi.h"
0035 #include "pp_psm.h"
0036 #include "vega10_hwmgr.h"
0037
0038 extern const struct pp_smumgr_func ci_smu_funcs;
0039 extern const struct pp_smumgr_func smu8_smu_funcs;
0040 extern const struct pp_smumgr_func iceland_smu_funcs;
0041 extern const struct pp_smumgr_func tonga_smu_funcs;
0042 extern const struct pp_smumgr_func fiji_smu_funcs;
0043 extern const struct pp_smumgr_func polaris10_smu_funcs;
0044 extern const struct pp_smumgr_func vegam_smu_funcs;
0045 extern const struct pp_smumgr_func vega10_smu_funcs;
0046 extern const struct pp_smumgr_func vega12_smu_funcs;
0047 extern const struct pp_smumgr_func smu10_smu_funcs;
0048 extern const struct pp_smumgr_func vega20_smu_funcs;
0049
0050 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
0051
0052 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
0053 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
0054 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
0055 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
0056 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
0057 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
0058 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
0059
0060
0061 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
0062 {
0063     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
0064     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
0065     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
0066     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
0067     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
0068     hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
0069
0070     hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
0071     hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
0072     hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
0073     hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
0074     hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
0075     hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
0076 }
0077
0078 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
0079 {
0080     struct amdgpu_device *adev;
0081
0082     if (!hwmgr)
0083         return -EINVAL;
0084
0085     hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
0086     hwmgr->pp_table_version = PP_TABLE_V1;
0087     hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
0088     hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
0089     hwmgr_init_default_caps(hwmgr);
0090     hwmgr_set_user_specify_caps(hwmgr);
0091     hwmgr->fan_ctrl_is_in_default_mode = true;
0092     hwmgr_init_workload_prority(hwmgr);
0093     hwmgr->gfxoff_state_changed_by_workload = false;
0094
0095     adev = hwmgr->adev;
0096
0097     switch (hwmgr->chip_family) {
0098     case AMDGPU_FAMILY_CI:
0099         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0100         hwmgr->smumgr_funcs = &ci_smu_funcs;
0101         ci_set_asic_special_caps(hwmgr);
0102         hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
0103                      PP_ENABLE_GFX_CG_THRU_SMU |
0104                      PP_GFXOFF_MASK);
0105         hwmgr->pp_table_version = PP_TABLE_V0;
0106         hwmgr->od_enabled = false;
0107         smu7_init_function_pointers(hwmgr);
0108         break;
0109     case AMDGPU_FAMILY_CZ:
0110         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0111         hwmgr->od_enabled = false;
0112         hwmgr->smumgr_funcs = &smu8_smu_funcs;
0113         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
0114         smu8_init_function_pointers(hwmgr);
0115         break;
0116     case AMDGPU_FAMILY_VI:
0117         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0118         hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
0119         switch (hwmgr->chip_id) {
0120         case CHIP_TOPAZ:
0121             hwmgr->smumgr_funcs = &iceland_smu_funcs;
0122             topaz_set_asic_special_caps(hwmgr);
0123             hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
0124                         PP_ENABLE_GFX_CG_THRU_SMU);
0125             hwmgr->pp_table_version = PP_TABLE_V0;
0126             hwmgr->od_enabled = false;
0127             break;
0128         case CHIP_TONGA:
0129             hwmgr->smumgr_funcs = &tonga_smu_funcs;
0130             tonga_set_asic_special_caps(hwmgr);
0131             hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
0132             break;
0133         case CHIP_FIJI:
0134             hwmgr->smumgr_funcs = &fiji_smu_funcs;
0135             fiji_set_asic_special_caps(hwmgr);
0136             hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
0137                         PP_ENABLE_GFX_CG_THRU_SMU);
0138             break;
0139         case CHIP_POLARIS11:
0140         case CHIP_POLARIS10:
0141         case CHIP_POLARIS12:
0142             hwmgr->smumgr_funcs = &polaris10_smu_funcs;
0143             polaris_set_asic_special_caps(hwmgr);
0144             hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
0145             break;
0146         case CHIP_VEGAM:
0147             hwmgr->smumgr_funcs = &vegam_smu_funcs;
0148             polaris_set_asic_special_caps(hwmgr);
0149             hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
0150             break;
0151         default:
0152             return -EINVAL;
0153         }
0154         smu7_init_function_pointers(hwmgr);
0155         break;
0156     case AMDGPU_FAMILY_AI:
0157         switch (hwmgr->chip_id) {
0158         case CHIP_VEGA10:
0159             adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0160             hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
0161             hwmgr->smumgr_funcs = &vega10_smu_funcs;
0162             vega10_hwmgr_init(hwmgr);
0163             break;
0164         case CHIP_VEGA12:
0165             hwmgr->smumgr_funcs = &vega12_smu_funcs;
0166             vega12_hwmgr_init(hwmgr);
0167             break;
0168         case CHIP_VEGA20:
0169             adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0170             hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
0171             hwmgr->smumgr_funcs = &vega20_smu_funcs;
0172             vega20_hwmgr_init(hwmgr);
0173             break;
0174         default:
0175             return -EINVAL;
0176         }
0177         break;
0178     case AMDGPU_FAMILY_RV:
0179         switch (hwmgr->chip_id) {
0180         case CHIP_RAVEN:
0181             hwmgr->od_enabled = false;
0182             hwmgr->smumgr_funcs = &smu10_smu_funcs;
0183             smu10_init_function_pointers(hwmgr);
0184             break;
0185         default:
0186             return -EINVAL;
0187         }
0188         break;
0189     default:
0190         return -EINVAL;
0191     }
0192
0193     return 0;
0194 }
0195
0196 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
0197 {
0198     if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
0199         return -EINVAL;
0200
0201     phm_register_irq_handlers(hwmgr);
0202     pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name);
0203
0204     return hwmgr->smumgr_funcs->smu_init(hwmgr);
0205 }
0206
0207
0208 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
0209 {
0210     if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
0211         hwmgr->smumgr_funcs->smu_fini(hwmgr);
0212
0213     return 0;
0214 }
0215
0216 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
0217 {
0218     int ret = 0;
0219
0220     hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device *)hwmgr->adev);
0221     hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf))
0222             ? true : false;
0223     if (!hwmgr->pm_en)
0224         return 0;
0225
0226     if (!hwmgr->pptable_func ||
0227         !hwmgr->pptable_func->pptable_init ||
0228         !hwmgr->hwmgr_func->backend_init) {
0229         hwmgr->pm_en = false;
0230         pr_info("dpm not supported \n");
0231         return 0;
0232     }
0233
0234     ret = hwmgr->pptable_func->pptable_init(hwmgr);
0235     if (ret)
0236         goto err;
0237
0238     ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
0239                 hwmgr->thermal_controller.fanInfo.bNoFan;
0240
0241     ret = hwmgr->hwmgr_func->backend_init(hwmgr);
0242     if (ret)
0243         goto err1;
0244  /* make sure dc limits are valid */
0245     if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
0246             (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
0247             hwmgr->dyn_state.max_clock_voltage_on_dc =
0248                     hwmgr->dyn_state.max_clock_voltage_on_ac;
0249
0250     ret = psm_init_power_state_table(hwmgr);
0251     if (ret)
0252         goto err2;
0253
0254     ret = phm_setup_asic(hwmgr);
0255     if (ret)
0256         goto err2;
0257
0258     ret = phm_enable_dynamic_state_management(hwmgr);
0259     if (ret)
0260         goto err2;
0261     ret = phm_start_thermal_controller(hwmgr);
0262     ret |= psm_set_performance_states(hwmgr);
0263     if (ret)
0264         goto err2;
0265
0266     ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
0267
0268     return 0;
0269 err2:
0270     if (hwmgr->hwmgr_func->backend_fini)
0271         hwmgr->hwmgr_func->backend_fini(hwmgr);
0272 err1:
0273     if (hwmgr->pptable_func->pptable_fini)
0274         hwmgr->pptable_func->pptable_fini(hwmgr);
0275 err:
0276     return ret;
0277 }
0278
0279 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
0280 {
0281     if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
0282         return 0;
0283
0284     phm_stop_thermal_controller(hwmgr);
0285     psm_set_boot_states(hwmgr);
0286     psm_adjust_power_state_dynamic(hwmgr, true, NULL);
0287     phm_disable_dynamic_state_management(hwmgr);
0288     phm_disable_clock_power_gatings(hwmgr);
0289
0290     if (hwmgr->hwmgr_func->backend_fini)
0291         hwmgr->hwmgr_func->backend_fini(hwmgr);
0292     if (hwmgr->pptable_func->pptable_fini)
0293         hwmgr->pptable_func->pptable_fini(hwmgr);
0294     return psm_fini_power_state_table(hwmgr);
0295 }
0296
0297 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
0298 {
0299     int ret = 0;
0300
0301     if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
0302         return 0;
0303
0304     phm_disable_smc_firmware_ctf(hwmgr);
0305     ret = psm_set_boot_states(hwmgr);
0306     if (ret)
0307         return ret;
0308     ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
0309     if (ret)
0310         return ret;
0311     ret = phm_power_down_asic(hwmgr);
0312
0313     return ret;
0314 }
0315
0316 int hwmgr_resume(struct pp_hwmgr *hwmgr)
0317 {
0318     int ret = 0;
0319
0320     if (!hwmgr)
0321         return -EINVAL;
0322
0323     if (!hwmgr->not_vf || !hwmgr->pm_en)
0324         return 0;
0325
0326     ret = phm_setup_asic(hwmgr);
0327     if (ret)
0328         return ret;
0329
0330     ret = phm_enable_dynamic_state_management(hwmgr);
0331     if (ret)
0332         return ret;
0333     ret = phm_start_thermal_controller(hwmgr);
0334     ret |= psm_set_performance_states(hwmgr);
0335     if (ret)
0336         return ret;
0337
0338     ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
0339
0340     return ret;
0341 }
0342
0343 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
0344 {
0345     switch (state) {
0346     case POWER_STATE_TYPE_BATTERY:
0347         return PP_StateUILabel_Battery;
0348     case POWER_STATE_TYPE_BALANCED:
0349         return PP_StateUILabel_Balanced;
0350     case POWER_STATE_TYPE_PERFORMANCE:
0351         return PP_StateUILabel_Performance;
0352     default:
0353         return PP_StateUILabel_None;
0354     }
0355 }
0356
0357 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
0358         enum amd_pm_state_type *user_state)
0359 {
0360     int ret = 0;
0361
0362     if (hwmgr == NULL)
0363         return -EINVAL;
0364
0365     switch (task_id) {
0366     case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
0367         if (!hwmgr->not_vf)
0368             return ret;
0369         ret = phm_pre_display_configuration_changed(hwmgr);
0370         if (ret)
0371             return ret;
0372         ret = phm_set_cpu_power_state(hwmgr);
0373         if (ret)
0374             return ret;
0375         ret = psm_set_performance_states(hwmgr);
0376         if (ret)
0377             return ret;
0378         ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
0379         break;
0380     case AMD_PP_TASK_ENABLE_USER_STATE:
0381     {
0382         enum PP_StateUILabel requested_ui_label;
0383         struct pp_power_state *requested_ps = NULL;
0384
0385         if (!hwmgr->not_vf)
0386             return ret;
0387         if (user_state == NULL) {
0388             ret = -EINVAL;
0389             break;
0390         }
0391
0392         requested_ui_label = power_state_convert(*user_state);
0393         ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
0394         if (ret)
0395             return ret;
0396         ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);
0397         break;
0398     }
0399     case AMD_PP_TASK_COMPLETE_INIT:
0400     case AMD_PP_TASK_READJUST_POWER_STATE:
0401         ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
0402         break;
0403     default:
0404         break;
0405     }
0406     return ret;
0407 }
0408
0409 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
0410 {
0411     phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
0412
0413     phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
0414     phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
0415
0416 #if defined(CONFIG_ACPI)
0417     if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
0418         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
0419 #endif
0420
0421     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0422         PHM_PlatformCaps_DynamicPatchPowerState);
0423
0424     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0425         PHM_PlatformCaps_EnableSMU7ThermalManagement);
0426
0427     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0428             PHM_PlatformCaps_DynamicPowerManagement);
0429
0430     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0431                     PHM_PlatformCaps_SMC);
0432
0433     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0434                     PHM_PlatformCaps_DynamicUVDState);
0435
0436     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0437                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
0438     return;
0439 }
0440
0441 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
0442 {
0443     if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
0444         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0445             PHM_PlatformCaps_SclkDeepSleep);
0446     else
0447         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0448             PHM_PlatformCaps_SclkDeepSleep);
0449
0450     if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
0451         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0452                 PHM_PlatformCaps_PowerContainment);
0453         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0454             PHM_PlatformCaps_CAC);
0455     } else {
0456         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0457                 PHM_PlatformCaps_PowerContainment);
0458         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0459             PHM_PlatformCaps_CAC);
0460     }
0461
0462     if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
0463         hwmgr->od_enabled = true;
0464
0465     return 0;
0466 }
0467
0468 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
0469 {
0470     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0471                         PHM_PlatformCaps_EVV);
0472     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0473                         PHM_PlatformCaps_SQRamping);
0474     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0475                         PHM_PlatformCaps_RegulatorHot);
0476
0477     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0478             PHM_PlatformCaps_MemorySpreadSpectrumSupport);
0479     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0480             PHM_PlatformCaps_EngineSpreadSpectrumSupport);
0481
0482     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0483                     PHM_PlatformCaps_AutomaticDCTransition);
0484
0485     if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
0486         (hwmgr->chip_id == CHIP_POLARIS12))
0487         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0488                 PHM_PlatformCaps_SPLLShutdownSupport);
0489
0490     if (hwmgr->chip_id != CHIP_POLARIS11) {
0491         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0492                             PHM_PlatformCaps_DBRamping);
0493         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0494                             PHM_PlatformCaps_TDRamping);
0495         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0496                             PHM_PlatformCaps_TCPRamping);
0497     }
0498     return 0;
0499 }
0500
0501 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
0502 {
0503     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0504                         PHM_PlatformCaps_EVV);
0505     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0506             PHM_PlatformCaps_SQRamping);
0507     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0508             PHM_PlatformCaps_DBRamping);
0509     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0510             PHM_PlatformCaps_TDRamping);
0511     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0512             PHM_PlatformCaps_TCPRamping);
0513     return 0;
0514 }
0515
0516 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
0517 {
0518     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0519                         PHM_PlatformCaps_EVV);
0520     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0521             PHM_PlatformCaps_SQRamping);
0522     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0523             PHM_PlatformCaps_DBRamping);
0524     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0525             PHM_PlatformCaps_TDRamping);
0526     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0527             PHM_PlatformCaps_TCPRamping);
0528
0529     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0530               PHM_PlatformCaps_UVDPowerGating);
0531     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0532               PHM_PlatformCaps_VCEPowerGating);
0533     return 0;
0534 }
0535
0536 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
0537 {
0538     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0539                         PHM_PlatformCaps_EVV);
0540     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0541             PHM_PlatformCaps_SQRamping);
0542     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0543             PHM_PlatformCaps_DBRamping);
0544     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0545             PHM_PlatformCaps_TDRamping);
0546     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0547             PHM_PlatformCaps_TCPRamping);
0548     return 0;
0549 }
0550
0551 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
0552 {
0553     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0554             PHM_PlatformCaps_SQRamping);
0555     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0556             PHM_PlatformCaps_DBRamping);
0557     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0558             PHM_PlatformCaps_TDRamping);
0559     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0560             PHM_PlatformCaps_TCPRamping);
0561     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0562             PHM_PlatformCaps_MemorySpreadSpectrumSupport);
0563     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0564             PHM_PlatformCaps_EngineSpreadSpectrumSupport);
0565     return 0;
0566 }