pm/legacy-dpm/sislands_smc.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef PP_SISLANDS_SMC_H
0024 #define PP_SISLANDS_SMC_H
0025
0026 #include "ppsmc.h"
0027
0028 #pragma pack(push, 1)
0029
0030 #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16
0031
0032 struct PP_SIslands_Dpm2PerfLevel
0033 {
0034     uint8_t MaxPS;
0035     uint8_t TgtAct;
0036     uint8_t MaxPS_StepInc;
0037     uint8_t MaxPS_StepDec;
0038     uint8_t PSSamplingTime;
0039     uint8_t NearTDPDec;
0040     uint8_t AboveSafeInc;
0041     uint8_t BelowSafeInc;
0042     uint8_t PSDeltaLimit;
0043     uint8_t PSDeltaWin;
0044     uint16_t PwrEfficiencyRatio;
0045     uint8_t Reserved[4];
0046 };
0047
0048 typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel;
0049
0050 struct PP_SIslands_DPM2Status
0051 {
0052     uint32_t    dpm2Flags;
0053     uint8_t     CurrPSkip;
0054     uint8_t     CurrPSkipPowerShift;
0055     uint8_t     CurrPSkipTDP;
0056     uint8_t     CurrPSkipOCP;
0057     uint8_t     MaxSPLLIndex;
0058     uint8_t     MinSPLLIndex;
0059     uint8_t     CurrSPLLIndex;
0060     uint8_t     InfSweepMode;
0061     uint8_t     InfSweepDir;
0062     uint8_t     TDPexceeded;
0063     uint8_t     reserved;
0064     uint8_t     SwitchDownThreshold;
0065     uint32_t    SwitchDownCounter;
0066     uint32_t    SysScalingFactor;
0067 };
0068
0069 typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status;
0070
0071 struct PP_SIslands_DPM2Parameters
0072 {
0073     uint32_t    TDPLimit;
0074     uint32_t    NearTDPLimit;
0075     uint32_t    SafePowerLimit;
0076     uint32_t    PowerBoostLimit;
0077     uint32_t    MinLimitDelta;
0078 };
0079 typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters;
0080
0081 struct PP_SIslands_PAPMStatus
0082 {
0083     uint32_t    EstimatedDGPU_T;
0084     uint32_t    EstimatedDGPU_P;
0085     uint32_t    EstimatedAPU_T;
0086     uint32_t    EstimatedAPU_P;
0087     uint8_t     dGPU_T_Limit_Exceeded;
0088     uint8_t     reserved[3];
0089 };
0090 typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus;
0091
0092 struct PP_SIslands_PAPMParameters
0093 {
0094     uint32_t    NearTDPLimitTherm;
0095     uint32_t    NearTDPLimitPAPM;
0096     uint32_t    PlatformPowerLimit;
0097     uint32_t    dGPU_T_Limit;
0098     uint32_t    dGPU_T_Warning;
0099     uint32_t    dGPU_T_Hysteresis;
0100 };
0101 typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters;
0102
0103 struct SISLANDS_SMC_SCLK_VALUE
0104 {
0105     uint32_t    vCG_SPLL_FUNC_CNTL;
0106     uint32_t    vCG_SPLL_FUNC_CNTL_2;
0107     uint32_t    vCG_SPLL_FUNC_CNTL_3;
0108     uint32_t    vCG_SPLL_FUNC_CNTL_4;
0109     uint32_t    vCG_SPLL_SPREAD_SPECTRUM;
0110     uint32_t    vCG_SPLL_SPREAD_SPECTRUM_2;
0111     uint32_t    sclk_value;
0112 };
0113
0114 typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE;
0115
0116 struct SISLANDS_SMC_MCLK_VALUE
0117 {
0118     uint32_t    vMPLL_FUNC_CNTL;
0119     uint32_t    vMPLL_FUNC_CNTL_1;
0120     uint32_t    vMPLL_FUNC_CNTL_2;
0121     uint32_t    vMPLL_AD_FUNC_CNTL;
0122     uint32_t    vMPLL_DQ_FUNC_CNTL;
0123     uint32_t    vMCLK_PWRMGT_CNTL;
0124     uint32_t    vDLL_CNTL;
0125     uint32_t    vMPLL_SS;
0126     uint32_t    vMPLL_SS2;
0127     uint32_t    mclk_value;
0128 };
0129
0130 typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE;
0131
0132 struct SISLANDS_SMC_VOLTAGE_VALUE
0133 {
0134     uint16_t    value;
0135     uint8_t     index;
0136     uint8_t     phase_settings;
0137 };
0138
0139 typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE;
0140
0141 struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL
0142 {
0143     uint8_t                     ACIndex;
0144     uint8_t                     displayWatermark;
0145     uint8_t                     gen2PCIE;
0146     uint8_t                     UVDWatermark;
0147     uint8_t                     VCEWatermark;
0148     uint8_t                     strobeMode;
0149     uint8_t                     mcFlags;
0150     uint8_t                     padding;
0151     uint32_t                    aT;
0152     uint32_t                    bSP;
0153     SISLANDS_SMC_SCLK_VALUE     sclk;
0154     SISLANDS_SMC_MCLK_VALUE     mclk;
0155     SISLANDS_SMC_VOLTAGE_VALUE  vddc;
0156     SISLANDS_SMC_VOLTAGE_VALUE  mvdd;
0157     SISLANDS_SMC_VOLTAGE_VALUE  vddci;
0158     SISLANDS_SMC_VOLTAGE_VALUE  std_vddc;
0159     uint8_t                     hysteresisUp;
0160     uint8_t                     hysteresisDown;
0161     uint8_t                     stateFlags;
0162     uint8_t                     arbRefreshState;
0163     uint32_t                    SQPowerThrottle;
0164     uint32_t                    SQPowerThrottle_2;
0165     uint32_t                    MaxPoweredUpCU;
0166     SISLANDS_SMC_VOLTAGE_VALUE  high_temp_vddc;
0167     SISLANDS_SMC_VOLTAGE_VALUE  low_temp_vddc;
0168     uint32_t                    reserved[2];
0169     PP_SIslands_Dpm2PerfLevel   dpm2;
0170 };
0171
0172 #define SISLANDS_SMC_STROBE_RATIO    0x0F
0173 #define SISLANDS_SMC_STROBE_ENABLE   0x10
0174
0175 #define SISLANDS_SMC_MC_EDC_RD_FLAG  0x01
0176 #define SISLANDS_SMC_MC_EDC_WR_FLAG  0x02
0177 #define SISLANDS_SMC_MC_RTT_ENABLE   0x04
0178 #define SISLANDS_SMC_MC_STUTTER_EN   0x08
0179 #define SISLANDS_SMC_MC_PG_EN        0x10
0180
0181 typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL;
0182
0183 struct SISLANDS_SMC_SWSTATE
0184 {
0185     uint8_t                             flags;
0186     uint8_t                             levelCount;
0187     uint8_t                             padding2;
0188     uint8_t                             padding3;
0189     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
0190 };
0191
0192 typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
0193
0194 struct SISLANDS_SMC_SWSTATE_SINGLE {
0195     uint8_t                             flags;
0196     uint8_t                             levelCount;
0197     uint8_t                             padding2;
0198     uint8_t                             padding3;
0199     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   level;
0200 };
0201
0202 #define SISLANDS_SMC_VOLTAGEMASK_VDDC  0
0203 #define SISLANDS_SMC_VOLTAGEMASK_MVDD  1
0204 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2
0205 #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3
0206 #define SISLANDS_SMC_VOLTAGEMASK_MAX   4
0207
0208 struct SISLANDS_SMC_VOLTAGEMASKTABLE
0209 {
0210     uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX];
0211 };
0212
0213 typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE;
0214
0215 #define SISLANDS_MAX_NO_VREG_STEPS 32
0216
0217 struct SISLANDS_SMC_STATETABLE
0218 {
0219     uint8_t                 thermalProtectType;
0220     uint8_t                 systemFlags;
0221     uint8_t                 maxVDDCIndexInPPTable;
0222     uint8_t                 extraFlags;
0223     uint32_t                lowSMIO[SISLANDS_MAX_NO_VREG_STEPS];
0224     SISLANDS_SMC_VOLTAGEMASKTABLE       voltageMaskTable;
0225     SISLANDS_SMC_VOLTAGEMASKTABLE       phaseMaskTable;
0226     PP_SIslands_DPM2Parameters      dpm2Params;
0227     struct SISLANDS_SMC_SWSTATE_SINGLE  initialState;
0228     struct SISLANDS_SMC_SWSTATE_SINGLE  ACPIState;
0229     struct SISLANDS_SMC_SWSTATE_SINGLE  ULVState;
0230     SISLANDS_SMC_SWSTATE            driverState;
0231     SISLANDS_SMC_HW_PERFORMANCE_LEVEL   dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
0232 };
0233
0234 typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE;
0235
0236 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout         0x0
0237 #define SI_SMC_SOFT_REGISTER_delay_vreg               0xC
0238 #define SI_SMC_SOFT_REGISTER_delay_acpi               0x28
0239 #define SI_SMC_SOFT_REGISTER_seq_index                0x5C
0240 #define SI_SMC_SOFT_REGISTER_mvdd_chg_time            0x60
0241 #define SI_SMC_SOFT_REGISTER_mclk_switch_lim          0x70
0242 #define SI_SMC_SOFT_REGISTER_watermark_threshold      0x78
0243 #define SI_SMC_SOFT_REGISTER_phase_shedding_delay     0x88
0244 #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay    0x8C
0245 #define SI_SMC_SOFT_REGISTER_mc_block_delay           0x98
0246 #define SI_SMC_SOFT_REGISTER_ticks_per_us             0xA8
0247 #define SI_SMC_SOFT_REGISTER_crtc_index               0xC4
0248 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8
0249 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC
0250 #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width  0xF4
0251 #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen   0xFC
0252 #define SI_SMC_SOFT_REGISTER_vr_hot_gpio              0x100
0253 #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type     0x118
0254 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd   0x11c
0255 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc   0x120
0256
0257 struct PP_SIslands_FanTable
0258 {
0259     uint8_t  fdo_mode;
0260     uint8_t  padding;
0261     int16_t  temp_min;
0262     int16_t  temp_med;
0263     int16_t  temp_max;
0264     int16_t  slope1;
0265     int16_t  slope2;
0266     int16_t  fdo_min;
0267     int16_t  hys_up;
0268     int16_t  hys_down;
0269     int16_t  hys_slope;
0270     int16_t  temp_resp_lim;
0271     int16_t  temp_curr;
0272     int16_t  slope_curr;
0273     int16_t  pwm_curr;
0274     uint32_t refresh_period;
0275     int16_t  fdo_max;
0276     uint8_t  temp_src;
0277     int8_t  padding2;
0278 };
0279
0280 typedef struct PP_SIslands_FanTable PP_SIslands_FanTable;
0281
0282 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
0283 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32
0284
0285 #define SMC_SISLANDS_SCALE_I  7
0286 #define SMC_SISLANDS_SCALE_R 12
0287
0288 struct PP_SIslands_CacConfig
0289 {
0290     uint16_t   cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES];
0291     uint32_t   lkge_lut_V0;
0292     uint32_t   lkge_lut_Vstep;
0293     uint32_t   WinTime;
0294     uint32_t   R_LL;
0295     uint32_t   calculation_repeats;
0296     uint32_t   l2numWin_TDP;
0297     uint32_t   dc_cac;
0298     uint8_t    lts_truncate_n;
0299     uint8_t    SHIFT_N;
0300     uint8_t    log2_PG_LKG_SCALE;
0301     uint8_t    cac_temp;
0302     uint32_t   lkge_lut_T0;
0303     uint32_t   lkge_lut_Tstep;
0304 };
0305
0306 typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig;
0307
0308 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16
0309 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20
0310
0311 struct SMC_SIslands_MCRegisterAddress
0312 {
0313     uint16_t s0;
0314     uint16_t s1;
0315 };
0316
0317 typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress;
0318
0319 struct SMC_SIslands_MCRegisterSet
0320 {
0321     uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
0322 };
0323
0324 typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet;
0325
0326 struct SMC_SIslands_MCRegisters
0327 {
0328     uint8_t                             last;
0329     uint8_t                             reserved[3];
0330     SMC_SIslands_MCRegisterAddress      address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
0331     SMC_SIslands_MCRegisterSet          data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT];
0332 };
0333
0334 typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters;
0335
0336 struct SMC_SIslands_MCArbDramTimingRegisterSet
0337 {
0338     uint32_t mc_arb_dram_timing;
0339     uint32_t mc_arb_dram_timing2;
0340     uint8_t  mc_arb_rfsh_rate;
0341     uint8_t  mc_arb_burst_time;
0342     uint8_t  padding[2];
0343 };
0344
0345 typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet;
0346
0347 struct SMC_SIslands_MCArbDramTimingRegisters
0348 {
0349     uint8_t                                     arb_current;
0350     uint8_t                                     reserved[3];
0351     SMC_SIslands_MCArbDramTimingRegisterSet     data[16];
0352 };
0353
0354 typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters;
0355
0356 struct SMC_SISLANDS_SPLL_DIV_TABLE
0357 {
0358     uint32_t    freq[256];
0359     uint32_t    ss[256];
0360 };
0361
0362 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK  0x01ffffff
0363 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0
0364 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK   0xfe000000
0365 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT  25
0366 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK   0x000fffff
0367 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT  0
0368 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK   0xfff00000
0369 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT  20
0370
0371 typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE;
0372
0373 #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5
0374
0375 #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16
0376
0377 struct Smc_SIslands_DTE_Configuration
0378 {
0379     uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
0380     uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
0381     uint32_t K;
0382     uint32_t T0;
0383     uint32_t MaxT;
0384     uint8_t  WindowSize;
0385     uint8_t  Tdep_count;
0386     uint8_t  temp_select;
0387     uint8_t  DTE_mode;
0388     uint8_t  T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0389     uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0390     uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
0391     uint32_t Tthreshold;
0392 };
0393
0394 typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration;
0395
0396 #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1
0397
0398 #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000
0399
0400 #define SISLANDS_SMC_FIRMWARE_HEADER_version                   0x0
0401 #define SISLANDS_SMC_FIRMWARE_HEADER_flags                     0x4
0402 #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters             0xC
0403 #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable                0x10
0404 #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable                  0x14
0405 #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable            0x18
0406 #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable           0x24
0407 #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30
0408 #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable                 0x38
0409 #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration          0x40
0410 #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters            0x48
0411
0412 #pragma pack(pop)
0413
0414 int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
0415                 u32 smc_start_address,
0416                 const u8 *src, u32 byte_count, u32 limit);
0417 void amdgpu_si_start_smc(struct amdgpu_device *adev);
0418 void amdgpu_si_reset_smc(struct amdgpu_device *adev);
0419 int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev);
0420 void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable);
0421 bool amdgpu_si_is_smc_running(struct amdgpu_device *adev);
0422 PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
0423 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev);
0424 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
0425 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
0426                   u32 *value, u32 limit);
0427 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
0428                    u32 value, u32 limit);
0429
0430 #endif
0431