pm/legacy-dpm/kv_dpm.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __KV_DPM_H__
0024 #define __KV_DPM_H__
0025
0026 #define SMU__NUM_SCLK_DPM_STATE  8
0027 #define SMU__NUM_MCLK_DPM_LEVELS 4
0028 #define SMU__NUM_LCLK_DPM_LEVELS 8
0029 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
0030 #include "smu7_fusion.h"
0031 #include "ppsmc.h"
0032
0033 #define SUMO_MAX_HARDWARE_POWERLEVELS 5
0034
0035 #define SUMO_MAX_NUMBER_VOLTAGES    4
0036
0037 struct sumo_vid_mapping_entry {
0038     u16 vid_2bit;
0039     u16 vid_7bit;
0040 };
0041
0042 struct sumo_vid_mapping_table {
0043     u32 num_entries;
0044     struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
0045 };
0046
0047 struct sumo_sclk_voltage_mapping_entry {
0048     u32 sclk_frequency;
0049     u16 vid_2bit;
0050     u16 rsv;
0051 };
0052
0053 struct sumo_sclk_voltage_mapping_table {
0054     u32 num_max_dpm_entries;
0055     struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
0056 };
0057
0058 #define TRINITY_AT_DFLT            30
0059
0060 #define KV_NUM_NBPSTATES   4
0061
0062 enum kv_pt_config_reg_type {
0063     KV_CONFIGREG_MMR = 0,
0064     KV_CONFIGREG_SMC_IND,
0065     KV_CONFIGREG_DIDT_IND,
0066     KV_CONFIGREG_CACHE,
0067     KV_CONFIGREG_MAX
0068 };
0069
0070 struct kv_pt_config_reg {
0071     u32 offset;
0072     u32 mask;
0073     u32 shift;
0074     u32 value;
0075     enum kv_pt_config_reg_type type;
0076 };
0077
0078 struct kv_lcac_config_values {
0079     u32 block_id;
0080     u32 signal_id;
0081     u32 t;
0082 };
0083
0084 struct kv_lcac_config_reg {
0085     u32 cntl;
0086     u32 block_mask;
0087     u32 block_shift;
0088     u32 signal_mask;
0089     u32 signal_shift;
0090     u32 t_mask;
0091     u32 t_shift;
0092     u32 enable_mask;
0093     u32 enable_shift;
0094 };
0095
0096 struct kv_pl {
0097     u32 sclk;
0098     u8 vddc_index;
0099     u8 ds_divider_index;
0100     u8 ss_divider_index;
0101     u8 allow_gnb_slow;
0102     u8 force_nbp_state;
0103     u8 display_wm;
0104     u8 vce_wm;
0105 };
0106
0107 struct kv_ps {
0108     struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
0109     u32 num_levels;
0110     bool need_dfs_bypass;
0111     u8 dpm0_pg_nb_ps_lo;
0112     u8 dpm0_pg_nb_ps_hi;
0113     u8 dpmx_nb_ps_lo;
0114     u8 dpmx_nb_ps_hi;
0115 };
0116
0117 struct kv_sys_info {
0118     u32 bootup_uma_clk;
0119     u32 bootup_sclk;
0120     u32 dentist_vco_freq;
0121     u32 nb_dpm_enable;
0122     u32 nbp_memory_clock[KV_NUM_NBPSTATES];
0123     u32 nbp_n_clock[KV_NUM_NBPSTATES];
0124     u16 bootup_nb_voltage_index;
0125     u8 htc_tmp_lmt;
0126     u8 htc_hyst_lmt;
0127     struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
0128     struct sumo_vid_mapping_table vid_mapping_table;
0129     u32 uma_channel_number;
0130 };
0131
0132 struct kv_power_info {
0133     u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
0134     u32 voltage_drop_t;
0135     struct kv_sys_info sys_info;
0136     struct kv_pl boot_pl;
0137     bool enable_nb_ps_policy;
0138     bool disable_nb_ps3_in_battery;
0139     bool video_start;
0140     bool battery_state;
0141     u32 lowest_valid;
0142     u32 highest_valid;
0143     u16 high_voltage_t;
0144     bool cac_enabled;
0145     bool bapm_enable;
0146     /* smc offsets */
0147     u32 sram_end;
0148     u32 dpm_table_start;
0149     u32 soft_regs_start;
0150     /* dpm SMU tables */
0151     u8 graphics_dpm_level_count;
0152     u8 uvd_level_count;
0153     u8 vce_level_count;
0154     u8 acp_level_count;
0155     u8 samu_level_count;
0156     u16 fps_high_t;
0157     SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
0158     SMU7_Fusion_ACPILevel acpi_level;
0159     SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
0160     SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
0161     SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
0162     SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
0163     u8 uvd_boot_level;
0164     u8 vce_boot_level;
0165     u8 acp_boot_level;
0166     u8 samu_boot_level;
0167     u8 uvd_interval;
0168     u8 vce_interval;
0169     u8 acp_interval;
0170     u8 samu_interval;
0171     u8 graphics_boot_level;
0172     u8 graphics_interval;
0173     u8 graphics_therm_throttle_enable;
0174     u8 graphics_voltage_change_enable;
0175     u8 graphics_clk_slow_enable;
0176     u8 graphics_clk_slow_divider;
0177     u8 fps_low_t;
0178     u32 low_sclk_interrupt_t;
0179     bool uvd_power_gated;
0180     bool vce_power_gated;
0181     bool acp_power_gated;
0182     bool samu_power_gated;
0183     bool nb_dpm_enabled;
0184     /* flags */
0185     bool enable_didt;
0186     bool enable_dpm;
0187     bool enable_auto_thermal_throttling;
0188     bool enable_nb_dpm;
0189     /* caps */
0190     bool caps_cac;
0191     bool caps_power_containment;
0192     bool caps_sq_ramping;
0193     bool caps_db_ramping;
0194     bool caps_td_ramping;
0195     bool caps_tcp_ramping;
0196     bool caps_sclk_throttle_low_notification;
0197     bool caps_fps;
0198     bool caps_uvd_dpm;
0199     bool caps_uvd_pg;
0200     bool caps_vce_pg;
0201     bool caps_samu_pg;
0202     bool caps_acp_pg;
0203     bool caps_stable_p_state;
0204     bool caps_enable_dfs_bypass;
0205     bool caps_sclk_ds;
0206     struct amdgpu_ps current_rps;
0207     struct kv_ps current_ps;
0208     struct amdgpu_ps requested_rps;
0209     struct kv_ps requested_ps;
0210 };
0211
0212 /* XXX are these ok? */
0213 #define KV_TEMP_RANGE_MIN (90 * 1000)
0214 #define KV_TEMP_RANGE_MAX (120 * 1000)
0215
0216 /* kv_smc.c */
0217 int amdgpu_kv_notify_message_to_smu(struct amdgpu_device *adev, u32 id);
0218 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
0219 int amdgpu_kv_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
0220                       PPSMC_Msg msg, u32 parameter);
0221 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
0222                u32 *value, u32 limit);
0223 int amdgpu_kv_smc_dpm_enable(struct amdgpu_device *adev, bool enable);
0224 int amdgpu_kv_smc_bapm_enable(struct amdgpu_device *adev, bool enable);
0225 int amdgpu_kv_copy_bytes_to_smc(struct amdgpu_device *adev,
0226              u32 smc_start_address,
0227              const u8 *src, u32 byte_count, u32 limit);
0228
0229 #endif