pm/inc/smu_v13_0_0_pptable.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #ifndef SMU_13_0_0_PPTABLE_H
0023 #define SMU_13_0_0_PPTABLE_H
0024
0025 #pragma pack(push, 1)
0026
0027 #define SMU_13_0_0_TABLE_FORMAT_REVISION 15
0028
0029 //// POWERPLAYTABLE::ulPlatformCaps
0030 #define SMU_13_0_0_PP_PLATFORM_CAP_POWERPLAY 0x1        // This cap indicates whether CCC need to show Powerplay page.
0031 #define SMU_13_0_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS.
0032 #define SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC 0x4       // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.
0033 #define SMU_13_0_0_PP_PLATFORM_CAP_BACO 0x8             // This cap indicates whether board supports the BACO circuitry.
0034 #define SMU_13_0_0_PP_PLATFORM_CAP_MACO 0x10            // This cap indicates whether board supports the MACO circuitry.
0035 #define SMU_13_0_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20    // This cap indicates whether board supports the Shadow Pstate.
0036
0037 // SMU_13_0_0_PP_THERMALCONTROLLER - Thermal Controller Type
0038 #define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0
0039 #define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28
0040
0041 #define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x81        // OverDrive 8 Table Version 0.2
0042 #define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00
0043
0044 enum SMU_13_0_0_ODFEATURE_CAP
0045 {
0046     SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,
0047     SMU_13_0_0_ODCAP_GFXCLK_CURVE,
0048     SMU_13_0_0_ODCAP_UCLK_LIMITS,
0049     SMU_13_0_0_ODCAP_POWER_LIMIT,
0050     SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,
0051     SMU_13_0_0_ODCAP_FAN_SPEED_MIN,
0052     SMU_13_0_0_ODCAP_TEMPERATURE_FAN,
0053     SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM,
0054     SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE,
0055     SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL,
0056     SMU_13_0_0_ODCAP_AUTO_UV_ENGINE,
0057     SMU_13_0_0_ODCAP_AUTO_OC_ENGINE,
0058     SMU_13_0_0_ODCAP_AUTO_OC_MEMORY,
0059     SMU_13_0_0_ODCAP_FAN_CURVE,
0060     SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
0061     SMU_13_0_0_ODCAP_POWER_MODE,
0062     SMU_13_0_0_ODCAP_COUNT,
0063 };
0064
0065 enum SMU_13_0_0_ODFEATURE_ID
0066 {
0067     SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS           = 1 << SMU_13_0_0_ODCAP_GFXCLK_LIMITS,           //GFXCLK Limit feature
0068     SMU_13_0_0_ODFEATURE_GFXCLK_CURVE            = 1 << SMU_13_0_0_ODCAP_GFXCLK_CURVE,            //GFXCLK Curve feature
0069     SMU_13_0_0_ODFEATURE_UCLK_LIMITS             = 1 << SMU_13_0_0_ODCAP_UCLK_LIMITS,             //UCLK Limit feature
0070     SMU_13_0_0_ODFEATURE_POWER_LIMIT             = 1 << SMU_13_0_0_ODCAP_POWER_LIMIT,             //Power Limit feature
0071     SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT      = 1 << SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,      //Fan Acoustic RPM feature
0072     SMU_13_0_0_ODFEATURE_FAN_SPEED_MIN           = 1 << SMU_13_0_0_ODCAP_FAN_SPEED_MIN,           //Minimum Fan Speed feature
0073     SMU_13_0_0_ODFEATURE_TEMPERATURE_FAN         = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_FAN,         //Fan Target Temperature Limit feature
0074     SMU_13_0_0_ODFEATURE_TEMPERATURE_SYSTEM      = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM,      //Operating Temperature Limit feature
0075     SMU_13_0_0_ODFEATURE_MEMORY_TIMING_TUNE      = 1 << SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE,      //AC Timing Tuning feature
0076     SMU_13_0_0_ODFEATURE_FAN_ZERO_RPM_CONTROL    = 1 << SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL,    //Zero RPM feature
0077     SMU_13_0_0_ODFEATURE_AUTO_UV_ENGINE          = 1 << SMU_13_0_0_ODCAP_AUTO_UV_ENGINE,          //Auto Under Volt GFXCLK feature
0078     SMU_13_0_0_ODFEATURE_AUTO_OC_ENGINE          = 1 << SMU_13_0_0_ODCAP_AUTO_OC_ENGINE,          //Auto Over Clock GFXCLK feature
0079     SMU_13_0_0_ODFEATURE_AUTO_OC_MEMORY          = 1 << SMU_13_0_0_ODCAP_AUTO_OC_MEMORY,          //Auto Over Clock MCLK feature
0080     SMU_13_0_0_ODFEATURE_FAN_CURVE               = 1 << SMU_13_0_0_ODCAP_FAN_CURVE,               //Fan Curve feature
0081     SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature
0082     SMU_13_0_0_ODFEATURE_POWER_MODE              = 1 << SMU_13_0_0_ODCAP_POWER_MODE,              //Optimized GPU Power Mode feature
0083     SMU_13_0_0_ODFEATURE_COUNT                   = 16,
0084 };
0085
0086 #define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features
0087
0088 enum SMU_13_0_0_ODSETTING_ID
0089 {
0090     SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,
0091     SMU_13_0_0_ODSETTING_GFXCLKFMIN,
0092     SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_A,
0093     SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_B,
0094     SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_C,
0095     SMU_13_0_0_ODSETTING_CUSTOM_CURVE_VFT_FMIN,
0096     SMU_13_0_0_ODSETTING_UCLKFMIN,
0097     SMU_13_0_0_ODSETTING_UCLKFMAX,
0098     SMU_13_0_0_ODSETTING_POWERPERCENTAGE,
0099     SMU_13_0_0_ODSETTING_FANRPMMIN,
0100     SMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMIT,
0101     SMU_13_0_0_ODSETTING_FANTARGETTEMPERATURE,
0102     SMU_13_0_0_ODSETTING_OPERATINGTEMPMAX,
0103     SMU_13_0_0_ODSETTING_ACTIMING,
0104     SMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
0105     SMU_13_0_0_ODSETTING_AUTOUVENGINE,
0106     SMU_13_0_0_ODSETTING_AUTOOCENGINE,
0107     SMU_13_0_0_ODSETTING_AUTOOCMEMORY,
0108     SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1,
0109     SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1,
0110     SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2,
0111     SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2,
0112     SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3,
0113     SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3,
0114     SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4,
0115     SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4,
0116     SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5,
0117     SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5,
0118     SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT,
0119     SMU_13_0_0_ODSETTING_POWER_MODE,
0120     SMU_13_0_0_ODSETTING_COUNT,
0121 };
0122 #define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings
0123
0124 enum SMU_13_0_0_PWRMODE_SETTING
0125 {
0126     SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,
0127     SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,
0128     SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,
0129     SMU_13_0_0_PMSETTING_POWER_LIMIT_RAGE,
0130     SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_QUIET,
0131     SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_BALANCE,
0132     SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_TURBO,
0133     SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_RAGE,
0134     SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_QUIET,
0135     SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_BALANCE,
0136     SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_TURBO,
0137     SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_RAGE,
0138     SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_QUIET,
0139     SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE,
0140     SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO,
0141     SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE,
0142 };
0143 #define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings
0144
0145 struct smu_13_0_0_overdrive_table
0146 {
0147     uint8_t revision;                             //Revision = SMU_13_0_0_PP_OVERDRIVE_VERSION
0148     uint8_t reserve[3];                           //Zero filled field reserved for future use
0149     uint32_t feature_count;                       //Total number of supported features
0150     uint32_t setting_count;                       //Total number of supported settings
0151     uint8_t cap[SMU_13_0_0_MAX_ODFEATURE];        //OD feature support flags
0152     uint32_t max[SMU_13_0_0_MAX_ODSETTING];       //default maximum settings
0153     uint32_t min[SMU_13_0_0_MAX_ODSETTING];       //default minimum settings
0154     int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power mode feature settings
0155 };
0156
0157 enum SMU_13_0_0_PPCLOCK_ID
0158 {
0159     SMU_13_0_0_PPCLOCK_GFXCLK = 0,
0160     SMU_13_0_0_PPCLOCK_SOCCLK,
0161     SMU_13_0_0_PPCLOCK_UCLK,
0162     SMU_13_0_0_PPCLOCK_FCLK,
0163     SMU_13_0_0_PPCLOCK_DCLK_0,
0164     SMU_13_0_0_PPCLOCK_VCLK_0,
0165     SMU_13_0_0_PPCLOCK_DCLK_1,
0166     SMU_13_0_0_PPCLOCK_VCLK_1,
0167     SMU_13_0_0_PPCLOCK_DCEFCLK,
0168     SMU_13_0_0_PPCLOCK_DISPCLK,
0169     SMU_13_0_0_PPCLOCK_PIXCLK,
0170     SMU_13_0_0_PPCLOCK_PHYCLK,
0171     SMU_13_0_0_PPCLOCK_DTBCLK,
0172     SMU_13_0_0_PPCLOCK_COUNT,
0173 };
0174 #define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks
0175
0176 struct smu_13_0_0_powerplay_table
0177 {
0178     struct atom_common_table_header header; //For SMU13, header.format_revision = 15, header.content_revision = 0
0179     uint8_t table_revision;                 //For SMU13, table_revision = 2
0180     uint8_t padding;
0181     uint16_t table_size;                    //Driver portion table size. The offset to smc_pptable including header size
0182     uint32_t golden_pp_id;                  //PPGen use only: PP Table ID on the Golden Data Base
0183     uint32_t golden_revision;               //PPGen use only: PP Table Revision on the Golden Data Base
0184     uint16_t format_id;                     //PPGen use only: PPTable for different ASICs. For SMU13 this should be 0x80
0185     uint32_t platform_caps;                 //POWERPLAYABLE::ulPlatformCaps
0186
0187     uint8_t thermal_controller_type; //one of SMU_13_0_0_PP_THERMALCONTROLLER
0188
0189     uint16_t small_power_limit1;
0190     uint16_t small_power_limit2;
0191     uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit.
0192     uint16_t software_shutdown_temp;
0193
0194     uint32_t reserve[45];
0195
0196     struct smu_13_0_0_overdrive_table overdrive_table;
0197     uint8_t padding1;
0198     PPTable_t smc_pptable; //PPTable_t in driver_if.h
0199 };
0200
0201 #pragma pack(pop)
0202
0203 #endif