pm/inc/amdgpu_dpm.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_DPM_H__
0024 #define __AMDGPU_DPM_H__
0025
0026 /* Argument for PPSMC_MSG_GpuChangeState */
0027 enum gfx_change_state {
0028     sGpuChangeState_D0Entry = 1,
0029     sGpuChangeState_D3Entry,
0030 };
0031
0032 enum amdgpu_int_thermal_type {
0033     THERMAL_TYPE_NONE,
0034     THERMAL_TYPE_EXTERNAL,
0035     THERMAL_TYPE_EXTERNAL_GPIO,
0036     THERMAL_TYPE_RV6XX,
0037     THERMAL_TYPE_RV770,
0038     THERMAL_TYPE_ADT7473_WITH_INTERNAL,
0039     THERMAL_TYPE_EVERGREEN,
0040     THERMAL_TYPE_SUMO,
0041     THERMAL_TYPE_NI,
0042     THERMAL_TYPE_SI,
0043     THERMAL_TYPE_EMC2103_WITH_INTERNAL,
0044     THERMAL_TYPE_CI,
0045     THERMAL_TYPE_KV,
0046 };
0047
0048 enum amdgpu_runpm_mode {
0049     AMDGPU_RUNPM_NONE,
0050     AMDGPU_RUNPM_PX,
0051     AMDGPU_RUNPM_BOCO,
0052     AMDGPU_RUNPM_BACO,
0053 };
0054
0055 struct amdgpu_ps {
0056     u32 caps; /* vbios flags */
0057     u32 class; /* vbios flags */
0058     u32 class2; /* vbios flags */
0059     /* UVD clocks */
0060     u32 vclk;
0061     u32 dclk;
0062     /* VCE clocks */
0063     u32 evclk;
0064     u32 ecclk;
0065     bool vce_active;
0066     enum amd_vce_level vce_level;
0067     /* asic priv */
0068     void *ps_priv;
0069 };
0070
0071 struct amdgpu_dpm_thermal {
0072     /* thermal interrupt work */
0073     struct work_struct work;
0074     /* low temperature threshold */
0075     int                min_temp;
0076     /* high temperature threshold */
0077     int                max_temp;
0078     /* edge max emergency(shutdown) temp */
0079     int                max_edge_emergency_temp;
0080     /* hotspot low temperature threshold */
0081     int                min_hotspot_temp;
0082     /* hotspot high temperature critical threshold */
0083     int                max_hotspot_crit_temp;
0084     /* hotspot max emergency(shutdown) temp */
0085     int                max_hotspot_emergency_temp;
0086     /* memory low temperature threshold */
0087     int                min_mem_temp;
0088     /* memory high temperature critical threshold */
0089     int                max_mem_crit_temp;
0090     /* memory max emergency(shutdown) temp */
0091     int                max_mem_emergency_temp;
0092     /* was last interrupt low to high or high to low */
0093     bool               high_to_low;
0094     /* interrupt source */
0095     struct amdgpu_irq_src   irq;
0096 };
0097
0098 struct amdgpu_clock_and_voltage_limits {
0099     u32 sclk;
0100     u32 mclk;
0101     u16 vddc;
0102     u16 vddci;
0103 };
0104
0105 struct amdgpu_clock_array {
0106     u32 count;
0107     u32 *values;
0108 };
0109
0110 struct amdgpu_clock_voltage_dependency_entry {
0111     u32 clk;
0112     u16 v;
0113 };
0114
0115 struct amdgpu_clock_voltage_dependency_table {
0116     u32 count;
0117     struct amdgpu_clock_voltage_dependency_entry *entries;
0118 };
0119
0120 union amdgpu_cac_leakage_entry {
0121     struct {
0122         u16 vddc;
0123         u32 leakage;
0124     };
0125     struct {
0126         u16 vddc1;
0127         u16 vddc2;
0128         u16 vddc3;
0129     };
0130 };
0131
0132 struct amdgpu_cac_leakage_table {
0133     u32 count;
0134     union amdgpu_cac_leakage_entry *entries;
0135 };
0136
0137 struct amdgpu_phase_shedding_limits_entry {
0138     u16 voltage;
0139     u32 sclk;
0140     u32 mclk;
0141 };
0142
0143 struct amdgpu_phase_shedding_limits_table {
0144     u32 count;
0145     struct amdgpu_phase_shedding_limits_entry *entries;
0146 };
0147
0148 struct amdgpu_uvd_clock_voltage_dependency_entry {
0149     u32 vclk;
0150     u32 dclk;
0151     u16 v;
0152 };
0153
0154 struct amdgpu_uvd_clock_voltage_dependency_table {
0155     u8 count;
0156     struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
0157 };
0158
0159 struct amdgpu_vce_clock_voltage_dependency_entry {
0160     u32 ecclk;
0161     u32 evclk;
0162     u16 v;
0163 };
0164
0165 struct amdgpu_vce_clock_voltage_dependency_table {
0166     u8 count;
0167     struct amdgpu_vce_clock_voltage_dependency_entry *entries;
0168 };
0169
0170 struct amdgpu_ppm_table {
0171     u8 ppm_design;
0172     u16 cpu_core_number;
0173     u32 platform_tdp;
0174     u32 small_ac_platform_tdp;
0175     u32 platform_tdc;
0176     u32 small_ac_platform_tdc;
0177     u32 apu_tdp;
0178     u32 dgpu_tdp;
0179     u32 dgpu_ulv_power;
0180     u32 tj_max;
0181 };
0182
0183 struct amdgpu_cac_tdp_table {
0184     u16 tdp;
0185     u16 configurable_tdp;
0186     u16 tdc;
0187     u16 battery_power_limit;
0188     u16 small_power_limit;
0189     u16 low_cac_leakage;
0190     u16 high_cac_leakage;
0191     u16 maximum_power_delivery_limit;
0192 };
0193
0194 struct amdgpu_dpm_dynamic_state {
0195     struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
0196     struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
0197     struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
0198     struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
0199     struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
0200     struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
0201     struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
0202     struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
0203     struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
0204     struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
0205     struct amdgpu_clock_array valid_sclk_values;
0206     struct amdgpu_clock_array valid_mclk_values;
0207     struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
0208     struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
0209     u32 mclk_sclk_ratio;
0210     u32 sclk_mclk_delta;
0211     u16 vddc_vddci_delta;
0212     u16 min_vddc_for_pcie_gen2;
0213     struct amdgpu_cac_leakage_table cac_leakage_table;
0214     struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
0215     struct amdgpu_ppm_table *ppm_table;
0216     struct amdgpu_cac_tdp_table *cac_tdp_table;
0217 };
0218
0219 struct amdgpu_dpm_fan {
0220     u16 t_min;
0221     u16 t_med;
0222     u16 t_high;
0223     u16 pwm_min;
0224     u16 pwm_med;
0225     u16 pwm_high;
0226     u8 t_hyst;
0227     u32 cycle_delay;
0228     u16 t_max;
0229     u8 control_mode;
0230     u16 default_max_fan_pwm;
0231     u16 default_fan_output_sensitivity;
0232     u16 fan_output_sensitivity;
0233     bool ucode_fan_control;
0234 };
0235
0236 struct amdgpu_dpm {
0237     struct amdgpu_ps        *ps;
0238     /* number of valid power states */
0239     int                     num_ps;
0240     /* current power state that is active */
0241     struct amdgpu_ps        *current_ps;
0242     /* requested power state */
0243     struct amdgpu_ps        *requested_ps;
0244     /* boot up power state */
0245     struct amdgpu_ps        *boot_ps;
0246     /* default uvd power state */
0247     struct amdgpu_ps        *uvd_ps;
0248     /* vce requirements */
0249     u32                  num_of_vce_states;
0250     struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
0251     enum amd_vce_level vce_level;
0252     enum amd_pm_state_type state;
0253     enum amd_pm_state_type user_state;
0254     enum amd_pm_state_type last_state;
0255     enum amd_pm_state_type last_user_state;
0256     u32                     platform_caps;
0257     u32                     voltage_response_time;
0258     u32                     backbias_response_time;
0259     void                    *priv;
0260     u32         new_active_crtcs;
0261     int         new_active_crtc_count;
0262     u32         current_active_crtcs;
0263     int         current_active_crtc_count;
0264     struct amdgpu_dpm_dynamic_state dyn_state;
0265     struct amdgpu_dpm_fan fan;
0266     u32 tdp_limit;
0267     u32 near_tdp_limit;
0268     u32 near_tdp_limit_adjusted;
0269     u32 sq_ramping_threshold;
0270     u32 cac_leakage;
0271     u16 tdp_od_limit;
0272     u32 tdp_adjustment;
0273     u16 load_line_slope;
0274     bool power_control;
0275     /* special states active */
0276     bool                    thermal_active;
0277     bool                    uvd_active;
0278     bool                    vce_active;
0279     /* thermal handling */
0280     struct amdgpu_dpm_thermal thermal;
0281     /* forced levels */
0282     enum amd_dpm_forced_level forced_level;
0283 };
0284
0285 enum ip_power_state {
0286     POWER_STATE_UNKNOWN,
0287     POWER_STATE_ON,
0288     POWER_STATE_OFF,
0289 };
0290
0291 /* Used to mask smu debug modes */
0292 #define SMU_DEBUG_HALT_ON_ERROR     0x1
0293
0294 #define MAX_SMU_I2C_BUSES       2
0295
0296 struct amdgpu_smu_i2c_bus {
0297     struct i2c_adapter adapter;
0298     struct amdgpu_device *adev;
0299     int port;
0300     struct mutex mutex;
0301 };
0302
0303 struct config_table_setting
0304 {
0305     uint16_t gfxclk_average_tau;
0306     uint16_t socclk_average_tau;
0307     uint16_t uclk_average_tau;
0308     uint16_t gfx_activity_average_tau;
0309     uint16_t mem_activity_average_tau;
0310     uint16_t socket_power_average_tau;
0311     uint16_t apu_socket_power_average_tau;
0312     uint16_t fclk_average_tau;
0313 };
0314
0315 struct amdgpu_pm {
0316     struct mutex        mutex;
0317     u32                     current_sclk;
0318     u32                     current_mclk;
0319     u32                     default_sclk;
0320     u32                     default_mclk;
0321     struct amdgpu_i2c_chan *i2c_bus;
0322     bool                    bus_locked;
0323     /* internal thermal controller on rv6xx+ */
0324     enum amdgpu_int_thermal_type int_thermal_type;
0325     struct device           *int_hwmon_dev;
0326     /* fan control parameters */
0327     bool                    no_fan;
0328     u8                      fan_pulses_per_revolution;
0329     u8                      fan_min_rpm;
0330     u8                      fan_max_rpm;
0331     /* dpm */
0332     bool                    dpm_enabled;
0333     bool                    sysfs_initialized;
0334     struct amdgpu_dpm       dpm;
0335     const struct firmware   *fw;    /* SMC firmware */
0336     uint32_t                fw_version;
0337     uint32_t                pcie_gen_mask;
0338     uint32_t                pcie_mlw_mask;
0339     struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
0340     uint32_t                smu_prv_buffer_size;
0341     struct amdgpu_bo        *smu_prv_buffer;
0342     bool ac_power;
0343     /* powerplay feature */
0344     uint32_t pp_feature;
0345
0346     /* Used for I2C access to various EEPROMs on relevant ASICs */
0347     struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES];
0348     struct i2c_adapter     *ras_eeprom_i2c_bus;
0349     struct i2c_adapter     *fru_eeprom_i2c_bus;
0350     struct list_head    pm_attr_list;
0351
0352     atomic_t        pwr_state[AMD_IP_BLOCK_TYPE_NUM];
0353
0354     /*
0355      * 0 = disabled (default), otherwise enable corresponding debug mode
0356      */
0357     uint32_t        smu_debug_mask;
0358
0359     bool            pp_force_state_enabled;
0360
0361     struct mutex            stable_pstate_ctx_lock;
0362     struct amdgpu_ctx       *stable_pstate_ctx;
0363
0364     struct config_table_setting config_table;
0365     /* runtime mode */
0366     enum amdgpu_runpm_mode rpm_mode;
0367 };
0368
0369 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
0370                void *data, uint32_t *size);
0371
0372 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
0373                       uint32_t block_type, bool gate);
0374
0375 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
0376
0377 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
0378
0379 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
0380                    uint32_t pstate);
0381
0382 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
0383                     enum PP_SMC_POWER_PROFILE type,
0384                     bool en);
0385
0386 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
0387
0388 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
0389
0390 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
0391
0392 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
0393 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
0394
0395 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
0396                  enum pp_mp1_state mp1_state);
0397
0398 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
0399
0400 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
0401
0402 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
0403
0404 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
0405                  uint32_t cstate);
0406
0407 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en);
0408
0409 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);
0410
0411 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
0412                       uint32_t msg_id);
0413
0414 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
0415                   bool acquire);
0416
0417 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
0418
0419 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
0420 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
0421 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
0422 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
0423 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
0424 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
0425 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
0426 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);
0427 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
0428                        enum pp_clock_type type,
0429                        uint32_t *min,
0430                        uint32_t *max);
0431 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
0432                         enum pp_clock_type type,
0433                         uint32_t min,
0434                         uint32_t max);
0435 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
0436 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
0437                uint64_t event_arg);
0438 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
0439 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev);
0440 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
0441                  enum gfx_change_state state);
0442 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
0443                 void *umc_ecc);
0444 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
0445                              uint32_t idx);
0446 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state);
0447 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
0448                 enum amd_pm_state_type state);
0449 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev);
0450 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
0451                        enum amd_dpm_forced_level level);
0452 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
0453                  struct pp_states_info *states);
0454 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
0455                   enum amd_pp_task task_id,
0456                   enum amd_pm_state_type *user_state);
0457 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table);
0458 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
0459                       uint32_t type,
0460                       long *input,
0461                       uint32_t size);
0462 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
0463                   uint32_t type,
0464                   long *input,
0465                   uint32_t size);
0466 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
0467                   enum pp_clock_type type,
0468                   char *buf);
0469 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
0470                   enum pp_clock_type type,
0471                   char *buf,
0472                   int *offset);
0473 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
0474                     uint64_t ppfeature_masks);
0475 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf);
0476 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
0477                  enum pp_clock_type type,
0478                  uint32_t mask);
0479 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev);
0480 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);
0481 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev);
0482 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);
0483 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
0484                       char *buf);
0485 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
0486                       long *input, uint32_t size);
0487 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);
0488 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
0489                     uint32_t *fan_mode);
0490 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
0491                  uint32_t speed);
0492 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
0493                  uint32_t *speed);
0494 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
0495                  uint32_t *speed);
0496 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
0497                  uint32_t speed);
0498 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
0499                     uint32_t mode);
0500 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
0501                    uint32_t *limit,
0502                    enum pp_power_limit_level pp_limit_level,
0503                    enum pp_power_type power_type);
0504 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
0505                    uint32_t limit);
0506 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev);
0507 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
0508                                struct seq_file *m);
0509 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
0510                        void **addr,
0511                        size_t *size);
0512 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
0513 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
0514                 const char *buf,
0515                 size_t size);
0516 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev);
0517 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev);
0518 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
0519                         const struct amd_pp_display_configuration *input);
0520 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
0521                  enum amd_pp_clock_type type,
0522                  struct amd_pp_clocks *clocks);
0523 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
0524                         struct amd_pp_simple_clock_info *clocks);
0525 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
0526                           enum amd_pp_clock_type type,
0527                           struct pp_clock_levels_with_latency *clocks);
0528 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
0529                           enum amd_pp_clock_type type,
0530                           struct pp_clock_levels_with_voltage *clocks);
0531 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
0532                            void *clock_ranges);
0533 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
0534                          struct pp_display_clock_request *clock);
0535 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
0536                   struct amd_pp_clock_info *clocks);
0537 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev);
0538 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
0539                     uint32_t count);
0540 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
0541                       uint32_t clock);
0542 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
0543                          uint32_t clock);
0544 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
0545                       uint32_t clock);
0546 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
0547                            bool disable_memory_clock_switch);
0548 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
0549                         struct pp_smu_nv_clock_table *max_clocks);
0550 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
0551                           unsigned int *clock_values_in_khz,
0552                           unsigned int *num_states);
0553 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
0554                    struct dpm_clocks *clock_table);
0555 #endif