amd/pm/amdgpu_dpm_internal.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "amdgpu_display.h"
0026 #include "hwmgr.h"
0027 #include "amdgpu_smu.h"
0028 #include "amdgpu_dpm_internal.h"
0029
0030 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev)
0031 {
0032     struct drm_device *ddev = adev_to_drm(adev);
0033     struct drm_crtc *crtc;
0034     struct amdgpu_crtc *amdgpu_crtc;
0035
0036     adev->pm.dpm.new_active_crtcs = 0;
0037     adev->pm.dpm.new_active_crtc_count = 0;
0038     if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
0039         list_for_each_entry(crtc,
0040                     &ddev->mode_config.crtc_list, head) {
0041             amdgpu_crtc = to_amdgpu_crtc(crtc);
0042             if (amdgpu_crtc->enabled) {
0043                 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
0044                 adev->pm.dpm.new_active_crtc_count++;
0045             }
0046         }
0047     }
0048 }
0049
0050 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev)
0051 {
0052     struct drm_device *dev = adev_to_drm(adev);
0053     struct drm_crtc *crtc;
0054     struct amdgpu_crtc *amdgpu_crtc;
0055     u32 vblank_in_pixels;
0056     u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
0057
0058     if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
0059         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0060             amdgpu_crtc = to_amdgpu_crtc(crtc);
0061             if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
0062                 vblank_in_pixels =
0063                     amdgpu_crtc->hw_mode.crtc_htotal *
0064                     (amdgpu_crtc->hw_mode.crtc_vblank_end -
0065                     amdgpu_crtc->hw_mode.crtc_vdisplay +
0066                     (amdgpu_crtc->v_border * 2));
0067
0068                 vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;
0069                 break;
0070             }
0071         }
0072     }
0073
0074     return vblank_time_us;
0075 }
0076
0077 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev)
0078 {
0079     struct drm_device *dev = adev_to_drm(adev);
0080     struct drm_crtc *crtc;
0081     struct amdgpu_crtc *amdgpu_crtc;
0082     u32 vrefresh = 0;
0083
0084     if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
0085         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0086             amdgpu_crtc = to_amdgpu_crtc(crtc);
0087             if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {
0088                 vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
0089                 break;
0090             }
0091         }
0092     }
0093
0094     return vrefresh;
0095 }