amd/include/vi_structs.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef VI_STRUCTS_H_
0025 #define VI_STRUCTS_H_
0026
0027 struct vi_sdma_mqd {
0028     uint32_t sdmax_rlcx_rb_cntl;
0029     uint32_t sdmax_rlcx_rb_base;
0030     uint32_t sdmax_rlcx_rb_base_hi;
0031     uint32_t sdmax_rlcx_rb_rptr;
0032     uint32_t sdmax_rlcx_rb_wptr;
0033     uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
0034     uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
0035     uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
0036     uint32_t sdmax_rlcx_rb_rptr_addr_hi;
0037     uint32_t sdmax_rlcx_rb_rptr_addr_lo;
0038     uint32_t sdmax_rlcx_ib_cntl;
0039     uint32_t sdmax_rlcx_ib_rptr;
0040     uint32_t sdmax_rlcx_ib_offset;
0041     uint32_t sdmax_rlcx_ib_base_lo;
0042     uint32_t sdmax_rlcx_ib_base_hi;
0043     uint32_t sdmax_rlcx_ib_size;
0044     uint32_t sdmax_rlcx_skip_cntl;
0045     uint32_t sdmax_rlcx_context_status;
0046     uint32_t sdmax_rlcx_doorbell;
0047     uint32_t sdmax_rlcx_virtual_addr;
0048     uint32_t sdmax_rlcx_ape1_cntl;
0049     uint32_t sdmax_rlcx_doorbell_log;
0050     uint32_t reserved_22;
0051     uint32_t reserved_23;
0052     uint32_t reserved_24;
0053     uint32_t reserved_25;
0054     uint32_t reserved_26;
0055     uint32_t reserved_27;
0056     uint32_t reserved_28;
0057     uint32_t reserved_29;
0058     uint32_t reserved_30;
0059     uint32_t reserved_31;
0060     uint32_t reserved_32;
0061     uint32_t reserved_33;
0062     uint32_t reserved_34;
0063     uint32_t reserved_35;
0064     uint32_t reserved_36;
0065     uint32_t reserved_37;
0066     uint32_t reserved_38;
0067     uint32_t reserved_39;
0068     uint32_t reserved_40;
0069     uint32_t reserved_41;
0070     uint32_t reserved_42;
0071     uint32_t reserved_43;
0072     uint32_t reserved_44;
0073     uint32_t reserved_45;
0074     uint32_t reserved_46;
0075     uint32_t reserved_47;
0076     uint32_t reserved_48;
0077     uint32_t reserved_49;
0078     uint32_t reserved_50;
0079     uint32_t reserved_51;
0080     uint32_t reserved_52;
0081     uint32_t reserved_53;
0082     uint32_t reserved_54;
0083     uint32_t reserved_55;
0084     uint32_t reserved_56;
0085     uint32_t reserved_57;
0086     uint32_t reserved_58;
0087     uint32_t reserved_59;
0088     uint32_t reserved_60;
0089     uint32_t reserved_61;
0090     uint32_t reserved_62;
0091     uint32_t reserved_63;
0092     uint32_t reserved_64;
0093     uint32_t reserved_65;
0094     uint32_t reserved_66;
0095     uint32_t reserved_67;
0096     uint32_t reserved_68;
0097     uint32_t reserved_69;
0098     uint32_t reserved_70;
0099     uint32_t reserved_71;
0100     uint32_t reserved_72;
0101     uint32_t reserved_73;
0102     uint32_t reserved_74;
0103     uint32_t reserved_75;
0104     uint32_t reserved_76;
0105     uint32_t reserved_77;
0106     uint32_t reserved_78;
0107     uint32_t reserved_79;
0108     uint32_t reserved_80;
0109     uint32_t reserved_81;
0110     uint32_t reserved_82;
0111     uint32_t reserved_83;
0112     uint32_t reserved_84;
0113     uint32_t reserved_85;
0114     uint32_t reserved_86;
0115     uint32_t reserved_87;
0116     uint32_t reserved_88;
0117     uint32_t reserved_89;
0118     uint32_t reserved_90;
0119     uint32_t reserved_91;
0120     uint32_t reserved_92;
0121     uint32_t reserved_93;
0122     uint32_t reserved_94;
0123     uint32_t reserved_95;
0124     uint32_t reserved_96;
0125     uint32_t reserved_97;
0126     uint32_t reserved_98;
0127     uint32_t reserved_99;
0128     uint32_t reserved_100;
0129     uint32_t reserved_101;
0130     uint32_t reserved_102;
0131     uint32_t reserved_103;
0132     uint32_t reserved_104;
0133     uint32_t reserved_105;
0134     uint32_t reserved_106;
0135     uint32_t reserved_107;
0136     uint32_t reserved_108;
0137     uint32_t reserved_109;
0138     uint32_t reserved_110;
0139     uint32_t reserved_111;
0140     uint32_t reserved_112;
0141     uint32_t reserved_113;
0142     uint32_t reserved_114;
0143     uint32_t reserved_115;
0144     uint32_t reserved_116;
0145     uint32_t reserved_117;
0146     uint32_t reserved_118;
0147     uint32_t reserved_119;
0148     uint32_t reserved_120;
0149     uint32_t reserved_121;
0150     uint32_t reserved_122;
0151     uint32_t reserved_123;
0152     uint32_t reserved_124;
0153     uint32_t reserved_125;
0154     /* reserved_126,127: repurposed for driver-internal use */
0155     uint32_t sdma_engine_id;
0156     uint32_t sdma_queue_id;
0157 };
0158
0159 struct vi_mqd {
0160     uint32_t header;
0161     uint32_t compute_dispatch_initiator;
0162     uint32_t compute_dim_x;
0163     uint32_t compute_dim_y;
0164     uint32_t compute_dim_z;
0165     uint32_t compute_start_x;
0166     uint32_t compute_start_y;
0167     uint32_t compute_start_z;
0168     uint32_t compute_num_thread_x;
0169     uint32_t compute_num_thread_y;
0170     uint32_t compute_num_thread_z;
0171     uint32_t compute_pipelinestat_enable;
0172     uint32_t compute_perfcount_enable;
0173     uint32_t compute_pgm_lo;
0174     uint32_t compute_pgm_hi;
0175     uint32_t compute_tba_lo;
0176     uint32_t compute_tba_hi;
0177     uint32_t compute_tma_lo;
0178     uint32_t compute_tma_hi;
0179     uint32_t compute_pgm_rsrc1;
0180     uint32_t compute_pgm_rsrc2;
0181     uint32_t compute_vmid;
0182     uint32_t compute_resource_limits;
0183     uint32_t compute_static_thread_mgmt_se0;
0184     uint32_t compute_static_thread_mgmt_se1;
0185     uint32_t compute_tmpring_size;
0186     uint32_t compute_static_thread_mgmt_se2;
0187     uint32_t compute_static_thread_mgmt_se3;
0188     uint32_t compute_restart_x;
0189     uint32_t compute_restart_y;
0190     uint32_t compute_restart_z;
0191     uint32_t compute_thread_trace_enable;
0192     uint32_t compute_misc_reserved;
0193     uint32_t compute_dispatch_id;
0194     uint32_t compute_threadgroup_id;
0195     uint32_t compute_relaunch;
0196     uint32_t compute_wave_restore_addr_lo;
0197     uint32_t compute_wave_restore_addr_hi;
0198     uint32_t compute_wave_restore_control;
0199     uint32_t reserved9;
0200     uint32_t reserved10;
0201     uint32_t reserved11;
0202     uint32_t reserved12;
0203     uint32_t reserved13;
0204     uint32_t reserved14;
0205     uint32_t reserved15;
0206     uint32_t reserved16;
0207     uint32_t reserved17;
0208     uint32_t reserved18;
0209     uint32_t reserved19;
0210     uint32_t reserved20;
0211     uint32_t reserved21;
0212     uint32_t reserved22;
0213     uint32_t reserved23;
0214     uint32_t reserved24;
0215     uint32_t reserved25;
0216     uint32_t reserved26;
0217     uint32_t reserved27;
0218     uint32_t reserved28;
0219     uint32_t reserved29;
0220     uint32_t reserved30;
0221     uint32_t reserved31;
0222     uint32_t reserved32;
0223     uint32_t reserved33;
0224     uint32_t reserved34;
0225     uint32_t compute_user_data_0;
0226     uint32_t compute_user_data_1;
0227     uint32_t compute_user_data_2;
0228     uint32_t compute_user_data_3;
0229     uint32_t compute_user_data_4;
0230     uint32_t compute_user_data_5;
0231     uint32_t compute_user_data_6;
0232     uint32_t compute_user_data_7;
0233     uint32_t compute_user_data_8;
0234     uint32_t compute_user_data_9;
0235     uint32_t compute_user_data_10;
0236     uint32_t compute_user_data_11;
0237     uint32_t compute_user_data_12;
0238     uint32_t compute_user_data_13;
0239     uint32_t compute_user_data_14;
0240     uint32_t compute_user_data_15;
0241     uint32_t cp_compute_csinvoc_count_lo;
0242     uint32_t cp_compute_csinvoc_count_hi;
0243     uint32_t reserved35;
0244     uint32_t reserved36;
0245     uint32_t reserved37;
0246     uint32_t cp_mqd_query_time_lo;
0247     uint32_t cp_mqd_query_time_hi;
0248     uint32_t cp_mqd_connect_start_time_lo;
0249     uint32_t cp_mqd_connect_start_time_hi;
0250     uint32_t cp_mqd_connect_end_time_lo;
0251     uint32_t cp_mqd_connect_end_time_hi;
0252     uint32_t cp_mqd_connect_end_wf_count;
0253     uint32_t cp_mqd_connect_end_pq_rptr;
0254     uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
0255     uint32_t cp_mqd_connect_end_ib_rptr;
0256     uint32_t reserved38;
0257     uint32_t reserved39;
0258     uint32_t cp_mqd_save_start_time_lo;
0259     uint32_t cp_mqd_save_start_time_hi;
0260     uint32_t cp_mqd_save_end_time_lo;
0261     uint32_t cp_mqd_save_end_time_hi;
0262     uint32_t cp_mqd_restore_start_time_lo;
0263     uint32_t cp_mqd_restore_start_time_hi;
0264     uint32_t cp_mqd_restore_end_time_lo;
0265     uint32_t cp_mqd_restore_end_time_hi;
0266     uint32_t disable_queue;
0267     uint32_t reserved41;
0268     uint32_t gds_cs_ctxsw_cnt0;
0269     uint32_t gds_cs_ctxsw_cnt1;
0270     uint32_t gds_cs_ctxsw_cnt2;
0271     uint32_t gds_cs_ctxsw_cnt3;
0272     uint32_t reserved42;
0273     uint32_t reserved43;
0274     uint32_t cp_pq_exe_status_lo;
0275     uint32_t cp_pq_exe_status_hi;
0276     uint32_t cp_packet_id_lo;
0277     uint32_t cp_packet_id_hi;
0278     uint32_t cp_packet_exe_status_lo;
0279     uint32_t cp_packet_exe_status_hi;
0280     uint32_t gds_save_base_addr_lo;
0281     uint32_t gds_save_base_addr_hi;
0282     uint32_t gds_save_mask_lo;
0283     uint32_t gds_save_mask_hi;
0284     uint32_t ctx_save_base_addr_lo;
0285     uint32_t ctx_save_base_addr_hi;
0286     uint32_t dynamic_cu_mask_addr_lo;
0287     uint32_t dynamic_cu_mask_addr_hi;
0288     uint32_t cp_mqd_base_addr_lo;
0289     uint32_t cp_mqd_base_addr_hi;
0290     uint32_t cp_hqd_active;
0291     uint32_t cp_hqd_vmid;
0292     uint32_t cp_hqd_persistent_state;
0293     uint32_t cp_hqd_pipe_priority;
0294     uint32_t cp_hqd_queue_priority;
0295     uint32_t cp_hqd_quantum;
0296     uint32_t cp_hqd_pq_base_lo;
0297     uint32_t cp_hqd_pq_base_hi;
0298     uint32_t cp_hqd_pq_rptr;
0299     uint32_t cp_hqd_pq_rptr_report_addr_lo;
0300     uint32_t cp_hqd_pq_rptr_report_addr_hi;
0301     uint32_t cp_hqd_pq_wptr_poll_addr_lo;
0302     uint32_t cp_hqd_pq_wptr_poll_addr_hi;
0303     uint32_t cp_hqd_pq_doorbell_control;
0304     uint32_t cp_hqd_pq_wptr;
0305     uint32_t cp_hqd_pq_control;
0306     uint32_t cp_hqd_ib_base_addr_lo;
0307     uint32_t cp_hqd_ib_base_addr_hi;
0308     uint32_t cp_hqd_ib_rptr;
0309     uint32_t cp_hqd_ib_control;
0310     uint32_t cp_hqd_iq_timer;
0311     uint32_t cp_hqd_iq_rptr;
0312     uint32_t cp_hqd_dequeue_request;
0313     uint32_t cp_hqd_dma_offload;
0314     uint32_t cp_hqd_sema_cmd;
0315     uint32_t cp_hqd_msg_type;
0316     uint32_t cp_hqd_atomic0_preop_lo;
0317     uint32_t cp_hqd_atomic0_preop_hi;
0318     uint32_t cp_hqd_atomic1_preop_lo;
0319     uint32_t cp_hqd_atomic1_preop_hi;
0320     uint32_t cp_hqd_hq_status0;
0321     uint32_t cp_hqd_hq_control0;
0322     uint32_t cp_mqd_control;
0323     uint32_t cp_hqd_hq_status1;
0324     uint32_t cp_hqd_hq_control1;
0325     uint32_t cp_hqd_eop_base_addr_lo;
0326     uint32_t cp_hqd_eop_base_addr_hi;
0327     uint32_t cp_hqd_eop_control;
0328     uint32_t cp_hqd_eop_rptr;
0329     uint32_t cp_hqd_eop_wptr;
0330     uint32_t cp_hqd_eop_done_events;
0331     uint32_t cp_hqd_ctx_save_base_addr_lo;
0332     uint32_t cp_hqd_ctx_save_base_addr_hi;
0333     uint32_t cp_hqd_ctx_save_control;
0334     uint32_t cp_hqd_cntl_stack_offset;
0335     uint32_t cp_hqd_cntl_stack_size;
0336     uint32_t cp_hqd_wg_state_offset;
0337     uint32_t cp_hqd_ctx_save_size;
0338     uint32_t cp_hqd_gds_resource_state;
0339     uint32_t cp_hqd_error;
0340     uint32_t cp_hqd_eop_wptr_mem;
0341     uint32_t cp_hqd_eop_dones;
0342     uint32_t reserved46;
0343     uint32_t reserved47;
0344     uint32_t reserved48;
0345     uint32_t reserved49;
0346     uint32_t reserved50;
0347     uint32_t reserved51;
0348     uint32_t reserved52;
0349     uint32_t reserved53;
0350     uint32_t reserved54;
0351     uint32_t reserved55;
0352     uint32_t iqtimer_pkt_header;
0353     uint32_t iqtimer_pkt_dw0;
0354     uint32_t iqtimer_pkt_dw1;
0355     uint32_t iqtimer_pkt_dw2;
0356     uint32_t iqtimer_pkt_dw3;
0357     uint32_t iqtimer_pkt_dw4;
0358     uint32_t iqtimer_pkt_dw5;
0359     uint32_t iqtimer_pkt_dw6;
0360     uint32_t iqtimer_pkt_dw7;
0361     uint32_t iqtimer_pkt_dw8;
0362     uint32_t iqtimer_pkt_dw9;
0363     uint32_t iqtimer_pkt_dw10;
0364     uint32_t iqtimer_pkt_dw11;
0365     uint32_t iqtimer_pkt_dw12;
0366     uint32_t iqtimer_pkt_dw13;
0367     uint32_t iqtimer_pkt_dw14;
0368     uint32_t iqtimer_pkt_dw15;
0369     uint32_t iqtimer_pkt_dw16;
0370     uint32_t iqtimer_pkt_dw17;
0371     uint32_t iqtimer_pkt_dw18;
0372     uint32_t iqtimer_pkt_dw19;
0373     uint32_t iqtimer_pkt_dw20;
0374     uint32_t iqtimer_pkt_dw21;
0375     uint32_t iqtimer_pkt_dw22;
0376     uint32_t iqtimer_pkt_dw23;
0377     uint32_t iqtimer_pkt_dw24;
0378     uint32_t iqtimer_pkt_dw25;
0379     uint32_t iqtimer_pkt_dw26;
0380     uint32_t iqtimer_pkt_dw27;
0381     uint32_t iqtimer_pkt_dw28;
0382     uint32_t iqtimer_pkt_dw29;
0383     uint32_t iqtimer_pkt_dw30;
0384     uint32_t iqtimer_pkt_dw31;
0385     uint32_t reserved56;
0386     uint32_t reserved57;
0387     uint32_t reserved58;
0388     uint32_t set_resources_header;
0389     uint32_t set_resources_dw1;
0390     uint32_t set_resources_dw2;
0391     uint32_t set_resources_dw3;
0392     uint32_t set_resources_dw4;
0393     uint32_t set_resources_dw5;
0394     uint32_t set_resources_dw6;
0395     uint32_t set_resources_dw7;
0396     uint32_t reserved59;
0397     uint32_t reserved60;
0398     uint32_t reserved61;
0399     uint32_t reserved62;
0400     uint32_t queue_doorbell_id0;
0401     uint32_t queue_doorbell_id1;
0402     uint32_t queue_doorbell_id2;
0403     uint32_t queue_doorbell_id3;
0404     uint32_t queue_doorbell_id4;
0405     uint32_t queue_doorbell_id5;
0406     uint32_t queue_doorbell_id6;
0407     uint32_t queue_doorbell_id7;
0408     uint32_t queue_doorbell_id8;
0409     uint32_t queue_doorbell_id9;
0410     uint32_t queue_doorbell_id10;
0411     uint32_t queue_doorbell_id11;
0412     uint32_t queue_doorbell_id12;
0413     uint32_t queue_doorbell_id13;
0414     uint32_t queue_doorbell_id14;
0415     uint32_t queue_doorbell_id15;
0416     uint32_t reserved_t[256];
0417 };
0418
0419 struct vi_mqd_allocation {
0420     struct vi_mqd mqd;
0421     uint32_t wptr_poll_mem;
0422     uint32_t rptr_report_mem;
0423     uint32_t dynamic_cu_mask;
0424     uint32_t dynamic_rb_mask;
0425 };
0426
0427 struct vi_ce_ib_state {
0428     uint32_t    ce_ib_completion_status;
0429     uint32_t    ce_constegnine_count;
0430     uint32_t    ce_ibOffset_ib1;
0431     uint32_t    ce_ibOffset_ib2;
0432 }; /* Total of 4 DWORD */
0433
0434 struct vi_de_ib_state {
0435     uint32_t    ib_completion_status;
0436     uint32_t    de_constEngine_count;
0437     uint32_t    ib_offset_ib1;
0438     uint32_t    ib_offset_ib2;
0439     uint32_t    preamble_begin_ib1;
0440     uint32_t    preamble_begin_ib2;
0441     uint32_t    preamble_end_ib1;
0442     uint32_t    preamble_end_ib2;
0443     uint32_t    draw_indirect_baseLo;
0444     uint32_t    draw_indirect_baseHi;
0445     uint32_t    disp_indirect_baseLo;
0446     uint32_t    disp_indirect_baseHi;
0447     uint32_t    gds_backup_addrlo;
0448     uint32_t    gds_backup_addrhi;
0449     uint32_t    index_base_addrlo;
0450     uint32_t    index_base_addrhi;
0451     uint32_t    sample_cntl;
0452 }; /* Total of 17 DWORD */
0453
0454 struct vi_ce_ib_state_chained_ib {
0455     /* section of non chained ib part */
0456     uint32_t    ce_ib_completion_status;
0457     uint32_t    ce_constegnine_count;
0458     uint32_t    ce_ibOffset_ib1;
0459     uint32_t    ce_ibOffset_ib2;
0460
0461     /* section of chained ib */
0462     uint32_t    ce_chainib_addrlo_ib1;
0463     uint32_t    ce_chainib_addrlo_ib2;
0464     uint32_t    ce_chainib_addrhi_ib1;
0465     uint32_t    ce_chainib_addrhi_ib2;
0466     uint32_t    ce_chainib_size_ib1;
0467     uint32_t    ce_chainib_size_ib2;
0468 }; /* total 10 DWORD */
0469
0470 struct vi_de_ib_state_chained_ib {
0471     /* section of non chained ib part */
0472     uint32_t    ib_completion_status;
0473     uint32_t    de_constEngine_count;
0474     uint32_t    ib_offset_ib1;
0475     uint32_t    ib_offset_ib2;
0476
0477     /* section of chained ib */
0478     uint32_t    chain_ib_addrlo_ib1;
0479     uint32_t    chain_ib_addrlo_ib2;
0480     uint32_t    chain_ib_addrhi_ib1;
0481     uint32_t    chain_ib_addrhi_ib2;
0482     uint32_t    chain_ib_size_ib1;
0483     uint32_t    chain_ib_size_ib2;
0484
0485     /* section of non chained ib part */
0486     uint32_t    preamble_begin_ib1;
0487     uint32_t    preamble_begin_ib2;
0488     uint32_t    preamble_end_ib1;
0489     uint32_t    preamble_end_ib2;
0490
0491     /* section of chained ib */
0492     uint32_t    chain_ib_pream_addrlo_ib1;
0493     uint32_t    chain_ib_pream_addrlo_ib2;
0494     uint32_t    chain_ib_pream_addrhi_ib1;
0495     uint32_t    chain_ib_pream_addrhi_ib2;
0496
0497     /* section of non chained ib part */
0498     uint32_t    draw_indirect_baseLo;
0499     uint32_t    draw_indirect_baseHi;
0500     uint32_t    disp_indirect_baseLo;
0501     uint32_t    disp_indirect_baseHi;
0502     uint32_t    gds_backup_addrlo;
0503     uint32_t    gds_backup_addrhi;
0504     uint32_t    index_base_addrlo;
0505     uint32_t    index_base_addrhi;
0506     uint32_t    sample_cntl;
0507 }; /* Total of 27 DWORD */
0508
0509 struct vi_gfx_meta_data {
0510     /* 4 DWORD, address must be 4KB aligned */
0511     struct vi_ce_ib_state        ce_payload;
0512     uint32_t                     reserved1[60];
0513     /* 17 DWORD, address must be 64B aligned */
0514     struct vi_de_ib_state        de_payload;
0515     /* PFP IB base address which get pre-empted */
0516     uint32_t                     DeIbBaseAddrLo;
0517     uint32_t                     DeIbBaseAddrHi;
0518     uint32_t                     reserved2[941];
0519 }; /* Total of 4K Bytes */
0520
0521 struct vi_gfx_meta_data_chained_ib {
0522     /* 10 DWORD, address must be 4KB aligned */
0523     struct vi_ce_ib_state_chained_ib       ce_payload;
0524     uint32_t                               reserved1[54];
0525     /* 27 DWORD, address must be 64B aligned */
0526     struct vi_de_ib_state_chained_ib       de_payload;
0527     /* PFP IB base address which get pre-empted */
0528     uint32_t                               DeIbBaseAddrLo;
0529     uint32_t                               DeIbBaseAddrHi;
0530     uint32_t                               reserved2[931];
0531 }; /* Total of 4K Bytes */
0532
0533 #endif /* VI_STRUCTS_H_ */