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0001 /*
0002  * Copyright (C) 2018  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _vega20_ip_offset_HEADER
0022 #define _vega20_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                       6
0025 #define MAX_SEGMENT                                        6
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 };
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0, 0 } } } };
0045 static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } },
0046                                         { { 0, 0, 0, 0, 0, 0 } },
0047                                         { { 0, 0, 0, 0, 0, 0 } },
0048                                         { { 0, 0, 0, 0, 0, 0 } },
0049                                         { { 0, 0, 0, 0, 0, 0 } },
0050                                         { { 0, 0, 0, 0, 0, 0 } } } };
0051 static const struct IP_BASE DCE_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0, 0 } },
0053                                         { { 0, 0, 0, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0, 0 } } } };
0057 static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } } } };
0063 static const struct IP_BASE FUSE_BASE            ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0, 0 } } } };
0069 static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0, 0 } } } };
0075 static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } } } };
0087 static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } } } };
0093 static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0, 0 } } } };
0099 static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } } } };
0105 static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } },
0109                                         { { 0, 0, 0, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0, 0 } } } };
0111 static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0, 0 } } } };
0117 static const struct IP_BASE SDMA1_BASE            ={ { { { 0x00001860, 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } } } };
0129 static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } } } };
0135 static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0, 0 } } } };
0141 static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
0142                                         { { 0, 0x00009000, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0, 0 } },
0144                                         { { 0, 0, 0, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0, 0 } } } };
0147 /* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/
0148 static const struct IP_BASE VCE_BASE            ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0, 0 } },
0151                                         { { 0, 0, 0, 0, 0, 0 } },
0152                                         { { 0, 0, 0, 0, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0, 0 } } } };
0154 static const struct IP_BASE XDMA_BASE            ={ { { { 0x00003400, 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0, 0 } },
0158                                         { { 0, 0, 0, 0, 0, 0 } },
0159                                         { { 0, 0, 0, 0, 0, 0 } } } };
0160 static const struct IP_BASE RSMU_BASE            ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0, 0 } },
0165                                         { { 0, 0, 0, 0, 0, 0 } } } };
0166 
0167 
0168 #define ATHUB_BASE__INST0_SEG0                     0x00000C20
0169 #define ATHUB_BASE__INST0_SEG1                     0
0170 #define ATHUB_BASE__INST0_SEG2                     0
0171 #define ATHUB_BASE__INST0_SEG3                     0
0172 #define ATHUB_BASE__INST0_SEG4                     0
0173 #define ATHUB_BASE__INST0_SEG5                     0
0174 
0175 #define ATHUB_BASE__INST1_SEG0                     0
0176 #define ATHUB_BASE__INST1_SEG1                     0
0177 #define ATHUB_BASE__INST1_SEG2                     0
0178 #define ATHUB_BASE__INST1_SEG3                     0
0179 #define ATHUB_BASE__INST1_SEG4                     0
0180 #define ATHUB_BASE__INST1_SEG5                     0
0181 
0182 #define ATHUB_BASE__INST2_SEG0                     0
0183 #define ATHUB_BASE__INST2_SEG1                     0
0184 #define ATHUB_BASE__INST2_SEG2                     0
0185 #define ATHUB_BASE__INST2_SEG3                     0
0186 #define ATHUB_BASE__INST2_SEG4                     0
0187 #define ATHUB_BASE__INST2_SEG5                     0
0188 
0189 #define ATHUB_BASE__INST3_SEG0                     0
0190 #define ATHUB_BASE__INST3_SEG1                     0
0191 #define ATHUB_BASE__INST3_SEG2                     0
0192 #define ATHUB_BASE__INST3_SEG3                     0
0193 #define ATHUB_BASE__INST3_SEG4                     0
0194 #define ATHUB_BASE__INST3_SEG5                     0
0195 
0196 #define ATHUB_BASE__INST4_SEG0                     0
0197 #define ATHUB_BASE__INST4_SEG1                     0
0198 #define ATHUB_BASE__INST4_SEG2                     0
0199 #define ATHUB_BASE__INST4_SEG3                     0
0200 #define ATHUB_BASE__INST4_SEG4                     0
0201 #define ATHUB_BASE__INST4_SEG5                     0
0202 
0203 #define ATHUB_BASE__INST5_SEG0                     0
0204 #define ATHUB_BASE__INST5_SEG1                     0
0205 #define ATHUB_BASE__INST5_SEG2                     0
0206 #define ATHUB_BASE__INST5_SEG3                     0
0207 #define ATHUB_BASE__INST5_SEG4                     0
0208 #define ATHUB_BASE__INST5_SEG5                     0
0209 
0210 #define CLK_BASE__INST0_SEG0                       0x00016C00
0211 #define CLK_BASE__INST0_SEG1                       0x00016E00
0212 #define CLK_BASE__INST0_SEG2                       0x00017000
0213 #define CLK_BASE__INST0_SEG3                       0x00017200
0214 #define CLK_BASE__INST0_SEG4                       0x0001B000
0215 #define CLK_BASE__INST0_SEG5                       0x0001B200
0216 
0217 #define CLK_BASE__INST1_SEG0                       0
0218 #define CLK_BASE__INST1_SEG1                       0
0219 #define CLK_BASE__INST1_SEG2                       0
0220 #define CLK_BASE__INST1_SEG3                       0
0221 #define CLK_BASE__INST1_SEG4                       0
0222 #define CLK_BASE__INST1_SEG5                       0
0223 
0224 #define CLK_BASE__INST2_SEG0                       0
0225 #define CLK_BASE__INST2_SEG1                       0
0226 #define CLK_BASE__INST2_SEG2                       0
0227 #define CLK_BASE__INST2_SEG3                       0
0228 #define CLK_BASE__INST2_SEG4                       0
0229 #define CLK_BASE__INST2_SEG5                       0
0230 
0231 #define CLK_BASE__INST3_SEG0                       0
0232 #define CLK_BASE__INST3_SEG1                       0
0233 #define CLK_BASE__INST3_SEG2                       0
0234 #define CLK_BASE__INST3_SEG3                       0
0235 #define CLK_BASE__INST3_SEG4                       0
0236 #define CLK_BASE__INST3_SEG5                       0
0237 
0238 #define CLK_BASE__INST4_SEG0                       0
0239 #define CLK_BASE__INST4_SEG1                       0
0240 #define CLK_BASE__INST4_SEG2                       0
0241 #define CLK_BASE__INST4_SEG3                       0
0242 #define CLK_BASE__INST4_SEG4                       0
0243 #define CLK_BASE__INST4_SEG5                       0
0244 
0245 #define CLK_BASE__INST5_SEG0                       0
0246 #define CLK_BASE__INST5_SEG1                       0
0247 #define CLK_BASE__INST5_SEG2                       0
0248 #define CLK_BASE__INST5_SEG3                       0
0249 #define CLK_BASE__INST5_SEG4                       0
0250 #define CLK_BASE__INST5_SEG5                       0
0251 
0252 #define DCE_BASE__INST0_SEG0                       0x00000012
0253 #define DCE_BASE__INST0_SEG1                       0x000000C0
0254 #define DCE_BASE__INST0_SEG2                       0x000034C0
0255 #define DCE_BASE__INST0_SEG3                       0
0256 #define DCE_BASE__INST0_SEG4                       0
0257 #define DCE_BASE__INST0_SEG5                       0
0258 
0259 #define DCE_BASE__INST1_SEG0                       0
0260 #define DCE_BASE__INST1_SEG1                       0
0261 #define DCE_BASE__INST1_SEG2                       0
0262 #define DCE_BASE__INST1_SEG3                       0
0263 #define DCE_BASE__INST1_SEG4                       0
0264 #define DCE_BASE__INST1_SEG5                       0
0265 
0266 #define DCE_BASE__INST2_SEG0                       0
0267 #define DCE_BASE__INST2_SEG1                       0
0268 #define DCE_BASE__INST2_SEG2                       0
0269 #define DCE_BASE__INST2_SEG3                       0
0270 #define DCE_BASE__INST2_SEG4                       0
0271 #define DCE_BASE__INST2_SEG5                       0
0272 
0273 #define DCE_BASE__INST3_SEG0                       0
0274 #define DCE_BASE__INST3_SEG1                       0
0275 #define DCE_BASE__INST3_SEG2                       0
0276 #define DCE_BASE__INST3_SEG3                       0
0277 #define DCE_BASE__INST3_SEG4                       0
0278 #define DCE_BASE__INST3_SEG5                       0
0279 
0280 #define DCE_BASE__INST4_SEG0                       0
0281 #define DCE_BASE__INST4_SEG1                       0
0282 #define DCE_BASE__INST4_SEG2                       0
0283 #define DCE_BASE__INST4_SEG3                       0
0284 #define DCE_BASE__INST4_SEG4                       0
0285 #define DCE_BASE__INST4_SEG5                       0
0286 
0287 #define DCE_BASE__INST5_SEG0                       0
0288 #define DCE_BASE__INST5_SEG1                       0
0289 #define DCE_BASE__INST5_SEG2                       0
0290 #define DCE_BASE__INST5_SEG3                       0
0291 #define DCE_BASE__INST5_SEG4                       0
0292 #define DCE_BASE__INST5_SEG5                       0
0293 
0294 #define DF_BASE__INST0_SEG0                        0x00007000
0295 #define DF_BASE__INST0_SEG1                        0
0296 #define DF_BASE__INST0_SEG2                        0
0297 #define DF_BASE__INST0_SEG3                        0
0298 #define DF_BASE__INST0_SEG4                        0
0299 #define DF_BASE__INST0_SEG5                        0
0300 
0301 #define DF_BASE__INST1_SEG0                        0
0302 #define DF_BASE__INST1_SEG1                        0
0303 #define DF_BASE__INST1_SEG2                        0
0304 #define DF_BASE__INST1_SEG3                        0
0305 #define DF_BASE__INST1_SEG4                        0
0306 #define DF_BASE__INST1_SEG5                        0
0307 
0308 #define DF_BASE__INST2_SEG0                        0
0309 #define DF_BASE__INST2_SEG1                        0
0310 #define DF_BASE__INST2_SEG2                        0
0311 #define DF_BASE__INST2_SEG3                        0
0312 #define DF_BASE__INST2_SEG4                        0
0313 #define DF_BASE__INST2_SEG5                        0
0314 
0315 #define DF_BASE__INST3_SEG0                        0
0316 #define DF_BASE__INST3_SEG1                        0
0317 #define DF_BASE__INST3_SEG2                        0
0318 #define DF_BASE__INST3_SEG3                        0
0319 #define DF_BASE__INST3_SEG4                        0
0320 #define DF_BASE__INST3_SEG5                        0
0321 
0322 #define DF_BASE__INST4_SEG0                        0
0323 #define DF_BASE__INST4_SEG1                        0
0324 #define DF_BASE__INST4_SEG2                        0
0325 #define DF_BASE__INST4_SEG3                        0
0326 #define DF_BASE__INST4_SEG4                        0
0327 #define DF_BASE__INST4_SEG5                        0
0328 
0329 #define DF_BASE__INST5_SEG0                        0
0330 #define DF_BASE__INST5_SEG1                        0
0331 #define DF_BASE__INST5_SEG2                        0
0332 #define DF_BASE__INST5_SEG3                        0
0333 #define DF_BASE__INST5_SEG4                        0
0334 #define DF_BASE__INST5_SEG5                        0
0335 
0336 #define FUSE_BASE__INST0_SEG0                      0x00017400
0337 #define FUSE_BASE__INST0_SEG1                      0
0338 #define FUSE_BASE__INST0_SEG2                      0
0339 #define FUSE_BASE__INST0_SEG3                      0
0340 #define FUSE_BASE__INST0_SEG4                      0
0341 #define FUSE_BASE__INST0_SEG5                      0
0342 
0343 #define FUSE_BASE__INST1_SEG0                      0
0344 #define FUSE_BASE__INST1_SEG1                      0
0345 #define FUSE_BASE__INST1_SEG2                      0
0346 #define FUSE_BASE__INST1_SEG3                      0
0347 #define FUSE_BASE__INST1_SEG4                      0
0348 #define FUSE_BASE__INST1_SEG5                      0
0349 
0350 #define FUSE_BASE__INST2_SEG0                      0
0351 #define FUSE_BASE__INST2_SEG1                      0
0352 #define FUSE_BASE__INST2_SEG2                      0
0353 #define FUSE_BASE__INST2_SEG3                      0
0354 #define FUSE_BASE__INST2_SEG4                      0
0355 #define FUSE_BASE__INST2_SEG5                      0
0356 
0357 #define FUSE_BASE__INST3_SEG0                      0
0358 #define FUSE_BASE__INST3_SEG1                      0
0359 #define FUSE_BASE__INST3_SEG2                      0
0360 #define FUSE_BASE__INST3_SEG3                      0
0361 #define FUSE_BASE__INST3_SEG4                      0
0362 #define FUSE_BASE__INST3_SEG5                      0
0363 
0364 #define FUSE_BASE__INST4_SEG0                      0
0365 #define FUSE_BASE__INST4_SEG1                      0
0366 #define FUSE_BASE__INST4_SEG2                      0
0367 #define FUSE_BASE__INST4_SEG3                      0
0368 #define FUSE_BASE__INST4_SEG4                      0
0369 #define FUSE_BASE__INST4_SEG5                      0
0370 
0371 #define FUSE_BASE__INST5_SEG0                      0
0372 #define FUSE_BASE__INST5_SEG1                      0
0373 #define FUSE_BASE__INST5_SEG2                      0
0374 #define FUSE_BASE__INST5_SEG3                      0
0375 #define FUSE_BASE__INST5_SEG4                      0
0376 #define FUSE_BASE__INST5_SEG5                      0
0377 
0378 #define GC_BASE__INST0_SEG0                        0x00002000
0379 #define GC_BASE__INST0_SEG1                        0x0000A000
0380 #define GC_BASE__INST0_SEG2                        0
0381 #define GC_BASE__INST0_SEG3                        0
0382 #define GC_BASE__INST0_SEG4                        0
0383 #define GC_BASE__INST0_SEG5                        0
0384 
0385 #define GC_BASE__INST1_SEG0                        0
0386 #define GC_BASE__INST1_SEG1                        0
0387 #define GC_BASE__INST1_SEG2                        0
0388 #define GC_BASE__INST1_SEG3                        0
0389 #define GC_BASE__INST1_SEG4                        0
0390 #define GC_BASE__INST1_SEG5                        0
0391 
0392 #define GC_BASE__INST2_SEG0                        0
0393 #define GC_BASE__INST2_SEG1                        0
0394 #define GC_BASE__INST2_SEG2                        0
0395 #define GC_BASE__INST2_SEG3                        0
0396 #define GC_BASE__INST2_SEG4                        0
0397 #define GC_BASE__INST2_SEG5                        0
0398 
0399 #define GC_BASE__INST3_SEG0                        0
0400 #define GC_BASE__INST3_SEG1                        0
0401 #define GC_BASE__INST3_SEG2                        0
0402 #define GC_BASE__INST3_SEG3                        0
0403 #define GC_BASE__INST3_SEG4                        0
0404 #define GC_BASE__INST3_SEG5                        0
0405 
0406 #define GC_BASE__INST4_SEG0                        0
0407 #define GC_BASE__INST4_SEG1                        0
0408 #define GC_BASE__INST4_SEG2                        0
0409 #define GC_BASE__INST4_SEG3                        0
0410 #define GC_BASE__INST4_SEG4                        0
0411 #define GC_BASE__INST4_SEG5                        0
0412 
0413 #define GC_BASE__INST5_SEG0                        0
0414 #define GC_BASE__INST5_SEG1                        0
0415 #define GC_BASE__INST5_SEG2                        0
0416 #define GC_BASE__INST5_SEG3                        0
0417 #define GC_BASE__INST5_SEG4                        0
0418 #define GC_BASE__INST5_SEG5                        0
0419 
0420 #define HDP_BASE__INST0_SEG0                       0x00000F20
0421 #define HDP_BASE__INST0_SEG1                       0
0422 #define HDP_BASE__INST0_SEG2                       0
0423 #define HDP_BASE__INST0_SEG3                       0
0424 #define HDP_BASE__INST0_SEG4                       0
0425 #define HDP_BASE__INST0_SEG5                       0
0426 
0427 #define HDP_BASE__INST1_SEG0                       0
0428 #define HDP_BASE__INST1_SEG1                       0
0429 #define HDP_BASE__INST1_SEG2                       0
0430 #define HDP_BASE__INST1_SEG3                       0
0431 #define HDP_BASE__INST1_SEG4                       0
0432 #define HDP_BASE__INST1_SEG5                       0
0433 
0434 #define HDP_BASE__INST2_SEG0                       0
0435 #define HDP_BASE__INST2_SEG1                       0
0436 #define HDP_BASE__INST2_SEG2                       0
0437 #define HDP_BASE__INST2_SEG3                       0
0438 #define HDP_BASE__INST2_SEG4                       0
0439 #define HDP_BASE__INST2_SEG5                       0
0440 
0441 #define HDP_BASE__INST3_SEG0                       0
0442 #define HDP_BASE__INST3_SEG1                       0
0443 #define HDP_BASE__INST3_SEG2                       0
0444 #define HDP_BASE__INST3_SEG3                       0
0445 #define HDP_BASE__INST3_SEG4                       0
0446 #define HDP_BASE__INST3_SEG5                       0
0447 
0448 #define HDP_BASE__INST4_SEG0                       0
0449 #define HDP_BASE__INST4_SEG1                       0
0450 #define HDP_BASE__INST4_SEG2                       0
0451 #define HDP_BASE__INST4_SEG3                       0
0452 #define HDP_BASE__INST4_SEG4                       0
0453 #define HDP_BASE__INST4_SEG5                       0
0454 
0455 #define HDP_BASE__INST5_SEG0                       0
0456 #define HDP_BASE__INST5_SEG1                       0
0457 #define HDP_BASE__INST5_SEG2                       0
0458 #define HDP_BASE__INST5_SEG3                       0
0459 #define HDP_BASE__INST5_SEG4                       0
0460 #define HDP_BASE__INST5_SEG5                       0
0461 
0462 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0463 #define MMHUB_BASE__INST0_SEG1                     0
0464 #define MMHUB_BASE__INST0_SEG2                     0
0465 #define MMHUB_BASE__INST0_SEG3                     0
0466 #define MMHUB_BASE__INST0_SEG4                     0
0467 #define MMHUB_BASE__INST0_SEG5                     0
0468 
0469 #define MMHUB_BASE__INST1_SEG0                     0
0470 #define MMHUB_BASE__INST1_SEG1                     0
0471 #define MMHUB_BASE__INST1_SEG2                     0
0472 #define MMHUB_BASE__INST1_SEG3                     0
0473 #define MMHUB_BASE__INST1_SEG4                     0
0474 #define MMHUB_BASE__INST1_SEG5                     0
0475 
0476 #define MMHUB_BASE__INST2_SEG0                     0
0477 #define MMHUB_BASE__INST2_SEG1                     0
0478 #define MMHUB_BASE__INST2_SEG2                     0
0479 #define MMHUB_BASE__INST2_SEG3                     0
0480 #define MMHUB_BASE__INST2_SEG4                     0
0481 #define MMHUB_BASE__INST2_SEG5                     0
0482 
0483 #define MMHUB_BASE__INST3_SEG0                     0
0484 #define MMHUB_BASE__INST3_SEG1                     0
0485 #define MMHUB_BASE__INST3_SEG2                     0
0486 #define MMHUB_BASE__INST3_SEG3                     0
0487 #define MMHUB_BASE__INST3_SEG4                     0
0488 #define MMHUB_BASE__INST3_SEG5                     0
0489 
0490 #define MMHUB_BASE__INST4_SEG0                     0
0491 #define MMHUB_BASE__INST4_SEG1                     0
0492 #define MMHUB_BASE__INST4_SEG2                     0
0493 #define MMHUB_BASE__INST4_SEG3                     0
0494 #define MMHUB_BASE__INST4_SEG4                     0
0495 #define MMHUB_BASE__INST4_SEG5                     0
0496 
0497 #define MMHUB_BASE__INST5_SEG0                     0
0498 #define MMHUB_BASE__INST5_SEG1                     0
0499 #define MMHUB_BASE__INST5_SEG2                     0
0500 #define MMHUB_BASE__INST5_SEG3                     0
0501 #define MMHUB_BASE__INST5_SEG4                     0
0502 #define MMHUB_BASE__INST5_SEG5                     0
0503 
0504 #define MP0_BASE__INST0_SEG0                       0x00016000
0505 #define MP0_BASE__INST0_SEG1                       0
0506 #define MP0_BASE__INST0_SEG2                       0
0507 #define MP0_BASE__INST0_SEG3                       0
0508 #define MP0_BASE__INST0_SEG4                       0
0509 #define MP0_BASE__INST0_SEG5                       0
0510 
0511 #define MP0_BASE__INST1_SEG0                       0
0512 #define MP0_BASE__INST1_SEG1                       0
0513 #define MP0_BASE__INST1_SEG2                       0
0514 #define MP0_BASE__INST1_SEG3                       0
0515 #define MP0_BASE__INST1_SEG4                       0
0516 #define MP0_BASE__INST1_SEG5                       0
0517 
0518 #define MP0_BASE__INST2_SEG0                       0
0519 #define MP0_BASE__INST2_SEG1                       0
0520 #define MP0_BASE__INST2_SEG2                       0
0521 #define MP0_BASE__INST2_SEG3                       0
0522 #define MP0_BASE__INST2_SEG4                       0
0523 #define MP0_BASE__INST2_SEG5                       0
0524 
0525 #define MP0_BASE__INST3_SEG0                       0
0526 #define MP0_BASE__INST3_SEG1                       0
0527 #define MP0_BASE__INST3_SEG2                       0
0528 #define MP0_BASE__INST3_SEG3                       0
0529 #define MP0_BASE__INST3_SEG4                       0
0530 #define MP0_BASE__INST3_SEG5                       0
0531 
0532 #define MP0_BASE__INST4_SEG0                       0
0533 #define MP0_BASE__INST4_SEG1                       0
0534 #define MP0_BASE__INST4_SEG2                       0
0535 #define MP0_BASE__INST4_SEG3                       0
0536 #define MP0_BASE__INST4_SEG4                       0
0537 #define MP0_BASE__INST4_SEG5                       0
0538 
0539 #define MP0_BASE__INST5_SEG0                       0
0540 #define MP0_BASE__INST5_SEG1                       0
0541 #define MP0_BASE__INST5_SEG2                       0
0542 #define MP0_BASE__INST5_SEG3                       0
0543 #define MP0_BASE__INST5_SEG4                       0
0544 #define MP0_BASE__INST5_SEG5                       0
0545 
0546 #define MP1_BASE__INST0_SEG0                       0x00016000
0547 #define MP1_BASE__INST0_SEG1                       0
0548 #define MP1_BASE__INST0_SEG2                       0
0549 #define MP1_BASE__INST0_SEG3                       0
0550 #define MP1_BASE__INST0_SEG4                       0
0551 #define MP1_BASE__INST0_SEG5                       0
0552 
0553 #define MP1_BASE__INST1_SEG0                       0
0554 #define MP1_BASE__INST1_SEG1                       0
0555 #define MP1_BASE__INST1_SEG2                       0
0556 #define MP1_BASE__INST1_SEG3                       0
0557 #define MP1_BASE__INST1_SEG4                       0
0558 #define MP1_BASE__INST1_SEG5                       0
0559 
0560 #define MP1_BASE__INST2_SEG0                       0
0561 #define MP1_BASE__INST2_SEG1                       0
0562 #define MP1_BASE__INST2_SEG2                       0
0563 #define MP1_BASE__INST2_SEG3                       0
0564 #define MP1_BASE__INST2_SEG4                       0
0565 #define MP1_BASE__INST2_SEG5                       0
0566 
0567 #define MP1_BASE__INST3_SEG0                       0
0568 #define MP1_BASE__INST3_SEG1                       0
0569 #define MP1_BASE__INST3_SEG2                       0
0570 #define MP1_BASE__INST3_SEG3                       0
0571 #define MP1_BASE__INST3_SEG4                       0
0572 #define MP1_BASE__INST3_SEG5                       0
0573 
0574 #define MP1_BASE__INST4_SEG0                       0
0575 #define MP1_BASE__INST4_SEG1                       0
0576 #define MP1_BASE__INST4_SEG2                       0
0577 #define MP1_BASE__INST4_SEG3                       0
0578 #define MP1_BASE__INST4_SEG4                       0
0579 #define MP1_BASE__INST4_SEG5                       0
0580 
0581 #define MP1_BASE__INST5_SEG0                       0
0582 #define MP1_BASE__INST5_SEG1                       0
0583 #define MP1_BASE__INST5_SEG2                       0
0584 #define MP1_BASE__INST5_SEG3                       0
0585 #define MP1_BASE__INST5_SEG4                       0
0586 #define MP1_BASE__INST5_SEG5                       0
0587 
0588 #define NBIO_BASE__INST0_SEG0                      0x00000000
0589 #define NBIO_BASE__INST0_SEG1                      0x00000014
0590 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0591 #define NBIO_BASE__INST0_SEG3                      0x00010400
0592 #define NBIO_BASE__INST0_SEG4                      0
0593 #define NBIO_BASE__INST0_SEG5                      0
0594 
0595 #define NBIO_BASE__INST1_SEG0                      0
0596 #define NBIO_BASE__INST1_SEG1                      0
0597 #define NBIO_BASE__INST1_SEG2                      0
0598 #define NBIO_BASE__INST1_SEG3                      0
0599 #define NBIO_BASE__INST1_SEG4                      0
0600 #define NBIO_BASE__INST1_SEG5                      0
0601 
0602 #define NBIO_BASE__INST2_SEG0                      0
0603 #define NBIO_BASE__INST2_SEG1                      0
0604 #define NBIO_BASE__INST2_SEG2                      0
0605 #define NBIO_BASE__INST2_SEG3                      0
0606 #define NBIO_BASE__INST2_SEG4                      0
0607 #define NBIO_BASE__INST2_SEG5                      0
0608 
0609 #define NBIO_BASE__INST3_SEG0                      0
0610 #define NBIO_BASE__INST3_SEG1                      0
0611 #define NBIO_BASE__INST3_SEG2                      0
0612 #define NBIO_BASE__INST3_SEG3                      0
0613 #define NBIO_BASE__INST3_SEG4                      0
0614 #define NBIO_BASE__INST3_SEG5                      0
0615 
0616 #define NBIO_BASE__INST4_SEG0                      0
0617 #define NBIO_BASE__INST4_SEG1                      0
0618 #define NBIO_BASE__INST4_SEG2                      0
0619 #define NBIO_BASE__INST4_SEG3                      0
0620 #define NBIO_BASE__INST4_SEG4                      0
0621 #define NBIO_BASE__INST4_SEG5                      0
0622 
0623 #define NBIO_BASE__INST5_SEG0                      0
0624 #define NBIO_BASE__INST5_SEG1                      0
0625 #define NBIO_BASE__INST5_SEG2                      0
0626 #define NBIO_BASE__INST5_SEG3                      0
0627 #define NBIO_BASE__INST5_SEG4                      0
0628 #define NBIO_BASE__INST5_SEG5                      0
0629 
0630 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0631 #define OSSSYS_BASE__INST0_SEG1                    0
0632 #define OSSSYS_BASE__INST0_SEG2                    0
0633 #define OSSSYS_BASE__INST0_SEG3                    0
0634 #define OSSSYS_BASE__INST0_SEG4                    0
0635 #define OSSSYS_BASE__INST0_SEG5                    0
0636 
0637 #define OSSSYS_BASE__INST1_SEG0                    0
0638 #define OSSSYS_BASE__INST1_SEG1                    0
0639 #define OSSSYS_BASE__INST1_SEG2                    0
0640 #define OSSSYS_BASE__INST1_SEG3                    0
0641 #define OSSSYS_BASE__INST1_SEG4                    0
0642 #define OSSSYS_BASE__INST1_SEG5                    0
0643 
0644 #define OSSSYS_BASE__INST2_SEG0                    0
0645 #define OSSSYS_BASE__INST2_SEG1                    0
0646 #define OSSSYS_BASE__INST2_SEG2                    0
0647 #define OSSSYS_BASE__INST2_SEG3                    0
0648 #define OSSSYS_BASE__INST2_SEG4                    0
0649 #define OSSSYS_BASE__INST2_SEG5                    0
0650 
0651 #define OSSSYS_BASE__INST3_SEG0                    0
0652 #define OSSSYS_BASE__INST3_SEG1                    0
0653 #define OSSSYS_BASE__INST3_SEG2                    0
0654 #define OSSSYS_BASE__INST3_SEG3                    0
0655 #define OSSSYS_BASE__INST3_SEG4                    0
0656 #define OSSSYS_BASE__INST3_SEG5                    0
0657 
0658 #define OSSSYS_BASE__INST4_SEG0                    0
0659 #define OSSSYS_BASE__INST4_SEG1                    0
0660 #define OSSSYS_BASE__INST4_SEG2                    0
0661 #define OSSSYS_BASE__INST4_SEG3                    0
0662 #define OSSSYS_BASE__INST4_SEG4                    0
0663 #define OSSSYS_BASE__INST4_SEG5                    0
0664 
0665 #define OSSSYS_BASE__INST5_SEG0                    0
0666 #define OSSSYS_BASE__INST5_SEG1                    0
0667 #define OSSSYS_BASE__INST5_SEG2                    0
0668 #define OSSSYS_BASE__INST5_SEG3                    0
0669 #define OSSSYS_BASE__INST5_SEG4                    0
0670 #define OSSSYS_BASE__INST5_SEG5                    0
0671 
0672 #define SDMA0_BASE__INST0_SEG0                     0x00001260
0673 #define SDMA0_BASE__INST0_SEG1                     0
0674 #define SDMA0_BASE__INST0_SEG2                     0
0675 #define SDMA0_BASE__INST0_SEG3                     0
0676 #define SDMA0_BASE__INST0_SEG4                     0
0677 #define SDMA0_BASE__INST0_SEG5                     0
0678 
0679 #define SDMA0_BASE__INST1_SEG0                     0
0680 #define SDMA0_BASE__INST1_SEG1                     0
0681 #define SDMA0_BASE__INST1_SEG2                     0
0682 #define SDMA0_BASE__INST1_SEG3                     0
0683 #define SDMA0_BASE__INST1_SEG4                     0
0684 #define SDMA0_BASE__INST1_SEG5                     0
0685 
0686 #define SDMA0_BASE__INST2_SEG0                     0
0687 #define SDMA0_BASE__INST2_SEG1                     0
0688 #define SDMA0_BASE__INST2_SEG2                     0
0689 #define SDMA0_BASE__INST2_SEG3                     0
0690 #define SDMA0_BASE__INST2_SEG4                     0
0691 #define SDMA0_BASE__INST2_SEG5                     0
0692 
0693 #define SDMA0_BASE__INST3_SEG0                     0
0694 #define SDMA0_BASE__INST3_SEG1                     0
0695 #define SDMA0_BASE__INST3_SEG2                     0
0696 #define SDMA0_BASE__INST3_SEG3                     0
0697 #define SDMA0_BASE__INST3_SEG4                     0
0698 #define SDMA0_BASE__INST3_SEG5                     0
0699 
0700 #define SDMA0_BASE__INST4_SEG0                     0
0701 #define SDMA0_BASE__INST4_SEG1                     0
0702 #define SDMA0_BASE__INST4_SEG2                     0
0703 #define SDMA0_BASE__INST4_SEG3                     0
0704 #define SDMA0_BASE__INST4_SEG4                     0
0705 #define SDMA0_BASE__INST4_SEG5                     0
0706 
0707 #define SDMA0_BASE__INST5_SEG0                     0
0708 #define SDMA0_BASE__INST5_SEG1                     0
0709 #define SDMA0_BASE__INST5_SEG2                     0
0710 #define SDMA0_BASE__INST5_SEG3                     0
0711 #define SDMA0_BASE__INST5_SEG4                     0
0712 #define SDMA0_BASE__INST5_SEG5                     0
0713 
0714 #define SDMA1_BASE__INST0_SEG0                     0x00001860
0715 #define SDMA1_BASE__INST0_SEG1                     0
0716 #define SDMA1_BASE__INST0_SEG2                     0
0717 #define SDMA1_BASE__INST0_SEG3                     0
0718 #define SDMA1_BASE__INST0_SEG4                     0
0719 #define SDMA1_BASE__INST0_SEG5                     0
0720 
0721 #define SDMA1_BASE__INST1_SEG0                     0
0722 #define SDMA1_BASE__INST1_SEG1                     0
0723 #define SDMA1_BASE__INST1_SEG2                     0
0724 #define SDMA1_BASE__INST1_SEG3                     0
0725 #define SDMA1_BASE__INST1_SEG4                     0
0726 #define SDMA1_BASE__INST1_SEG5                     0
0727 
0728 #define SDMA1_BASE__INST2_SEG0                     0
0729 #define SDMA1_BASE__INST2_SEG1                     0
0730 #define SDMA1_BASE__INST2_SEG2                     0
0731 #define SDMA1_BASE__INST2_SEG3                     0
0732 #define SDMA1_BASE__INST2_SEG4                     0
0733 #define SDMA1_BASE__INST2_SEG5                     0
0734 
0735 #define SDMA1_BASE__INST3_SEG0                     0
0736 #define SDMA1_BASE__INST3_SEG1                     0
0737 #define SDMA1_BASE__INST3_SEG2                     0
0738 #define SDMA1_BASE__INST3_SEG3                     0
0739 #define SDMA1_BASE__INST3_SEG4                     0
0740 #define SDMA1_BASE__INST3_SEG5                     0
0741 
0742 #define SDMA1_BASE__INST4_SEG0                     0
0743 #define SDMA1_BASE__INST4_SEG1                     0
0744 #define SDMA1_BASE__INST4_SEG2                     0
0745 #define SDMA1_BASE__INST4_SEG3                     0
0746 #define SDMA1_BASE__INST4_SEG4                     0
0747 #define SDMA1_BASE__INST4_SEG5                     0
0748 
0749 #define SDMA1_BASE__INST5_SEG0                     0
0750 #define SDMA1_BASE__INST5_SEG1                     0
0751 #define SDMA1_BASE__INST5_SEG2                     0
0752 #define SDMA1_BASE__INST5_SEG3                     0
0753 #define SDMA1_BASE__INST5_SEG4                     0
0754 #define SDMA1_BASE__INST5_SEG5                     0
0755 
0756 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0757 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0758 #define SMUIO_BASE__INST0_SEG2                     0
0759 #define SMUIO_BASE__INST0_SEG3                     0
0760 #define SMUIO_BASE__INST0_SEG4                     0
0761 #define SMUIO_BASE__INST0_SEG5                     0
0762 
0763 #define SMUIO_BASE__INST1_SEG0                     0
0764 #define SMUIO_BASE__INST1_SEG1                     0
0765 #define SMUIO_BASE__INST1_SEG2                     0
0766 #define SMUIO_BASE__INST1_SEG3                     0
0767 #define SMUIO_BASE__INST1_SEG4                     0
0768 #define SMUIO_BASE__INST1_SEG5                     0
0769 
0770 #define SMUIO_BASE__INST2_SEG0                     0
0771 #define SMUIO_BASE__INST2_SEG1                     0
0772 #define SMUIO_BASE__INST2_SEG2                     0
0773 #define SMUIO_BASE__INST2_SEG3                     0
0774 #define SMUIO_BASE__INST2_SEG4                     0
0775 #define SMUIO_BASE__INST2_SEG5                     0
0776 
0777 #define SMUIO_BASE__INST3_SEG0                     0
0778 #define SMUIO_BASE__INST3_SEG1                     0
0779 #define SMUIO_BASE__INST3_SEG2                     0
0780 #define SMUIO_BASE__INST3_SEG3                     0
0781 #define SMUIO_BASE__INST3_SEG4                     0
0782 #define SMUIO_BASE__INST3_SEG5                     0
0783 
0784 #define SMUIO_BASE__INST4_SEG0                     0
0785 #define SMUIO_BASE__INST4_SEG1                     0
0786 #define SMUIO_BASE__INST4_SEG2                     0
0787 #define SMUIO_BASE__INST4_SEG3                     0
0788 #define SMUIO_BASE__INST4_SEG4                     0
0789 #define SMUIO_BASE__INST4_SEG5                     0
0790 
0791 #define SMUIO_BASE__INST5_SEG0                     0
0792 #define SMUIO_BASE__INST5_SEG1                     0
0793 #define SMUIO_BASE__INST5_SEG2                     0
0794 #define SMUIO_BASE__INST5_SEG3                     0
0795 #define SMUIO_BASE__INST5_SEG4                     0
0796 #define SMUIO_BASE__INST5_SEG5                     0
0797 
0798 #define THM_BASE__INST0_SEG0                       0x00016600
0799 #define THM_BASE__INST0_SEG1                       0
0800 #define THM_BASE__INST0_SEG2                       0
0801 #define THM_BASE__INST0_SEG3                       0
0802 #define THM_BASE__INST0_SEG4                       0
0803 #define THM_BASE__INST0_SEG5                       0
0804 
0805 #define THM_BASE__INST1_SEG0                       0
0806 #define THM_BASE__INST1_SEG1                       0
0807 #define THM_BASE__INST1_SEG2                       0
0808 #define THM_BASE__INST1_SEG3                       0
0809 #define THM_BASE__INST1_SEG4                       0
0810 #define THM_BASE__INST1_SEG5                       0
0811 
0812 #define THM_BASE__INST2_SEG0                       0
0813 #define THM_BASE__INST2_SEG1                       0
0814 #define THM_BASE__INST2_SEG2                       0
0815 #define THM_BASE__INST2_SEG3                       0
0816 #define THM_BASE__INST2_SEG4                       0
0817 #define THM_BASE__INST2_SEG5                       0
0818 
0819 #define THM_BASE__INST3_SEG0                       0
0820 #define THM_BASE__INST3_SEG1                       0
0821 #define THM_BASE__INST3_SEG2                       0
0822 #define THM_BASE__INST3_SEG3                       0
0823 #define THM_BASE__INST3_SEG4                       0
0824 #define THM_BASE__INST3_SEG5                       0
0825 
0826 #define THM_BASE__INST4_SEG0                       0
0827 #define THM_BASE__INST4_SEG1                       0
0828 #define THM_BASE__INST4_SEG2                       0
0829 #define THM_BASE__INST4_SEG3                       0
0830 #define THM_BASE__INST4_SEG4                       0
0831 #define THM_BASE__INST4_SEG5                       0
0832 
0833 #define THM_BASE__INST5_SEG0                       0
0834 #define THM_BASE__INST5_SEG1                       0
0835 #define THM_BASE__INST5_SEG2                       0
0836 #define THM_BASE__INST5_SEG3                       0
0837 #define THM_BASE__INST5_SEG4                       0
0838 #define THM_BASE__INST5_SEG5                       0
0839 
0840 #define UMC_BASE__INST0_SEG0                       0x00014000
0841 #define UMC_BASE__INST0_SEG1                       0
0842 #define UMC_BASE__INST0_SEG2                       0
0843 #define UMC_BASE__INST0_SEG3                       0
0844 #define UMC_BASE__INST0_SEG4                       0
0845 #define UMC_BASE__INST0_SEG5                       0
0846 
0847 #define UMC_BASE__INST1_SEG0                       0
0848 #define UMC_BASE__INST1_SEG1                       0
0849 #define UMC_BASE__INST1_SEG2                       0
0850 #define UMC_BASE__INST1_SEG3                       0
0851 #define UMC_BASE__INST1_SEG4                       0
0852 #define UMC_BASE__INST1_SEG5                       0
0853 
0854 #define UMC_BASE__INST2_SEG0                       0
0855 #define UMC_BASE__INST2_SEG1                       0
0856 #define UMC_BASE__INST2_SEG2                       0
0857 #define UMC_BASE__INST2_SEG3                       0
0858 #define UMC_BASE__INST2_SEG4                       0
0859 #define UMC_BASE__INST2_SEG5                       0
0860 
0861 #define UMC_BASE__INST3_SEG0                       0
0862 #define UMC_BASE__INST3_SEG1                       0
0863 #define UMC_BASE__INST3_SEG2                       0
0864 #define UMC_BASE__INST3_SEG3                       0
0865 #define UMC_BASE__INST3_SEG4                       0
0866 #define UMC_BASE__INST3_SEG5                       0
0867 
0868 #define UMC_BASE__INST4_SEG0                       0
0869 #define UMC_BASE__INST4_SEG1                       0
0870 #define UMC_BASE__INST4_SEG2                       0
0871 #define UMC_BASE__INST4_SEG3                       0
0872 #define UMC_BASE__INST4_SEG4                       0
0873 #define UMC_BASE__INST4_SEG5                       0
0874 
0875 #define UMC_BASE__INST5_SEG0                       0
0876 #define UMC_BASE__INST5_SEG1                       0
0877 #define UMC_BASE__INST5_SEG2                       0
0878 #define UMC_BASE__INST5_SEG3                       0
0879 #define UMC_BASE__INST5_SEG4                       0
0880 #define UMC_BASE__INST5_SEG5                       0
0881 
0882 #define UVD_BASE__INST0_SEG0                       0x00007800
0883 #define UVD_BASE__INST0_SEG1                       0x00007E00
0884 #define UVD_BASE__INST0_SEG2                       0
0885 #define UVD_BASE__INST0_SEG3                       0
0886 #define UVD_BASE__INST0_SEG4                       0
0887 #define UVD_BASE__INST0_SEG5                       0
0888 
0889 #define UVD_BASE__INST1_SEG0                       0
0890 #define UVD_BASE__INST1_SEG1                       0x00009000
0891 #define UVD_BASE__INST1_SEG2                       0
0892 #define UVD_BASE__INST1_SEG3                       0
0893 #define UVD_BASE__INST1_SEG4                       0
0894 #define UVD_BASE__INST1_SEG5                       0
0895 
0896 #define UVD_BASE__INST2_SEG0                       0
0897 #define UVD_BASE__INST2_SEG1                       0
0898 #define UVD_BASE__INST2_SEG2                       0
0899 #define UVD_BASE__INST2_SEG3                       0
0900 #define UVD_BASE__INST2_SEG4                       0
0901 #define UVD_BASE__INST2_SEG5                       0
0902 
0903 #define UVD_BASE__INST3_SEG0                       0
0904 #define UVD_BASE__INST3_SEG1                       0
0905 #define UVD_BASE__INST3_SEG2                       0
0906 #define UVD_BASE__INST3_SEG3                       0
0907 #define UVD_BASE__INST3_SEG4                       0
0908 #define UVD_BASE__INST3_SEG5                       0
0909 
0910 #define UVD_BASE__INST4_SEG0                       0
0911 #define UVD_BASE__INST4_SEG1                       0
0912 #define UVD_BASE__INST4_SEG2                       0
0913 #define UVD_BASE__INST4_SEG3                       0
0914 #define UVD_BASE__INST4_SEG4                       0
0915 #define UVD_BASE__INST4_SEG5                       0
0916 
0917 #define UVD_BASE__INST5_SEG0                       0
0918 #define UVD_BASE__INST5_SEG1                       0
0919 #define UVD_BASE__INST5_SEG2                       0
0920 #define UVD_BASE__INST5_SEG3                       0
0921 #define UVD_BASE__INST5_SEG4                       0
0922 #define UVD_BASE__INST5_SEG5                       0
0923 
0924 #define VCE_BASE__INST0_SEG0                       0x00008800
0925 #define VCE_BASE__INST0_SEG1                       0
0926 #define VCE_BASE__INST0_SEG2                       0
0927 #define VCE_BASE__INST0_SEG3                       0
0928 #define VCE_BASE__INST0_SEG4                       0
0929 #define VCE_BASE__INST0_SEG5                       0
0930 
0931 #define VCE_BASE__INST1_SEG0                       0
0932 #define VCE_BASE__INST1_SEG1                       0
0933 #define VCE_BASE__INST1_SEG2                       0
0934 #define VCE_BASE__INST1_SEG3                       0
0935 #define VCE_BASE__INST1_SEG4                       0
0936 #define VCE_BASE__INST1_SEG5                       0
0937 
0938 #define VCE_BASE__INST2_SEG0                       0
0939 #define VCE_BASE__INST2_SEG1                       0
0940 #define VCE_BASE__INST2_SEG2                       0
0941 #define VCE_BASE__INST2_SEG3                       0
0942 #define VCE_BASE__INST2_SEG4                       0
0943 #define VCE_BASE__INST2_SEG5                       0
0944 
0945 #define VCE_BASE__INST3_SEG0                       0
0946 #define VCE_BASE__INST3_SEG1                       0
0947 #define VCE_BASE__INST3_SEG2                       0
0948 #define VCE_BASE__INST3_SEG3                       0
0949 #define VCE_BASE__INST3_SEG4                       0
0950 #define VCE_BASE__INST3_SEG5                       0
0951 
0952 #define VCE_BASE__INST4_SEG0                       0
0953 #define VCE_BASE__INST4_SEG1                       0
0954 #define VCE_BASE__INST4_SEG2                       0
0955 #define VCE_BASE__INST4_SEG3                       0
0956 #define VCE_BASE__INST4_SEG4                       0
0957 #define VCE_BASE__INST4_SEG5                       0
0958 
0959 #define VCE_BASE__INST5_SEG0                       0
0960 #define VCE_BASE__INST5_SEG1                       0
0961 #define VCE_BASE__INST5_SEG2                       0
0962 #define VCE_BASE__INST5_SEG3                       0
0963 #define VCE_BASE__INST5_SEG4                       0
0964 #define VCE_BASE__INST5_SEG5                       0
0965 
0966 #define XDMA_BASE__INST0_SEG0                      0x00003400
0967 #define XDMA_BASE__INST0_SEG1                      0
0968 #define XDMA_BASE__INST0_SEG2                      0
0969 #define XDMA_BASE__INST0_SEG3                      0
0970 #define XDMA_BASE__INST0_SEG4                      0
0971 #define XDMA_BASE__INST0_SEG5                      0
0972 
0973 #define XDMA_BASE__INST1_SEG0                      0
0974 #define XDMA_BASE__INST1_SEG1                      0
0975 #define XDMA_BASE__INST1_SEG2                      0
0976 #define XDMA_BASE__INST1_SEG3                      0
0977 #define XDMA_BASE__INST1_SEG4                      0
0978 #define XDMA_BASE__INST1_SEG5                      0
0979 
0980 #define XDMA_BASE__INST2_SEG0                      0
0981 #define XDMA_BASE__INST2_SEG1                      0
0982 #define XDMA_BASE__INST2_SEG2                      0
0983 #define XDMA_BASE__INST2_SEG3                      0
0984 #define XDMA_BASE__INST2_SEG4                      0
0985 #define XDMA_BASE__INST2_SEG5                      0
0986 
0987 #define XDMA_BASE__INST3_SEG0                      0
0988 #define XDMA_BASE__INST3_SEG1                      0
0989 #define XDMA_BASE__INST3_SEG2                      0
0990 #define XDMA_BASE__INST3_SEG3                      0
0991 #define XDMA_BASE__INST3_SEG4                      0
0992 #define XDMA_BASE__INST3_SEG5                      0
0993 
0994 #define XDMA_BASE__INST4_SEG0                      0
0995 #define XDMA_BASE__INST4_SEG1                      0
0996 #define XDMA_BASE__INST4_SEG2                      0
0997 #define XDMA_BASE__INST4_SEG3                      0
0998 #define XDMA_BASE__INST4_SEG4                      0
0999 #define XDMA_BASE__INST4_SEG5                      0
1000 
1001 #define XDMA_BASE__INST5_SEG0                      0
1002 #define XDMA_BASE__INST5_SEG1                      0
1003 #define XDMA_BASE__INST5_SEG2                      0
1004 #define XDMA_BASE__INST5_SEG3                      0
1005 #define XDMA_BASE__INST5_SEG4                      0
1006 #define XDMA_BASE__INST5_SEG5                      0
1007 
1008 #define RSMU_BASE__INST0_SEG0                      0x00012000
1009 #define RSMU_BASE__INST0_SEG1                      0
1010 #define RSMU_BASE__INST0_SEG2                      0
1011 #define RSMU_BASE__INST0_SEG3                      0
1012 #define RSMU_BASE__INST0_SEG4                      0
1013 #define RSMU_BASE__INST0_SEG5                      0
1014 
1015 #define RSMU_BASE__INST1_SEG0                      0
1016 #define RSMU_BASE__INST1_SEG1                      0
1017 #define RSMU_BASE__INST1_SEG2                      0
1018 #define RSMU_BASE__INST1_SEG3                      0
1019 #define RSMU_BASE__INST1_SEG4                      0
1020 #define RSMU_BASE__INST1_SEG5                      0
1021 
1022 #define RSMU_BASE__INST2_SEG0                      0
1023 #define RSMU_BASE__INST2_SEG1                      0
1024 #define RSMU_BASE__INST2_SEG2                      0
1025 #define RSMU_BASE__INST2_SEG3                      0
1026 #define RSMU_BASE__INST2_SEG4                      0
1027 #define RSMU_BASE__INST2_SEG5                      0
1028 
1029 #define RSMU_BASE__INST3_SEG0                      0
1030 #define RSMU_BASE__INST3_SEG1                      0
1031 #define RSMU_BASE__INST3_SEG2                      0
1032 #define RSMU_BASE__INST3_SEG3                      0
1033 #define RSMU_BASE__INST3_SEG4                      0
1034 #define RSMU_BASE__INST3_SEG5                      0
1035 
1036 #define RSMU_BASE__INST4_SEG0                      0
1037 #define RSMU_BASE__INST4_SEG1                      0
1038 #define RSMU_BASE__INST4_SEG2                      0
1039 #define RSMU_BASE__INST4_SEG3                      0
1040 #define RSMU_BASE__INST4_SEG4                      0
1041 #define RSMU_BASE__INST4_SEG5                      0
1042 
1043 #define RSMU_BASE__INST5_SEG0                      0
1044 #define RSMU_BASE__INST5_SEG1                      0
1045 #define RSMU_BASE__INST5_SEG2                      0
1046 #define RSMU_BASE__INST5_SEG3                      0
1047 #define RSMU_BASE__INST5_SEG4                      0
1048 #define RSMU_BASE__INST5_SEG5                      0
1049 
1050 #endif
1051
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