amd/include/vega10_ip_offset.h

0001 /*
0002  * Copyright (C) 2018  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _vega10_ip_offset_HEADER
0022 #define _vega10_ip_offset_HEADER
0023
0024 #define MAX_INSTANCE                                       5
0025 #define MAX_SEGMENT                                        5
0026
0027 struct IP_BASE_INSTANCE
0028 {
0029     unsigned int segment[MAX_SEGMENT];
0030 };
0031
0032 struct IP_BASE
0033 {
0034     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0035 };
0036
0037
0038 static const struct IP_BASE __maybe_unused NBIF_BASE    = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
0039                                         { { 0, 0, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0 } } } };
0043 static const struct IP_BASE __maybe_unused NBIO_BASE    = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
0044                                         { { 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0 } },
0046                                         { { 0, 0, 0, 0, 0 } },
0047                                         { { 0, 0, 0, 0, 0 } } } };
0048 static const struct IP_BASE __maybe_unused DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
0049                                         { { 0, 0, 0, 0, 0 } },
0050                                         { { 0, 0, 0, 0, 0 } },
0051                                         { { 0, 0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0 } } } };
0053 static const struct IP_BASE __maybe_unused DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0 } } } };
0058 static const struct IP_BASE __maybe_unused MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0 } } } };
0063 static const struct IP_BASE __maybe_unused MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0 } } } };
0068 static const struct IP_BASE __maybe_unused MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0 } } } };
0073 static const struct IP_BASE __maybe_unused DF_BASE  = { { { { 0x00007000, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0 } },
0075                                         { { 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0 } } } };
0078 static const struct IP_BASE __maybe_unused UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0 } },
0081                                         { { 0, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0 } } } };  //note: GLN does not use the first segment
0083 static const struct IP_BASE __maybe_unused VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0 } } } };  //note: GLN does not use the first segment
0088 static const struct IP_BASE __maybe_unused DBGU_BASE    = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0093 static const struct IP_BASE __maybe_unused DBGU_NBIO_BASE   = { { { { 0x000001C0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0098 static const struct IP_BASE __maybe_unused DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0103 static const struct IP_BASE __maybe_unused DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0108 static const struct IP_BASE __maybe_unused DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
0109                                         { { 0, 0, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
0113 static const struct IP_BASE __maybe_unused ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0 } },
0117                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0118 static const struct IP_BASE __maybe_unused SYSTEMHUB_BASE   = { { { { 0x00000EA0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0 } } } }; // not exist
0123 static const struct IP_BASE __maybe_unused L2IMU_BASE   = { { { { 0x00007DC0, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0 } } } };
0128 static const struct IP_BASE __maybe_unused IOHC_BASE    = { { { { 0x00010000, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0 } } } };
0133 static const struct IP_BASE __maybe_unused ATHUB_BASE   = { { { { 0x00000C20, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0 } } } };
0138 static const struct IP_BASE __maybe_unused VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0 } } } };
0143 static const struct IP_BASE __maybe_unused GC_BASE  = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
0144                                         { { 0, 0, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0 } } } };
0148 static const struct IP_BASE __maybe_unused MMHUB_BASE   = { { { { 0x0001A000, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0 } },
0151                                         { { 0, 0, 0, 0, 0 } },
0152                                         { { 0, 0, 0, 0, 0 } } } };
0153 static const struct IP_BASE __maybe_unused RSMU_BASE    = { { { { 0x00012000, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0 } } } };
0158 static const struct IP_BASE __maybe_unused HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
0159                                         { { 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0 } } } };
0163 static const struct IP_BASE __maybe_unused OSSSYS_BASE   = { { { { 0x000010A0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0 } },
0165                                         { { 0, 0, 0, 0, 0 } },
0166                                         { { 0, 0, 0, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0 } } } };
0168 static const struct IP_BASE __maybe_unused SDMA0_BASE   = { { { { 0x00001260, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0 } },
0172                                         { { 0, 0, 0, 0, 0 } } } };
0173 static const struct IP_BASE __maybe_unused SDMA1_BASE   = { { { { 0x00001460, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0 } },
0175                                         { { 0, 0, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0 } } } };
0178 static const struct IP_BASE __maybe_unused XDMA_BASE    = { { { { 0x00003400, 0, 0, 0, 0 } },
0179                                         { { 0, 0, 0, 0, 0 } },
0180                                         { { 0, 0, 0, 0, 0 } },
0181                                         { { 0, 0, 0, 0, 0 } },
0182                                         { { 0, 0, 0, 0, 0 } } } };
0183 static const struct IP_BASE __maybe_unused UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
0184                                         { { 0, 0, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0 } },
0186                                         { { 0, 0, 0, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0 } } } };
0188 static const struct IP_BASE __maybe_unused THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0 } },
0191                                         { { 0, 0, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0 } } } };
0193 static const struct IP_BASE __maybe_unused SMUIO_BASE   = { { { { 0x00016800, 0, 0, 0, 0 } },
0194                                         { { 0, 0, 0, 0, 0 } },
0195                                         { { 0, 0, 0, 0, 0 } },
0196                                         { { 0, 0, 0, 0, 0 } },
0197                                         { { 0, 0, 0, 0, 0 } } } };
0198 static const struct IP_BASE __maybe_unused PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
0199                                         { { 0, 0, 0, 0, 0 } },
0200                                         { { 0, 0, 0, 0, 0 } },
0201                                         { { 0, 0, 0, 0, 0 } },
0202                                         { { 0, 0, 0, 0, 0 } } } };
0203 static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
0204                                         { { 0x00016E00, 0, 0, 0, 0 } },
0205                                         { { 0x00017000, 0, 0, 0, 0 } },
0206                                         { { 0x00017200, 0, 0, 0, 0 } },
0207                                         { { 0x00017E00, 0, 0, 0, 0 } } } };
0208 static const struct IP_BASE __maybe_unused FUSE_BASE    = { { { { 0x00017400, 0, 0, 0, 0 } },
0209                                         { { 0, 0, 0, 0, 0 } },
0210                                         { { 0, 0, 0, 0, 0 } },
0211                                         { { 0, 0, 0, 0, 0 } },
0212                                         { { 0, 0, 0, 0, 0 } } } };
0213
0214
0215 #define NBIF_BASE__INST0_SEG0                     0x00000000
0216 #define NBIF_BASE__INST0_SEG1                     0x00000014
0217 #define NBIF_BASE__INST0_SEG2                     0x00000D20
0218 #define NBIF_BASE__INST0_SEG3                     0x00010400
0219 #define NBIF_BASE__INST0_SEG4                     0
0220
0221 #define NBIF_BASE__INST1_SEG0                     0
0222 #define NBIF_BASE__INST1_SEG1                     0
0223 #define NBIF_BASE__INST1_SEG2                     0
0224 #define NBIF_BASE__INST1_SEG3                     0
0225 #define NBIF_BASE__INST1_SEG4                     0
0226
0227 #define NBIF_BASE__INST2_SEG0                     0
0228 #define NBIF_BASE__INST2_SEG1                     0
0229 #define NBIF_BASE__INST2_SEG2                     0
0230 #define NBIF_BASE__INST2_SEG3                     0
0231 #define NBIF_BASE__INST2_SEG4                     0
0232
0233 #define NBIF_BASE__INST3_SEG0                     0
0234 #define NBIF_BASE__INST3_SEG1                     0
0235 #define NBIF_BASE__INST3_SEG2                     0
0236 #define NBIF_BASE__INST3_SEG3                     0
0237 #define NBIF_BASE__INST3_SEG4                     0
0238
0239 #define NBIF_BASE__INST4_SEG0                     0
0240 #define NBIF_BASE__INST4_SEG1                     0
0241 #define NBIF_BASE__INST4_SEG2                     0
0242 #define NBIF_BASE__INST4_SEG3                     0
0243 #define NBIF_BASE__INST4_SEG4                     0
0244
0245 #define NBIO_BASE__INST0_SEG0                     0x00000000
0246 #define NBIO_BASE__INST0_SEG1                     0x00000014
0247 #define NBIO_BASE__INST0_SEG2                     0x00000D20
0248 #define NBIO_BASE__INST0_SEG3                     0x00010400
0249 #define NBIO_BASE__INST0_SEG4                     0
0250
0251 #define NBIO_BASE__INST1_SEG0                     0
0252 #define NBIO_BASE__INST1_SEG1                     0
0253 #define NBIO_BASE__INST1_SEG2                     0
0254 #define NBIO_BASE__INST1_SEG3                     0
0255 #define NBIO_BASE__INST1_SEG4                     0
0256
0257 #define NBIO_BASE__INST2_SEG0                     0
0258 #define NBIO_BASE__INST2_SEG1                     0
0259 #define NBIO_BASE__INST2_SEG2                     0
0260 #define NBIO_BASE__INST2_SEG3                     0
0261 #define NBIO_BASE__INST2_SEG4                     0
0262
0263 #define NBIO_BASE__INST3_SEG0                     0
0264 #define NBIO_BASE__INST3_SEG1                     0
0265 #define NBIO_BASE__INST3_SEG2                     0
0266 #define NBIO_BASE__INST3_SEG3                     0
0267 #define NBIO_BASE__INST3_SEG4                     0
0268
0269 #define NBIO_BASE__INST4_SEG0                     0
0270 #define NBIO_BASE__INST4_SEG1                     0
0271 #define NBIO_BASE__INST4_SEG2                     0
0272 #define NBIO_BASE__INST4_SEG3                     0
0273 #define NBIO_BASE__INST4_SEG4                     0
0274
0275 #define DCE_BASE__INST0_SEG0                      0x00000012
0276 #define DCE_BASE__INST0_SEG1                      0x000000C0
0277 #define DCE_BASE__INST0_SEG2                      0x000034C0
0278 #define DCE_BASE__INST0_SEG3                      0
0279 #define DCE_BASE__INST0_SEG4                      0
0280
0281 #define DCE_BASE__INST1_SEG0                      0
0282 #define DCE_BASE__INST1_SEG1                      0
0283 #define DCE_BASE__INST1_SEG2                      0
0284 #define DCE_BASE__INST1_SEG3                      0
0285 #define DCE_BASE__INST1_SEG4                      0
0286
0287 #define DCE_BASE__INST2_SEG0                      0
0288 #define DCE_BASE__INST2_SEG1                      0
0289 #define DCE_BASE__INST2_SEG2                      0
0290 #define DCE_BASE__INST2_SEG3                      0
0291 #define DCE_BASE__INST2_SEG4                      0
0292
0293 #define DCE_BASE__INST3_SEG0                      0
0294 #define DCE_BASE__INST3_SEG1                      0
0295 #define DCE_BASE__INST3_SEG2                      0
0296 #define DCE_BASE__INST3_SEG3                      0
0297 #define DCE_BASE__INST3_SEG4                      0
0298
0299 #define DCE_BASE__INST4_SEG0                      0
0300 #define DCE_BASE__INST4_SEG1                      0
0301 #define DCE_BASE__INST4_SEG2                      0
0302 #define DCE_BASE__INST4_SEG3                      0
0303 #define DCE_BASE__INST4_SEG4                      0
0304
0305 #define DCN_BASE__INST0_SEG0                      0x00000012
0306 #define DCN_BASE__INST0_SEG1                      0x000000C0
0307 #define DCN_BASE__INST0_SEG2                      0x000034C0
0308 #define DCN_BASE__INST0_SEG3                      0
0309 #define DCN_BASE__INST0_SEG4                      0
0310
0311 #define DCN_BASE__INST1_SEG0                      0
0312 #define DCN_BASE__INST1_SEG1                      0
0313 #define DCN_BASE__INST1_SEG2                      0
0314 #define DCN_BASE__INST1_SEG3                      0
0315 #define DCN_BASE__INST1_SEG4                      0
0316
0317 #define DCN_BASE__INST2_SEG0                      0
0318 #define DCN_BASE__INST2_SEG1                      0
0319 #define DCN_BASE__INST2_SEG2                      0
0320 #define DCN_BASE__INST2_SEG3                      0
0321 #define DCN_BASE__INST2_SEG4                      0
0322
0323 #define DCN_BASE__INST3_SEG0                      0
0324 #define DCN_BASE__INST3_SEG1                      0
0325 #define DCN_BASE__INST3_SEG2                      0
0326 #define DCN_BASE__INST3_SEG3                      0
0327 #define DCN_BASE__INST3_SEG4                      0
0328
0329 #define DCN_BASE__INST4_SEG0                      0
0330 #define DCN_BASE__INST4_SEG1                      0
0331 #define DCN_BASE__INST4_SEG2                      0
0332 #define DCN_BASE__INST4_SEG3                      0
0333 #define DCN_BASE__INST4_SEG4                      0
0334
0335 #define MP0_BASE__INST0_SEG0                      0x00016000
0336 #define MP0_BASE__INST0_SEG1                      0
0337 #define MP0_BASE__INST0_SEG2                      0
0338 #define MP0_BASE__INST0_SEG3                      0
0339 #define MP0_BASE__INST0_SEG4                      0
0340
0341 #define MP0_BASE__INST1_SEG0                      0
0342 #define MP0_BASE__INST1_SEG1                      0
0343 #define MP0_BASE__INST1_SEG2                      0
0344 #define MP0_BASE__INST1_SEG3                      0
0345 #define MP0_BASE__INST1_SEG4                      0
0346
0347 #define MP0_BASE__INST2_SEG0                      0
0348 #define MP0_BASE__INST2_SEG1                      0
0349 #define MP0_BASE__INST2_SEG2                      0
0350 #define MP0_BASE__INST2_SEG3                      0
0351 #define MP0_BASE__INST2_SEG4                      0
0352
0353 #define MP0_BASE__INST3_SEG0                      0
0354 #define MP0_BASE__INST3_SEG1                      0
0355 #define MP0_BASE__INST3_SEG2                      0
0356 #define MP0_BASE__INST3_SEG3                      0
0357 #define MP0_BASE__INST3_SEG4                      0
0358
0359 #define MP0_BASE__INST4_SEG0                      0
0360 #define MP0_BASE__INST4_SEG1                      0
0361 #define MP0_BASE__INST4_SEG2                      0
0362 #define MP0_BASE__INST4_SEG3                      0
0363 #define MP0_BASE__INST4_SEG4                      0
0364
0365 #define MP1_BASE__INST0_SEG0                      0x00016200
0366 #define MP1_BASE__INST0_SEG1                      0
0367 #define MP1_BASE__INST0_SEG2                      0
0368 #define MP1_BASE__INST0_SEG3                      0
0369 #define MP1_BASE__INST0_SEG4                      0
0370
0371 #define MP1_BASE__INST1_SEG0                      0
0372 #define MP1_BASE__INST1_SEG1                      0
0373 #define MP1_BASE__INST1_SEG2                      0
0374 #define MP1_BASE__INST1_SEG3                      0
0375 #define MP1_BASE__INST1_SEG4                      0
0376
0377 #define MP1_BASE__INST2_SEG0                      0
0378 #define MP1_BASE__INST2_SEG1                      0
0379 #define MP1_BASE__INST2_SEG2                      0
0380 #define MP1_BASE__INST2_SEG3                      0
0381 #define MP1_BASE__INST2_SEG4                      0
0382
0383 #define MP1_BASE__INST3_SEG0                      0
0384 #define MP1_BASE__INST3_SEG1                      0
0385 #define MP1_BASE__INST3_SEG2                      0
0386 #define MP1_BASE__INST3_SEG3                      0
0387 #define MP1_BASE__INST3_SEG4                      0
0388
0389 #define MP1_BASE__INST4_SEG0                      0
0390 #define MP1_BASE__INST4_SEG1                      0
0391 #define MP1_BASE__INST4_SEG2                      0
0392 #define MP1_BASE__INST4_SEG3                      0
0393 #define MP1_BASE__INST4_SEG4                      0
0394
0395 #define MP2_BASE__INST0_SEG0                      0x00016400
0396 #define MP2_BASE__INST0_SEG1                      0
0397 #define MP2_BASE__INST0_SEG2                      0
0398 #define MP2_BASE__INST0_SEG3                      0
0399 #define MP2_BASE__INST0_SEG4                      0
0400
0401 #define MP2_BASE__INST1_SEG0                      0
0402 #define MP2_BASE__INST1_SEG1                      0
0403 #define MP2_BASE__INST1_SEG2                      0
0404 #define MP2_BASE__INST1_SEG3                      0
0405 #define MP2_BASE__INST1_SEG4                      0
0406
0407 #define MP2_BASE__INST2_SEG0                      0
0408 #define MP2_BASE__INST2_SEG1                      0
0409 #define MP2_BASE__INST2_SEG2                      0
0410 #define MP2_BASE__INST2_SEG3                      0
0411 #define MP2_BASE__INST2_SEG4                      0
0412
0413 #define MP2_BASE__INST3_SEG0                      0
0414 #define MP2_BASE__INST3_SEG1                      0
0415 #define MP2_BASE__INST3_SEG2                      0
0416 #define MP2_BASE__INST3_SEG3                      0
0417 #define MP2_BASE__INST3_SEG4                      0
0418
0419 #define MP2_BASE__INST4_SEG0                      0
0420 #define MP2_BASE__INST4_SEG1                      0
0421 #define MP2_BASE__INST4_SEG2                      0
0422 #define MP2_BASE__INST4_SEG3                      0
0423 #define MP2_BASE__INST4_SEG4                      0
0424
0425 #define DF_BASE__INST0_SEG0                       0x00007000
0426 #define DF_BASE__INST0_SEG1                       0
0427 #define DF_BASE__INST0_SEG2                       0
0428 #define DF_BASE__INST0_SEG3                       0
0429 #define DF_BASE__INST0_SEG4                       0
0430
0431 #define DF_BASE__INST1_SEG0                       0
0432 #define DF_BASE__INST1_SEG1                       0
0433 #define DF_BASE__INST1_SEG2                       0
0434 #define DF_BASE__INST1_SEG3                       0
0435 #define DF_BASE__INST1_SEG4                       0
0436
0437 #define DF_BASE__INST2_SEG0                       0
0438 #define DF_BASE__INST2_SEG1                       0
0439 #define DF_BASE__INST2_SEG2                       0
0440 #define DF_BASE__INST2_SEG3                       0
0441 #define DF_BASE__INST2_SEG4                       0
0442
0443 #define DF_BASE__INST3_SEG0                       0
0444 #define DF_BASE__INST3_SEG1                       0
0445 #define DF_BASE__INST3_SEG2                       0
0446 #define DF_BASE__INST3_SEG3                       0
0447 #define DF_BASE__INST3_SEG4                       0
0448
0449 #define DF_BASE__INST4_SEG0                       0
0450 #define DF_BASE__INST4_SEG1                       0
0451 #define DF_BASE__INST4_SEG2                       0
0452 #define DF_BASE__INST4_SEG3                       0
0453 #define DF_BASE__INST4_SEG4                       0
0454
0455 #define UVD_BASE__INST0_SEG0                      0x00007800
0456 #define UVD_BASE__INST0_SEG1                      0x00007E00
0457 #define UVD_BASE__INST0_SEG2                      0
0458 #define UVD_BASE__INST0_SEG3                      0
0459 #define UVD_BASE__INST0_SEG4                      0
0460
0461 #define UVD_BASE__INST1_SEG0                      0
0462 #define UVD_BASE__INST1_SEG1                      0
0463 #define UVD_BASE__INST1_SEG2                      0
0464 #define UVD_BASE__INST1_SEG3                      0
0465 #define UVD_BASE__INST1_SEG4                      0
0466
0467 #define UVD_BASE__INST2_SEG0                      0
0468 #define UVD_BASE__INST2_SEG1                      0
0469 #define UVD_BASE__INST2_SEG2                      0
0470 #define UVD_BASE__INST2_SEG3                      0
0471 #define UVD_BASE__INST2_SEG4                      0
0472
0473 #define UVD_BASE__INST3_SEG0                      0
0474 #define UVD_BASE__INST3_SEG1                      0
0475 #define UVD_BASE__INST3_SEG2                      0
0476 #define UVD_BASE__INST3_SEG3                      0
0477 #define UVD_BASE__INST3_SEG4                      0
0478
0479 #define UVD_BASE__INST4_SEG0                      0
0480 #define UVD_BASE__INST4_SEG1                      0
0481 #define UVD_BASE__INST4_SEG2                      0
0482 #define UVD_BASE__INST4_SEG3                      0
0483 #define UVD_BASE__INST4_SEG4                      0
0484
0485 #define VCN_BASE__INST0_SEG0                      0x00007800
0486 #define VCN_BASE__INST0_SEG1                      0x00007E00
0487 #define VCN_BASE__INST0_SEG2                      0
0488 #define VCN_BASE__INST0_SEG3                      0
0489 #define VCN_BASE__INST0_SEG4                      0
0490
0491 #define VCN_BASE__INST1_SEG0                      0
0492 #define VCN_BASE__INST1_SEG1                      0
0493 #define VCN_BASE__INST1_SEG2                      0
0494 #define VCN_BASE__INST1_SEG3                      0
0495 #define VCN_BASE__INST1_SEG4                      0
0496
0497 #define VCN_BASE__INST2_SEG0                      0
0498 #define VCN_BASE__INST2_SEG1                      0
0499 #define VCN_BASE__INST2_SEG2                      0
0500 #define VCN_BASE__INST2_SEG3                      0
0501 #define VCN_BASE__INST2_SEG4                      0
0502
0503 #define VCN_BASE__INST3_SEG0                      0
0504 #define VCN_BASE__INST3_SEG1                      0
0505 #define VCN_BASE__INST3_SEG2                      0
0506 #define VCN_BASE__INST3_SEG3                      0
0507 #define VCN_BASE__INST3_SEG4                      0
0508
0509 #define VCN_BASE__INST4_SEG0                      0
0510 #define VCN_BASE__INST4_SEG1                      0
0511 #define VCN_BASE__INST4_SEG2                      0
0512 #define VCN_BASE__INST4_SEG3                      0
0513 #define VCN_BASE__INST4_SEG4                      0
0514
0515 #define DBGU_BASE__INST0_SEG0                     0x00000180
0516 #define DBGU_BASE__INST0_SEG1                     0x000001A0
0517 #define DBGU_BASE__INST0_SEG2                     0
0518 #define DBGU_BASE__INST0_SEG3                     0
0519 #define DBGU_BASE__INST0_SEG4                     0
0520
0521 #define DBGU_BASE__INST1_SEG0                     0
0522 #define DBGU_BASE__INST1_SEG1                     0
0523 #define DBGU_BASE__INST1_SEG2                     0
0524 #define DBGU_BASE__INST1_SEG3                     0
0525 #define DBGU_BASE__INST1_SEG4                     0
0526
0527 #define DBGU_BASE__INST2_SEG0                     0
0528 #define DBGU_BASE__INST2_SEG1                     0
0529 #define DBGU_BASE__INST2_SEG2                     0
0530 #define DBGU_BASE__INST2_SEG3                     0
0531 #define DBGU_BASE__INST2_SEG4                     0
0532
0533 #define DBGU_BASE__INST3_SEG0                     0
0534 #define DBGU_BASE__INST3_SEG1                     0
0535 #define DBGU_BASE__INST3_SEG2                     0
0536 #define DBGU_BASE__INST3_SEG3                     0
0537 #define DBGU_BASE__INST3_SEG4                     0
0538
0539 #define DBGU_BASE__INST4_SEG0                     0
0540 #define DBGU_BASE__INST4_SEG1                     0
0541 #define DBGU_BASE__INST4_SEG2                     0
0542 #define DBGU_BASE__INST4_SEG3                     0
0543 #define DBGU_BASE__INST4_SEG4                     0
0544
0545 #define DBGU_NBIO_BASE__INST0_SEG0                0x000001C0
0546 #define DBGU_NBIO_BASE__INST0_SEG1                0
0547 #define DBGU_NBIO_BASE__INST0_SEG2                0
0548 #define DBGU_NBIO_BASE__INST0_SEG3                0
0549 #define DBGU_NBIO_BASE__INST0_SEG4                0
0550
0551 #define DBGU_NBIO_BASE__INST1_SEG0                0
0552 #define DBGU_NBIO_BASE__INST1_SEG1                0
0553 #define DBGU_NBIO_BASE__INST1_SEG2                0
0554 #define DBGU_NBIO_BASE__INST1_SEG3                0
0555 #define DBGU_NBIO_BASE__INST1_SEG4                0
0556
0557 #define DBGU_NBIO_BASE__INST2_SEG0                0
0558 #define DBGU_NBIO_BASE__INST2_SEG1                0
0559 #define DBGU_NBIO_BASE__INST2_SEG2                0
0560 #define DBGU_NBIO_BASE__INST2_SEG3                0
0561 #define DBGU_NBIO_BASE__INST2_SEG4                0
0562
0563 #define DBGU_NBIO_BASE__INST3_SEG0                0
0564 #define DBGU_NBIO_BASE__INST3_SEG1                0
0565 #define DBGU_NBIO_BASE__INST3_SEG2                0
0566 #define DBGU_NBIO_BASE__INST3_SEG3                0
0567 #define DBGU_NBIO_BASE__INST3_SEG4                0
0568
0569 #define DBGU_NBIO_BASE__INST4_SEG0                0
0570 #define DBGU_NBIO_BASE__INST4_SEG1                0
0571 #define DBGU_NBIO_BASE__INST4_SEG2                0
0572 #define DBGU_NBIO_BASE__INST4_SEG3                0
0573 #define DBGU_NBIO_BASE__INST4_SEG4                0
0574
0575 #define DBGU_IO_BASE__INST0_SEG0                  0x000001E0
0576 #define DBGU_IO_BASE__INST0_SEG1                  0
0577 #define DBGU_IO_BASE__INST0_SEG2                  0
0578 #define DBGU_IO_BASE__INST0_SEG3                  0
0579 #define DBGU_IO_BASE__INST0_SEG4                  0
0580
0581 #define DBGU_IO_BASE__INST1_SEG0                  0
0582 #define DBGU_IO_BASE__INST1_SEG1                  0
0583 #define DBGU_IO_BASE__INST1_SEG2                  0
0584 #define DBGU_IO_BASE__INST1_SEG3                  0
0585 #define DBGU_IO_BASE__INST1_SEG4                  0
0586
0587 #define DBGU_IO_BASE__INST2_SEG0                  0
0588 #define DBGU_IO_BASE__INST2_SEG1                  0
0589 #define DBGU_IO_BASE__INST2_SEG2                  0
0590 #define DBGU_IO_BASE__INST2_SEG3                  0
0591 #define DBGU_IO_BASE__INST2_SEG4                  0
0592
0593 #define DBGU_IO_BASE__INST3_SEG0                  0
0594 #define DBGU_IO_BASE__INST3_SEG1                  0
0595 #define DBGU_IO_BASE__INST3_SEG2                  0
0596 #define DBGU_IO_BASE__INST3_SEG3                  0
0597 #define DBGU_IO_BASE__INST3_SEG4                  0
0598
0599 #define DBGU_IO_BASE__INST4_SEG0                  0
0600 #define DBGU_IO_BASE__INST4_SEG1                  0
0601 #define DBGU_IO_BASE__INST4_SEG2                  0
0602 #define DBGU_IO_BASE__INST4_SEG3                  0
0603 #define DBGU_IO_BASE__INST4_SEG4                  0
0604
0605 #define DFX_DAP_BASE__INST0_SEG0                  0x000005A0
0606 #define DFX_DAP_BASE__INST0_SEG1                  0
0607 #define DFX_DAP_BASE__INST0_SEG2                  0
0608 #define DFX_DAP_BASE__INST0_SEG3                  0
0609 #define DFX_DAP_BASE__INST0_SEG4                  0
0610
0611 #define DFX_DAP_BASE__INST1_SEG0                  0
0612 #define DFX_DAP_BASE__INST1_SEG1                  0
0613 #define DFX_DAP_BASE__INST1_SEG2                  0
0614 #define DFX_DAP_BASE__INST1_SEG3                  0
0615 #define DFX_DAP_BASE__INST1_SEG4                  0
0616
0617 #define DFX_DAP_BASE__INST2_SEG0                  0
0618 #define DFX_DAP_BASE__INST2_SEG1                  0
0619 #define DFX_DAP_BASE__INST2_SEG2                  0
0620 #define DFX_DAP_BASE__INST2_SEG3                  0
0621 #define DFX_DAP_BASE__INST2_SEG4                  0
0622
0623 #define DFX_DAP_BASE__INST3_SEG0                  0
0624 #define DFX_DAP_BASE__INST3_SEG1                  0
0625 #define DFX_DAP_BASE__INST3_SEG2                  0
0626 #define DFX_DAP_BASE__INST3_SEG3                  0
0627 #define DFX_DAP_BASE__INST3_SEG4                  0
0628
0629 #define DFX_DAP_BASE__INST4_SEG0                  0
0630 #define DFX_DAP_BASE__INST4_SEG1                  0
0631 #define DFX_DAP_BASE__INST4_SEG2                  0
0632 #define DFX_DAP_BASE__INST4_SEG3                  0
0633 #define DFX_DAP_BASE__INST4_SEG4                  0
0634
0635 #define DFX_BASE__INST0_SEG0                      0x00000580
0636 #define DFX_BASE__INST0_SEG1                      0
0637 #define DFX_BASE__INST0_SEG2                      0
0638 #define DFX_BASE__INST0_SEG3                      0
0639 #define DFX_BASE__INST0_SEG4                      0
0640
0641 #define DFX_BASE__INST1_SEG0                      0
0642 #define DFX_BASE__INST1_SEG1                      0
0643 #define DFX_BASE__INST1_SEG2                      0
0644 #define DFX_BASE__INST1_SEG3                      0
0645 #define DFX_BASE__INST1_SEG4                      0
0646
0647 #define DFX_BASE__INST2_SEG0                      0
0648 #define DFX_BASE__INST2_SEG1                      0
0649 #define DFX_BASE__INST2_SEG2                      0
0650 #define DFX_BASE__INST2_SEG3                      0
0651 #define DFX_BASE__INST2_SEG4                      0
0652
0653 #define DFX_BASE__INST3_SEG0                      0
0654 #define DFX_BASE__INST3_SEG1                      0
0655 #define DFX_BASE__INST3_SEG2                      0
0656 #define DFX_BASE__INST3_SEG3                      0
0657 #define DFX_BASE__INST3_SEG4                      0
0658
0659 #define DFX_BASE__INST4_SEG0                      0
0660 #define DFX_BASE__INST4_SEG1                      0
0661 #define DFX_BASE__INST4_SEG2                      0
0662 #define DFX_BASE__INST4_SEG3                      0
0663 #define DFX_BASE__INST4_SEG4                      0
0664
0665 #define ISP_BASE__INST0_SEG0                      0x00018000
0666 #define ISP_BASE__INST0_SEG1                      0
0667 #define ISP_BASE__INST0_SEG2                      0
0668 #define ISP_BASE__INST0_SEG3                      0
0669 #define ISP_BASE__INST0_SEG4                      0
0670
0671 #define ISP_BASE__INST1_SEG0                      0
0672 #define ISP_BASE__INST1_SEG1                      0
0673 #define ISP_BASE__INST1_SEG2                      0
0674 #define ISP_BASE__INST1_SEG3                      0
0675 #define ISP_BASE__INST1_SEG4                      0
0676
0677 #define ISP_BASE__INST2_SEG0                      0
0678 #define ISP_BASE__INST2_SEG1                      0
0679 #define ISP_BASE__INST2_SEG2                      0
0680 #define ISP_BASE__INST2_SEG3                      0
0681 #define ISP_BASE__INST2_SEG4                      0
0682
0683 #define ISP_BASE__INST3_SEG0                      0
0684 #define ISP_BASE__INST3_SEG1                      0
0685 #define ISP_BASE__INST3_SEG2                      0
0686 #define ISP_BASE__INST3_SEG3                      0
0687 #define ISP_BASE__INST3_SEG4                      0
0688
0689 #define ISP_BASE__INST4_SEG0                      0
0690 #define ISP_BASE__INST4_SEG1                      0
0691 #define ISP_BASE__INST4_SEG2                      0
0692 #define ISP_BASE__INST4_SEG3                      0
0693 #define ISP_BASE__INST4_SEG4                      0
0694
0695 #define SYSTEMHUB_BASE__INST0_SEG0                0x00000EA0
0696 #define SYSTEMHUB_BASE__INST0_SEG1                0
0697 #define SYSTEMHUB_BASE__INST0_SEG2                0
0698 #define SYSTEMHUB_BASE__INST0_SEG3                0
0699 #define SYSTEMHUB_BASE__INST0_SEG4                0
0700
0701 #define SYSTEMHUB_BASE__INST1_SEG0                0
0702 #define SYSTEMHUB_BASE__INST1_SEG1                0
0703 #define SYSTEMHUB_BASE__INST1_SEG2                0
0704 #define SYSTEMHUB_BASE__INST1_SEG3                0
0705 #define SYSTEMHUB_BASE__INST1_SEG4                0
0706
0707 #define SYSTEMHUB_BASE__INST2_SEG0                0
0708 #define SYSTEMHUB_BASE__INST2_SEG1                0
0709 #define SYSTEMHUB_BASE__INST2_SEG2                0
0710 #define SYSTEMHUB_BASE__INST2_SEG3                0
0711 #define SYSTEMHUB_BASE__INST2_SEG4                0
0712
0713 #define SYSTEMHUB_BASE__INST3_SEG0                0
0714 #define SYSTEMHUB_BASE__INST3_SEG1                0
0715 #define SYSTEMHUB_BASE__INST3_SEG2                0
0716 #define SYSTEMHUB_BASE__INST3_SEG3                0
0717 #define SYSTEMHUB_BASE__INST3_SEG4                0
0718
0719 #define SYSTEMHUB_BASE__INST4_SEG0                0
0720 #define SYSTEMHUB_BASE__INST4_SEG1                0
0721 #define SYSTEMHUB_BASE__INST4_SEG2                0
0722 #define SYSTEMHUB_BASE__INST4_SEG3                0
0723 #define SYSTEMHUB_BASE__INST4_SEG4                0
0724
0725 #define L2IMU_BASE__INST0_SEG0                    0x00007DC0
0726 #define L2IMU_BASE__INST0_SEG1                    0
0727 #define L2IMU_BASE__INST0_SEG2                    0
0728 #define L2IMU_BASE__INST0_SEG3                    0
0729 #define L2IMU_BASE__INST0_SEG4                    0
0730
0731 #define L2IMU_BASE__INST1_SEG0                    0
0732 #define L2IMU_BASE__INST1_SEG1                    0
0733 #define L2IMU_BASE__INST1_SEG2                    0
0734 #define L2IMU_BASE__INST1_SEG3                    0
0735 #define L2IMU_BASE__INST1_SEG4                    0
0736
0737 #define L2IMU_BASE__INST2_SEG0                    0
0738 #define L2IMU_BASE__INST2_SEG1                    0
0739 #define L2IMU_BASE__INST2_SEG2                    0
0740 #define L2IMU_BASE__INST2_SEG3                    0
0741 #define L2IMU_BASE__INST2_SEG4                    0
0742
0743 #define L2IMU_BASE__INST3_SEG0                    0
0744 #define L2IMU_BASE__INST3_SEG1                    0
0745 #define L2IMU_BASE__INST3_SEG2                    0
0746 #define L2IMU_BASE__INST3_SEG3                    0
0747 #define L2IMU_BASE__INST3_SEG4                    0
0748
0749 #define L2IMU_BASE__INST4_SEG0                    0
0750 #define L2IMU_BASE__INST4_SEG1                    0
0751 #define L2IMU_BASE__INST4_SEG2                    0
0752 #define L2IMU_BASE__INST4_SEG3                    0
0753 #define L2IMU_BASE__INST4_SEG4                    0
0754
0755 #define IOHC_BASE__INST0_SEG0                     0x00010000
0756 #define IOHC_BASE__INST0_SEG1                     0
0757 #define IOHC_BASE__INST0_SEG2                     0
0758 #define IOHC_BASE__INST0_SEG3                     0
0759 #define IOHC_BASE__INST0_SEG4                     0
0760
0761 #define IOHC_BASE__INST1_SEG0                     0
0762 #define IOHC_BASE__INST1_SEG1                     0
0763 #define IOHC_BASE__INST1_SEG2                     0
0764 #define IOHC_BASE__INST1_SEG3                     0
0765 #define IOHC_BASE__INST1_SEG4                     0
0766
0767 #define IOHC_BASE__INST2_SEG0                     0
0768 #define IOHC_BASE__INST2_SEG1                     0
0769 #define IOHC_BASE__INST2_SEG2                     0
0770 #define IOHC_BASE__INST2_SEG3                     0
0771 #define IOHC_BASE__INST2_SEG4                     0
0772
0773 #define IOHC_BASE__INST3_SEG0                     0
0774 #define IOHC_BASE__INST3_SEG1                     0
0775 #define IOHC_BASE__INST3_SEG2                     0
0776 #define IOHC_BASE__INST3_SEG3                     0
0777 #define IOHC_BASE__INST3_SEG4                     0
0778
0779 #define IOHC_BASE__INST4_SEG0                     0
0780 #define IOHC_BASE__INST4_SEG1                     0
0781 #define IOHC_BASE__INST4_SEG2                     0
0782 #define IOHC_BASE__INST4_SEG3                     0
0783 #define IOHC_BASE__INST4_SEG4                     0
0784
0785 #define ATHUB_BASE__INST0_SEG0                    0x00000C20
0786 #define ATHUB_BASE__INST0_SEG1                    0
0787 #define ATHUB_BASE__INST0_SEG2                    0
0788 #define ATHUB_BASE__INST0_SEG3                    0
0789 #define ATHUB_BASE__INST0_SEG4                    0
0790
0791 #define ATHUB_BASE__INST1_SEG0                    0
0792 #define ATHUB_BASE__INST1_SEG1                    0
0793 #define ATHUB_BASE__INST1_SEG2                    0
0794 #define ATHUB_BASE__INST1_SEG3                    0
0795 #define ATHUB_BASE__INST1_SEG4                    0
0796
0797 #define ATHUB_BASE__INST2_SEG0                    0
0798 #define ATHUB_BASE__INST2_SEG1                    0
0799 #define ATHUB_BASE__INST2_SEG2                    0
0800 #define ATHUB_BASE__INST2_SEG3                    0
0801 #define ATHUB_BASE__INST2_SEG4                    0
0802
0803 #define ATHUB_BASE__INST3_SEG0                    0
0804 #define ATHUB_BASE__INST3_SEG1                    0
0805 #define ATHUB_BASE__INST3_SEG2                    0
0806 #define ATHUB_BASE__INST3_SEG3                    0
0807 #define ATHUB_BASE__INST3_SEG4                    0
0808
0809 #define ATHUB_BASE__INST4_SEG0                    0
0810 #define ATHUB_BASE__INST4_SEG1                    0
0811 #define ATHUB_BASE__INST4_SEG2                    0
0812 #define ATHUB_BASE__INST4_SEG3                    0
0813 #define ATHUB_BASE__INST4_SEG4                    0
0814
0815 #define VCE_BASE__INST0_SEG0                      0x00007E00
0816 #define VCE_BASE__INST0_SEG1                      0x00048800
0817 #define VCE_BASE__INST0_SEG2                      0
0818 #define VCE_BASE__INST0_SEG3                      0
0819 #define VCE_BASE__INST0_SEG4                      0
0820
0821 #define VCE_BASE__INST1_SEG0                      0
0822 #define VCE_BASE__INST1_SEG1                      0
0823 #define VCE_BASE__INST1_SEG2                      0
0824 #define VCE_BASE__INST1_SEG3                      0
0825 #define VCE_BASE__INST1_SEG4                      0
0826
0827 #define VCE_BASE__INST2_SEG0                      0
0828 #define VCE_BASE__INST2_SEG1                      0
0829 #define VCE_BASE__INST2_SEG2                      0
0830 #define VCE_BASE__INST2_SEG3                      0
0831 #define VCE_BASE__INST2_SEG4                      0
0832
0833 #define VCE_BASE__INST3_SEG0                      0
0834 #define VCE_BASE__INST3_SEG1                      0
0835 #define VCE_BASE__INST3_SEG2                      0
0836 #define VCE_BASE__INST3_SEG3                      0
0837 #define VCE_BASE__INST3_SEG4                      0
0838
0839 #define VCE_BASE__INST4_SEG0                      0
0840 #define VCE_BASE__INST4_SEG1                      0
0841 #define VCE_BASE__INST4_SEG2                      0
0842 #define VCE_BASE__INST4_SEG3                      0
0843 #define VCE_BASE__INST4_SEG4                      0
0844
0845 #define GC_BASE__INST0_SEG0                       0x00002000
0846 #define GC_BASE__INST0_SEG1                       0x0000A000
0847 #define GC_BASE__INST0_SEG2                       0
0848 #define GC_BASE__INST0_SEG3                       0
0849 #define GC_BASE__INST0_SEG4                       0
0850
0851 #define GC_BASE__INST1_SEG0                       0
0852 #define GC_BASE__INST1_SEG1                       0
0853 #define GC_BASE__INST1_SEG2                       0
0854 #define GC_BASE__INST1_SEG3                       0
0855 #define GC_BASE__INST1_SEG4                       0
0856
0857 #define GC_BASE__INST2_SEG0                       0
0858 #define GC_BASE__INST2_SEG1                       0
0859 #define GC_BASE__INST2_SEG2                       0
0860 #define GC_BASE__INST2_SEG3                       0
0861 #define GC_BASE__INST2_SEG4                       0
0862
0863 #define GC_BASE__INST3_SEG0                       0
0864 #define GC_BASE__INST3_SEG1                       0
0865 #define GC_BASE__INST3_SEG2                       0
0866 #define GC_BASE__INST3_SEG3                       0
0867 #define GC_BASE__INST3_SEG4                       0
0868
0869 #define GC_BASE__INST4_SEG0                       0
0870 #define GC_BASE__INST4_SEG1                       0
0871 #define GC_BASE__INST4_SEG2                       0
0872 #define GC_BASE__INST4_SEG3                       0
0873 #define GC_BASE__INST4_SEG4                       0
0874
0875 #define MMHUB_BASE__INST0_SEG0                    0x0001A000
0876 #define MMHUB_BASE__INST0_SEG1                    0
0877 #define MMHUB_BASE__INST0_SEG2                    0
0878 #define MMHUB_BASE__INST0_SEG3                    0
0879 #define MMHUB_BASE__INST0_SEG4                    0
0880
0881 #define MMHUB_BASE__INST1_SEG0                    0
0882 #define MMHUB_BASE__INST1_SEG1                    0
0883 #define MMHUB_BASE__INST1_SEG2                    0
0884 #define MMHUB_BASE__INST1_SEG3                    0
0885 #define MMHUB_BASE__INST1_SEG4                    0
0886
0887 #define MMHUB_BASE__INST2_SEG0                    0
0888 #define MMHUB_BASE__INST2_SEG1                    0
0889 #define MMHUB_BASE__INST2_SEG2                    0
0890 #define MMHUB_BASE__INST2_SEG3                    0
0891 #define MMHUB_BASE__INST2_SEG4                    0
0892
0893 #define MMHUB_BASE__INST3_SEG0                    0
0894 #define MMHUB_BASE__INST3_SEG1                    0
0895 #define MMHUB_BASE__INST3_SEG2                    0
0896 #define MMHUB_BASE__INST3_SEG3                    0
0897 #define MMHUB_BASE__INST3_SEG4                    0
0898
0899 #define MMHUB_BASE__INST4_SEG0                    0
0900 #define MMHUB_BASE__INST4_SEG1                    0
0901 #define MMHUB_BASE__INST4_SEG2                    0
0902 #define MMHUB_BASE__INST4_SEG3                    0
0903 #define MMHUB_BASE__INST4_SEG4                    0
0904
0905 #define RSMU_BASE__INST0_SEG0                     0x00012000
0906 #define RSMU_BASE__INST0_SEG1                     0
0907 #define RSMU_BASE__INST0_SEG2                     0
0908 #define RSMU_BASE__INST0_SEG3                     0
0909 #define RSMU_BASE__INST0_SEG4                     0
0910
0911 #define RSMU_BASE__INST1_SEG0                     0
0912 #define RSMU_BASE__INST1_SEG1                     0
0913 #define RSMU_BASE__INST1_SEG2                     0
0914 #define RSMU_BASE__INST1_SEG3                     0
0915 #define RSMU_BASE__INST1_SEG4                     0
0916
0917 #define RSMU_BASE__INST2_SEG0                     0
0918 #define RSMU_BASE__INST2_SEG1                     0
0919 #define RSMU_BASE__INST2_SEG2                     0
0920 #define RSMU_BASE__INST2_SEG3                     0
0921 #define RSMU_BASE__INST2_SEG4                     0
0922
0923 #define RSMU_BASE__INST3_SEG0                     0
0924 #define RSMU_BASE__INST3_SEG1                     0
0925 #define RSMU_BASE__INST3_SEG2                     0
0926 #define RSMU_BASE__INST3_SEG3                     0
0927 #define RSMU_BASE__INST3_SEG4                     0
0928
0929 #define RSMU_BASE__INST4_SEG0                     0
0930 #define RSMU_BASE__INST4_SEG1                     0
0931 #define RSMU_BASE__INST4_SEG2                     0
0932 #define RSMU_BASE__INST4_SEG3                     0
0933 #define RSMU_BASE__INST4_SEG4                     0
0934
0935 #define HDP_BASE__INST0_SEG0                      0x00000F20
0936 #define HDP_BASE__INST0_SEG1                      0
0937 #define HDP_BASE__INST0_SEG2                      0
0938 #define HDP_BASE__INST0_SEG3                      0
0939 #define HDP_BASE__INST0_SEG4                      0
0940
0941 #define HDP_BASE__INST1_SEG0                      0
0942 #define HDP_BASE__INST1_SEG1                      0
0943 #define HDP_BASE__INST1_SEG2                      0
0944 #define HDP_BASE__INST1_SEG3                      0
0945 #define HDP_BASE__INST1_SEG4                      0
0946
0947 #define HDP_BASE__INST2_SEG0                      0
0948 #define HDP_BASE__INST2_SEG1                      0
0949 #define HDP_BASE__INST2_SEG2                      0
0950 #define HDP_BASE__INST2_SEG3                      0
0951 #define HDP_BASE__INST2_SEG4                      0
0952
0953 #define HDP_BASE__INST3_SEG0                      0
0954 #define HDP_BASE__INST3_SEG1                      0
0955 #define HDP_BASE__INST3_SEG2                      0
0956 #define HDP_BASE__INST3_SEG3                      0
0957 #define HDP_BASE__INST3_SEG4                      0
0958
0959 #define HDP_BASE__INST4_SEG0                      0
0960 #define HDP_BASE__INST4_SEG1                      0
0961 #define HDP_BASE__INST4_SEG2                      0
0962 #define HDP_BASE__INST4_SEG3                      0
0963 #define HDP_BASE__INST4_SEG4                      0
0964
0965 #define OSSSYS_BASE__INST0_SEG0                   0x000010A0
0966 #define OSSSYS_BASE__INST0_SEG1                   0
0967 #define OSSSYS_BASE__INST0_SEG2                   0
0968 #define OSSSYS_BASE__INST0_SEG3                   0
0969 #define OSSSYS_BASE__INST0_SEG4                   0
0970
0971 #define OSSSYS_BASE__INST1_SEG0                   0
0972 #define OSSSYS_BASE__INST1_SEG1                   0
0973 #define OSSSYS_BASE__INST1_SEG2                   0
0974 #define OSSSYS_BASE__INST1_SEG3                   0
0975 #define OSSSYS_BASE__INST1_SEG4                   0
0976
0977 #define OSSSYS_BASE__INST2_SEG0                   0
0978 #define OSSSYS_BASE__INST2_SEG1                   0
0979 #define OSSSYS_BASE__INST2_SEG2                   0
0980 #define OSSSYS_BASE__INST2_SEG3                   0
0981 #define OSSSYS_BASE__INST2_SEG4                   0
0982
0983 #define OSSSYS_BASE__INST3_SEG0                   0
0984 #define OSSSYS_BASE__INST3_SEG1                   0
0985 #define OSSSYS_BASE__INST3_SEG2                   0
0986 #define OSSSYS_BASE__INST3_SEG3                   0
0987 #define OSSSYS_BASE__INST3_SEG4                   0
0988
0989 #define OSSSYS_BASE__INST4_SEG0                   0
0990 #define OSSSYS_BASE__INST4_SEG1                   0
0991 #define OSSSYS_BASE__INST4_SEG2                   0
0992 #define OSSSYS_BASE__INST4_SEG3                   0
0993 #define OSSSYS_BASE__INST4_SEG4                   0
0994
0995 #define SDMA0_BASE__INST0_SEG0                    0x00001260
0996 #define SDMA0_BASE__INST0_SEG1                    0
0997 #define SDMA0_BASE__INST0_SEG2                    0
0998 #define SDMA0_BASE__INST0_SEG3                    0
0999 #define SDMA0_BASE__INST0_SEG4                    0
1000
1001 #define SDMA0_BASE__INST1_SEG0                    0
1002 #define SDMA0_BASE__INST1_SEG1                    0
1003 #define SDMA0_BASE__INST1_SEG2                    0
1004 #define SDMA0_BASE__INST1_SEG3                    0
1005 #define SDMA0_BASE__INST1_SEG4                    0
1006
1007 #define SDMA0_BASE__INST2_SEG0                    0
1008 #define SDMA0_BASE__INST2_SEG1                    0
1009 #define SDMA0_BASE__INST2_SEG2                    0
1010 #define SDMA0_BASE__INST2_SEG3                    0
1011 #define SDMA0_BASE__INST2_SEG4                    0
1012
1013 #define SDMA0_BASE__INST3_SEG0                    0
1014 #define SDMA0_BASE__INST3_SEG1                    0
1015 #define SDMA0_BASE__INST3_SEG2                    0
1016 #define SDMA0_BASE__INST3_SEG3                    0
1017 #define SDMA0_BASE__INST3_SEG4                    0
1018
1019 #define SDMA0_BASE__INST4_SEG0                    0
1020 #define SDMA0_BASE__INST4_SEG1                    0
1021 #define SDMA0_BASE__INST4_SEG2                    0
1022 #define SDMA0_BASE__INST4_SEG3                    0
1023 #define SDMA0_BASE__INST4_SEG4                    0
1024
1025 #define SDMA1_BASE__INST0_SEG0                    0x00001460
1026 #define SDMA1_BASE__INST0_SEG1                    0
1027 #define SDMA1_BASE__INST0_SEG2                    0
1028 #define SDMA1_BASE__INST0_SEG3                    0
1029 #define SDMA1_BASE__INST0_SEG4                    0
1030
1031 #define SDMA1_BASE__INST1_SEG0                    0
1032 #define SDMA1_BASE__INST1_SEG1                    0
1033 #define SDMA1_BASE__INST1_SEG2                    0
1034 #define SDMA1_BASE__INST1_SEG3                    0
1035 #define SDMA1_BASE__INST1_SEG4                    0
1036
1037 #define SDMA1_BASE__INST2_SEG0                    0
1038 #define SDMA1_BASE__INST2_SEG1                    0
1039 #define SDMA1_BASE__INST2_SEG2                    0
1040 #define SDMA1_BASE__INST2_SEG3                    0
1041 #define SDMA1_BASE__INST2_SEG4                    0
1042
1043 #define SDMA1_BASE__INST3_SEG0                    0
1044 #define SDMA1_BASE__INST3_SEG1                    0
1045 #define SDMA1_BASE__INST3_SEG2                    0
1046 #define SDMA1_BASE__INST3_SEG3                    0
1047 #define SDMA1_BASE__INST3_SEG4                    0
1048
1049 #define SDMA1_BASE__INST4_SEG0                    0
1050 #define SDMA1_BASE__INST4_SEG1                    0
1051 #define SDMA1_BASE__INST4_SEG2                    0
1052 #define SDMA1_BASE__INST4_SEG3                    0
1053 #define SDMA1_BASE__INST4_SEG4                    0
1054
1055 #define XDMA_BASE__INST0_SEG0                     0x00003400
1056 #define XDMA_BASE__INST0_SEG1                     0
1057 #define XDMA_BASE__INST0_SEG2                     0
1058 #define XDMA_BASE__INST0_SEG3                     0
1059 #define XDMA_BASE__INST0_SEG4                     0
1060
1061 #define XDMA_BASE__INST1_SEG0                     0
1062 #define XDMA_BASE__INST1_SEG1                     0
1063 #define XDMA_BASE__INST1_SEG2                     0
1064 #define XDMA_BASE__INST1_SEG3                     0
1065 #define XDMA_BASE__INST1_SEG4                     0
1066
1067 #define XDMA_BASE__INST2_SEG0                     0
1068 #define XDMA_BASE__INST2_SEG1                     0
1069 #define XDMA_BASE__INST2_SEG2                     0
1070 #define XDMA_BASE__INST2_SEG3                     0
1071 #define XDMA_BASE__INST2_SEG4                     0
1072
1073 #define XDMA_BASE__INST3_SEG0                     0
1074 #define XDMA_BASE__INST3_SEG1                     0
1075 #define XDMA_BASE__INST3_SEG2                     0
1076 #define XDMA_BASE__INST3_SEG3                     0
1077 #define XDMA_BASE__INST3_SEG4                     0
1078
1079 #define XDMA_BASE__INST4_SEG0                     0
1080 #define XDMA_BASE__INST4_SEG1                     0
1081 #define XDMA_BASE__INST4_SEG2                     0
1082 #define XDMA_BASE__INST4_SEG3                     0
1083 #define XDMA_BASE__INST4_SEG4                     0
1084
1085 #define UMC_BASE__INST0_SEG0                      0x00014000
1086 #define UMC_BASE__INST0_SEG1                      0
1087 #define UMC_BASE__INST0_SEG2                      0
1088 #define UMC_BASE__INST0_SEG3                      0
1089 #define UMC_BASE__INST0_SEG4                      0
1090
1091 #define UMC_BASE__INST1_SEG0                      0
1092 #define UMC_BASE__INST1_SEG1                      0
1093 #define UMC_BASE__INST1_SEG2                      0
1094 #define UMC_BASE__INST1_SEG3                      0
1095 #define UMC_BASE__INST1_SEG4                      0
1096
1097 #define UMC_BASE__INST2_SEG0                      0
1098 #define UMC_BASE__INST2_SEG1                      0
1099 #define UMC_BASE__INST2_SEG2                      0
1100 #define UMC_BASE__INST2_SEG3                      0
1101 #define UMC_BASE__INST2_SEG4                      0
1102
1103 #define UMC_BASE__INST3_SEG0                      0
1104 #define UMC_BASE__INST3_SEG1                      0
1105 #define UMC_BASE__INST3_SEG2                      0
1106 #define UMC_BASE__INST3_SEG3                      0
1107 #define UMC_BASE__INST3_SEG4                      0
1108
1109 #define UMC_BASE__INST4_SEG0                      0
1110 #define UMC_BASE__INST4_SEG1                      0
1111 #define UMC_BASE__INST4_SEG2                      0
1112 #define UMC_BASE__INST4_SEG3                      0
1113 #define UMC_BASE__INST4_SEG4                      0
1114
1115 #define THM_BASE__INST0_SEG0                      0x00016600
1116 #define THM_BASE__INST0_SEG1                      0
1117 #define THM_BASE__INST0_SEG2                      0
1118 #define THM_BASE__INST0_SEG3                      0
1119 #define THM_BASE__INST0_SEG4                      0
1120
1121 #define THM_BASE__INST1_SEG0                      0
1122 #define THM_BASE__INST1_SEG1                      0
1123 #define THM_BASE__INST1_SEG2                      0
1124 #define THM_BASE__INST1_SEG3                      0
1125 #define THM_BASE__INST1_SEG4                      0
1126
1127 #define THM_BASE__INST2_SEG0                      0
1128 #define THM_BASE__INST2_SEG1                      0
1129 #define THM_BASE__INST2_SEG2                      0
1130 #define THM_BASE__INST2_SEG3                      0
1131 #define THM_BASE__INST2_SEG4                      0
1132
1133 #define THM_BASE__INST3_SEG0                      0
1134 #define THM_BASE__INST3_SEG1                      0
1135 #define THM_BASE__INST3_SEG2                      0
1136 #define THM_BASE__INST3_SEG3                      0
1137 #define THM_BASE__INST3_SEG4                      0
1138
1139 #define THM_BASE__INST4_SEG0                      0
1140 #define THM_BASE__INST4_SEG1                      0
1141 #define THM_BASE__INST4_SEG2                      0
1142 #define THM_BASE__INST4_SEG3                      0
1143 #define THM_BASE__INST4_SEG4                      0
1144
1145 #define SMUIO_BASE__INST0_SEG0                    0x00016800
1146 #define SMUIO_BASE__INST0_SEG1                    0
1147 #define SMUIO_BASE__INST0_SEG2                    0
1148 #define SMUIO_BASE__INST0_SEG3                    0
1149 #define SMUIO_BASE__INST0_SEG4                    0
1150
1151 #define SMUIO_BASE__INST1_SEG0                    0
1152 #define SMUIO_BASE__INST1_SEG1                    0
1153 #define SMUIO_BASE__INST1_SEG2                    0
1154 #define SMUIO_BASE__INST1_SEG3                    0
1155 #define SMUIO_BASE__INST1_SEG4                    0
1156
1157 #define SMUIO_BASE__INST2_SEG0                    0
1158 #define SMUIO_BASE__INST2_SEG1                    0
1159 #define SMUIO_BASE__INST2_SEG2                    0
1160 #define SMUIO_BASE__INST2_SEG3                    0
1161 #define SMUIO_BASE__INST2_SEG4                    0
1162
1163 #define SMUIO_BASE__INST3_SEG0                    0
1164 #define SMUIO_BASE__INST3_SEG1                    0
1165 #define SMUIO_BASE__INST3_SEG2                    0
1166 #define SMUIO_BASE__INST3_SEG3                    0
1167 #define SMUIO_BASE__INST3_SEG4                    0
1168
1169 #define SMUIO_BASE__INST4_SEG0                    0
1170 #define SMUIO_BASE__INST4_SEG1                    0
1171 #define SMUIO_BASE__INST4_SEG2                    0
1172 #define SMUIO_BASE__INST4_SEG3                    0
1173 #define SMUIO_BASE__INST4_SEG4                    0
1174
1175 #define PWR_BASE__INST0_SEG0                      0x00016A00
1176 #define PWR_BASE__INST0_SEG1                      0
1177 #define PWR_BASE__INST0_SEG2                      0
1178 #define PWR_BASE__INST0_SEG3                      0
1179 #define PWR_BASE__INST0_SEG4                      0
1180
1181 #define PWR_BASE__INST1_SEG0                      0
1182 #define PWR_BASE__INST1_SEG1                      0
1183 #define PWR_BASE__INST1_SEG2                      0
1184 #define PWR_BASE__INST1_SEG3                      0
1185 #define PWR_BASE__INST1_SEG4                      0
1186
1187 #define PWR_BASE__INST2_SEG0                      0
1188 #define PWR_BASE__INST2_SEG1                      0
1189 #define PWR_BASE__INST2_SEG2                      0
1190 #define PWR_BASE__INST2_SEG3                      0
1191 #define PWR_BASE__INST2_SEG4                      0
1192
1193 #define PWR_BASE__INST3_SEG0                      0
1194 #define PWR_BASE__INST3_SEG1                      0
1195 #define PWR_BASE__INST3_SEG2                      0
1196 #define PWR_BASE__INST3_SEG3                      0
1197 #define PWR_BASE__INST3_SEG4                      0
1198
1199 #define PWR_BASE__INST4_SEG0                      0
1200 #define PWR_BASE__INST4_SEG1                      0
1201 #define PWR_BASE__INST4_SEG2                      0
1202 #define PWR_BASE__INST4_SEG3                      0
1203 #define PWR_BASE__INST4_SEG4                      0
1204
1205 #define CLK_BASE__INST0_SEG0                      0x00016C00
1206 #define CLK_BASE__INST0_SEG1                      0
1207 #define CLK_BASE__INST0_SEG2                      0
1208 #define CLK_BASE__INST0_SEG3                      0
1209 #define CLK_BASE__INST0_SEG4                      0
1210
1211 #define CLK_BASE__INST1_SEG0                      0x00016E00
1212 #define CLK_BASE__INST1_SEG1                      0
1213 #define CLK_BASE__INST1_SEG2                      0
1214 #define CLK_BASE__INST1_SEG3                      0
1215 #define CLK_BASE__INST1_SEG4                      0
1216
1217 #define CLK_BASE__INST2_SEG0                      0x00017000
1218 #define CLK_BASE__INST2_SEG1                      0
1219 #define CLK_BASE__INST2_SEG2                      0
1220 #define CLK_BASE__INST2_SEG3                      0
1221 #define CLK_BASE__INST2_SEG4                      0
1222
1223 #define CLK_BASE__INST3_SEG0                      0x00017200
1224 #define CLK_BASE__INST3_SEG1                      0
1225 #define CLK_BASE__INST3_SEG2                      0
1226 #define CLK_BASE__INST3_SEG3                      0
1227 #define CLK_BASE__INST3_SEG4                      0
1228
1229 #define CLK_BASE__INST4_SEG0                      0x00017E00
1230 #define CLK_BASE__INST4_SEG1                      0
1231 #define CLK_BASE__INST4_SEG2                      0
1232 #define CLK_BASE__INST4_SEG3                      0
1233 #define CLK_BASE__INST4_SEG4                      0
1234
1235 #define FUSE_BASE__INST0_SEG0                     0x00017400
1236 #define FUSE_BASE__INST0_SEG1                     0
1237 #define FUSE_BASE__INST0_SEG2                     0
1238 #define FUSE_BASE__INST0_SEG3                     0
1239 #define FUSE_BASE__INST0_SEG4                     0
1240
1241 #define FUSE_BASE__INST1_SEG0                     0
1242 #define FUSE_BASE__INST1_SEG1                     0
1243 #define FUSE_BASE__INST1_SEG2                     0
1244 #define FUSE_BASE__INST1_SEG3                     0
1245 #define FUSE_BASE__INST1_SEG4                     0
1246
1247 #define FUSE_BASE__INST2_SEG0                     0
1248 #define FUSE_BASE__INST2_SEG1                     0
1249 #define FUSE_BASE__INST2_SEG2                     0
1250 #define FUSE_BASE__INST2_SEG3                     0
1251 #define FUSE_BASE__INST2_SEG4                     0
1252
1253 #define FUSE_BASE__INST3_SEG0                     0
1254 #define FUSE_BASE__INST3_SEG1                     0
1255 #define FUSE_BASE__INST3_SEG2                     0
1256 #define FUSE_BASE__INST3_SEG3                     0
1257 #define FUSE_BASE__INST3_SEG4                     0
1258
1259 #define FUSE_BASE__INST4_SEG0                     0
1260 #define FUSE_BASE__INST4_SEG1                     0
1261 #define FUSE_BASE__INST4_SEG2                     0
1262 #define FUSE_BASE__INST4_SEG3                     0
1263 #define FUSE_BASE__INST4_SEG4                     0
1264 #endif
1265