amd/include/v11_structs.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef V11_STRUCTS_H_
0025 #define V11_STRUCTS_H_
0026
0027 struct v11_gfx_mqd {
0028     uint32_t reserved_0; // offset: 0  (0x0)
0029     uint32_t reserved_1; // offset: 1  (0x1)
0030     uint32_t reserved_2; // offset: 2  (0x2)
0031     uint32_t reserved_3; // offset: 3  (0x3)
0032     uint32_t reserved_4; // offset: 4  (0x4)
0033     uint32_t reserved_5; // offset: 5  (0x5)
0034     uint32_t reserved_6; // offset: 6  (0x6)
0035     uint32_t reserved_7; // offset: 7  (0x7)
0036     uint32_t reserved_8; // offset: 8  (0x8)
0037     uint32_t reserved_9; // offset: 9  (0x9)
0038     uint32_t reserved_10; // offset: 10  (0xA)
0039     uint32_t reserved_11; // offset: 11  (0xB)
0040     uint32_t reserved_12; // offset: 12  (0xC)
0041     uint32_t reserved_13; // offset: 13  (0xD)
0042     uint32_t reserved_14; // offset: 14  (0xE)
0043     uint32_t reserved_15; // offset: 15  (0xF)
0044     uint32_t reserved_16; // offset: 16  (0x10)
0045     uint32_t reserved_17; // offset: 17  (0x11)
0046     uint32_t reserved_18; // offset: 18  (0x12)
0047     uint32_t reserved_19; // offset: 19  (0x13)
0048     uint32_t reserved_20; // offset: 20  (0x14)
0049     uint32_t reserved_21; // offset: 21  (0x15)
0050     uint32_t reserved_22; // offset: 22  (0x16)
0051     uint32_t reserved_23; // offset: 23  (0x17)
0052     uint32_t reserved_24; // offset: 24  (0x18)
0053     uint32_t reserved_25; // offset: 25  (0x19)
0054     uint32_t reserved_26; // offset: 26  (0x1A)
0055     uint32_t reserved_27; // offset: 27  (0x1B)
0056     uint32_t reserved_28; // offset: 28  (0x1C)
0057     uint32_t reserved_29; // offset: 29  (0x1D)
0058     uint32_t reserved_30; // offset: 30  (0x1E)
0059     uint32_t reserved_31; // offset: 31  (0x1F)
0060     uint32_t reserved_32; // offset: 32  (0x20)
0061     uint32_t reserved_33; // offset: 33  (0x21)
0062     uint32_t reserved_34; // offset: 34  (0x22)
0063     uint32_t reserved_35; // offset: 35  (0x23)
0064     uint32_t reserved_36; // offset: 36  (0x24)
0065     uint32_t reserved_37; // offset: 37  (0x25)
0066     uint32_t reserved_38; // offset: 38  (0x26)
0067     uint32_t reserved_39; // offset: 39  (0x27)
0068     uint32_t reserved_40; // offset: 40  (0x28)
0069     uint32_t reserved_41; // offset: 41  (0x29)
0070     uint32_t reserved_42; // offset: 42  (0x2A)
0071     uint32_t reserved_43; // offset: 43  (0x2B)
0072     uint32_t reserved_44; // offset: 44  (0x2C)
0073     uint32_t reserved_45; // offset: 45  (0x2D)
0074     uint32_t reserved_46; // offset: 46  (0x2E)
0075     uint32_t reserved_47; // offset: 47  (0x2F)
0076     uint32_t reserved_48; // offset: 48  (0x30)
0077     uint32_t reserved_49; // offset: 49  (0x31)
0078     uint32_t reserved_50; // offset: 50  (0x32)
0079     uint32_t reserved_51; // offset: 51  (0x33)
0080     uint32_t reserved_52; // offset: 52  (0x34)
0081     uint32_t reserved_53; // offset: 53  (0x35)
0082     uint32_t reserved_54; // offset: 54  (0x36)
0083     uint32_t reserved_55; // offset: 55  (0x37)
0084     uint32_t reserved_56; // offset: 56  (0x38)
0085     uint32_t reserved_57; // offset: 57  (0x39)
0086     uint32_t reserved_58; // offset: 58  (0x3A)
0087     uint32_t reserved_59; // offset: 59  (0x3B)
0088     uint32_t reserved_60; // offset: 60  (0x3C)
0089     uint32_t reserved_61; // offset: 61  (0x3D)
0090     uint32_t reserved_62; // offset: 62  (0x3E)
0091     uint32_t reserved_63; // offset: 63  (0x3F)
0092     uint32_t reserved_64; // offset: 64  (0x40)
0093     uint32_t reserved_65; // offset: 65  (0x41)
0094     uint32_t reserved_66; // offset: 66  (0x42)
0095     uint32_t reserved_67; // offset: 67  (0x43)
0096     uint32_t reserved_68; // offset: 68  (0x44)
0097     uint32_t reserved_69; // offset: 69  (0x45)
0098     uint32_t reserved_70; // offset: 70  (0x46)
0099     uint32_t reserved_71; // offset: 71  (0x47)
0100     uint32_t reserved_72; // offset: 72  (0x48)
0101     uint32_t reserved_73; // offset: 73  (0x49)
0102     uint32_t reserved_74; // offset: 74  (0x4A)
0103     uint32_t reserved_75; // offset: 75  (0x4B)
0104     uint32_t reserved_76; // offset: 76  (0x4C)
0105     uint32_t reserved_77; // offset: 77  (0x4D)
0106     uint32_t reserved_78; // offset: 78  (0x4E)
0107     uint32_t reserved_79; // offset: 79  (0x4F)
0108     uint32_t reserved_80; // offset: 80  (0x50)
0109     uint32_t reserved_81; // offset: 81  (0x51)
0110     uint32_t reserved_82; // offset: 82  (0x52)
0111     uint32_t reserved_83; // offset: 83  (0x53)
0112     uint32_t checksum_lo; // offset: 84  (0x54)
0113     uint32_t checksum_hi; // offset: 85  (0x55)
0114     uint32_t cp_mqd_query_time_lo; // offset: 86  (0x56)
0115     uint32_t cp_mqd_query_time_hi; // offset: 87  (0x57)
0116     uint32_t reserved_88; // offset: 88  (0x58)
0117     uint32_t reserved_89; // offset: 89  (0x59)
0118     uint32_t reserved_90; // offset: 90  (0x5A)
0119     uint32_t reserved_91; // offset: 91  (0x5B)
0120     uint32_t cp_mqd_query_wave_count; // offset: 92  (0x5C)
0121     uint32_t cp_mqd_query_gfx_hqd_rptr; // offset: 93  (0x5D)
0122     uint32_t cp_mqd_query_gfx_hqd_wptr; // offset: 94  (0x5E)
0123     uint32_t cp_mqd_query_gfx_hqd_offset; // offset: 95  (0x5F)
0124     uint32_t reserved_96; // offset: 96  (0x60)
0125     uint32_t reserved_97; // offset: 97  (0x61)
0126     uint32_t reserved_98; // offset: 98  (0x62)
0127     uint32_t reserved_99; // offset: 99  (0x63)
0128     uint32_t reserved_100; // offset: 100  (0x64)
0129     uint32_t reserved_101; // offset: 101  (0x65)
0130     uint32_t reserved_102; // offset: 102  (0x66)
0131     uint32_t reserved_103; // offset: 103  (0x67)
0132     uint32_t control_buf_addr_lo; // offset: 104  (0x68)
0133     uint32_t control_buf_addr_hi; // offset: 105  (0x69)
0134     uint32_t disable_queue; // offset: 106  (0x6A)
0135     uint32_t reserved_107; // offset: 107  (0x6B)
0136     uint32_t reserved_108; // offset: 108  (0x6C)
0137     uint32_t reserved_109; // offset: 109  (0x6D)
0138     uint32_t reserved_110; // offset: 110  (0x6E)
0139     uint32_t reserved_111; // offset: 111  (0x6F)
0140     uint32_t reserved_112; // offset: 112  (0x70)
0141     uint32_t reserved_113; // offset: 113  (0x71)
0142     uint32_t reserved_114; // offset: 114  (0x72)
0143     uint32_t reserved_115; // offset: 115  (0x73)
0144     uint32_t reserved_116; // offset: 116  (0x74)
0145     uint32_t reserved_117; // offset: 117  (0x75)
0146     uint32_t reserved_118; // offset: 118  (0x76)
0147     uint32_t reserved_119; // offset: 119  (0x77)
0148     uint32_t reserved_120; // offset: 120  (0x78)
0149     uint32_t reserved_121; // offset: 121  (0x79)
0150     uint32_t reserved_122; // offset: 122  (0x7A)
0151     uint32_t reserved_123; // offset: 123  (0x7B)
0152     uint32_t reserved_124; // offset: 124  (0x7C)
0153     uint32_t reserved_125; // offset: 125  (0x7D)
0154     uint32_t reserved_126; // offset: 126  (0x7E)
0155     uint32_t reserved_127; // offset: 127  (0x7F)
0156     uint32_t cp_mqd_base_addr; // offset: 128  (0x80)
0157     uint32_t cp_mqd_base_addr_hi; // offset: 129  (0x81)
0158     uint32_t cp_gfx_hqd_active; // offset: 130  (0x82)
0159     uint32_t cp_gfx_hqd_vmid; // offset: 131  (0x83)
0160     uint32_t reserved_131; // offset: 132  (0x84)
0161     uint32_t reserved_132; // offset: 133  (0x85)
0162     uint32_t cp_gfx_hqd_queue_priority; // offset: 134  (0x86)
0163     uint32_t cp_gfx_hqd_quantum; // offset: 135  (0x87)
0164     uint32_t cp_gfx_hqd_base; // offset: 136  (0x88)
0165     uint32_t cp_gfx_hqd_base_hi; // offset: 137  (0x89)
0166     uint32_t cp_gfx_hqd_rptr; // offset: 138  (0x8A)
0167     uint32_t cp_gfx_hqd_rptr_addr; // offset: 139  (0x8B)
0168     uint32_t cp_gfx_hqd_rptr_addr_hi; // offset: 140  (0x8C)
0169     uint32_t cp_rb_wptr_poll_addr_lo; // offset: 141  (0x8D)
0170     uint32_t cp_rb_wptr_poll_addr_hi; // offset: 142  (0x8E)
0171     uint32_t cp_rb_doorbell_control; // offset: 143  (0x8F)
0172     uint32_t cp_gfx_hqd_offset; // offset: 144  (0x90)
0173     uint32_t cp_gfx_hqd_cntl; // offset: 145  (0x91)
0174     uint32_t reserved_146; // offset: 146  (0x92)
0175     uint32_t reserved_147; // offset: 147  (0x93)
0176     uint32_t cp_gfx_hqd_csmd_rptr; // offset: 148  (0x94)
0177     uint32_t cp_gfx_hqd_wptr; // offset: 149  (0x95)
0178     uint32_t cp_gfx_hqd_wptr_hi; // offset: 150  (0x96)
0179     uint32_t reserved_151; // offset: 151  (0x97)
0180     uint32_t reserved_152; // offset: 152  (0x98)
0181     uint32_t reserved_153; // offset: 153  (0x99)
0182     uint32_t reserved_154; // offset: 154  (0x9A)
0183     uint32_t reserved_155; // offset: 155  (0x9B)
0184     uint32_t cp_gfx_hqd_mapped; // offset: 156  (0x9C)
0185     uint32_t cp_gfx_hqd_que_mgr_control; // offset: 157  (0x9D)
0186     uint32_t reserved_158; // offset: 158  (0x9E)
0187     uint32_t reserved_159; // offset: 159  (0x9F)
0188     uint32_t cp_gfx_hqd_hq_status0; // offset: 160  (0xA0)
0189     uint32_t cp_gfx_hqd_hq_control0; // offset: 161  (0xA1)
0190     uint32_t cp_gfx_mqd_control; // offset: 162  (0xA2)
0191     uint32_t reserved_163; // offset: 163  (0xA3)
0192     uint32_t reserved_164; // offset: 164  (0xA4)
0193     uint32_t reserved_165; // offset: 165  (0xA5)
0194     uint32_t reserved_166; // offset: 166  (0xA6)
0195     uint32_t reserved_167; // offset: 167  (0xA7)
0196     uint32_t reserved_168; // offset: 168  (0xA8)
0197     uint32_t reserved_169; // offset: 169  (0xA9)
0198     uint32_t cp_num_prim_needed_count0_lo; // offset: 170  (0xAA)
0199     uint32_t cp_num_prim_needed_count0_hi; // offset: 171  (0xAB)
0200     uint32_t cp_num_prim_needed_count1_lo; // offset: 172  (0xAC)
0201     uint32_t cp_num_prim_needed_count1_hi; // offset: 173  (0xAD)
0202     uint32_t cp_num_prim_needed_count2_lo; // offset: 174  (0xAE)
0203     uint32_t cp_num_prim_needed_count2_hi; // offset: 175  (0xAF)
0204     uint32_t cp_num_prim_needed_count3_lo; // offset: 176  (0xB0)
0205     uint32_t cp_num_prim_needed_count3_hi; // offset: 177  (0xB1)
0206     uint32_t cp_num_prim_written_count0_lo; // offset: 178  (0xB2)
0207     uint32_t cp_num_prim_written_count0_hi; // offset: 179  (0xB3)
0208     uint32_t cp_num_prim_written_count1_lo; // offset: 180  (0xB4)
0209     uint32_t cp_num_prim_written_count1_hi; // offset: 181  (0xB5)
0210     uint32_t cp_num_prim_written_count2_lo; // offset: 182  (0xB6)
0211     uint32_t cp_num_prim_written_count2_hi; // offset: 183  (0xB7)
0212     uint32_t cp_num_prim_written_count3_lo; // offset: 184  (0xB8)
0213     uint32_t cp_num_prim_written_count3_hi; // offset: 185  (0xB9)
0214     uint32_t reserved_186; // offset: 186  (0xBA)
0215     uint32_t reserved_187; // offset: 187  (0xBB)
0216     uint32_t reserved_188; // offset: 188  (0xBC)
0217     uint32_t reserved_189; // offset: 189  (0xBD)
0218     uint32_t mp1_smn_fps_cnt; // offset: 190  (0xBE)
0219     uint32_t sq_thread_trace_buf0_base; // offset: 191  (0xBF)
0220     uint32_t sq_thread_trace_buf0_size; // offset: 192  (0xC0)
0221     uint32_t sq_thread_trace_buf1_base; // offset: 193  (0xC1)
0222     uint32_t sq_thread_trace_buf1_size; // offset: 194  (0xC2)
0223     uint32_t sq_thread_trace_wptr; // offset: 195  (0xC3)
0224     uint32_t sq_thread_trace_mask; // offset: 196  (0xC4)
0225     uint32_t sq_thread_trace_token_mask; // offset: 197  (0xC5)
0226     uint32_t sq_thread_trace_ctrl; // offset: 198  (0xC6)
0227     uint32_t sq_thread_trace_status; // offset: 199  (0xC7)
0228     uint32_t sq_thread_trace_dropped_cntr; // offset: 200  (0xC8)
0229     uint32_t sq_thread_trace_finish_done_debug; // offset: 201  (0xC9)
0230     uint32_t sq_thread_trace_gfx_draw_cntr; // offset: 202  (0xCA)
0231     uint32_t sq_thread_trace_gfx_marker_cntr; // offset: 203  (0xCB)
0232     uint32_t sq_thread_trace_hp3d_draw_cntr; // offset: 204  (0xCC)
0233     uint32_t sq_thread_trace_hp3d_marker_cntr; // offset: 205  (0xCD)
0234     uint32_t reserved_206; // offset: 206  (0xCE)
0235     uint32_t reserved_207; // offset: 207  (0xCF)
0236     uint32_t cp_sc_psinvoc_count0_lo; // offset: 208  (0xD0)
0237     uint32_t cp_sc_psinvoc_count0_hi; // offset: 209  (0xD1)
0238     uint32_t cp_pa_cprim_count_lo; // offset: 210  (0xD2)
0239     uint32_t cp_pa_cprim_count_hi; // offset: 211  (0xD3)
0240     uint32_t cp_pa_cinvoc_count_lo; // offset: 212  (0xD4)
0241     uint32_t cp_pa_cinvoc_count_hi; // offset: 213  (0xD5)
0242     uint32_t cp_vgt_vsinvoc_count_lo; // offset: 214  (0xD6)
0243     uint32_t cp_vgt_vsinvoc_count_hi; // offset: 215  (0xD7)
0244     uint32_t cp_vgt_gsinvoc_count_lo; // offset: 216  (0xD8)
0245     uint32_t cp_vgt_gsinvoc_count_hi; // offset: 217  (0xD9)
0246     uint32_t cp_vgt_gsprim_count_lo; // offset: 218  (0xDA)
0247     uint32_t cp_vgt_gsprim_count_hi; // offset: 219  (0xDB)
0248     uint32_t cp_vgt_iaprim_count_lo; // offset: 220  (0xDC)
0249     uint32_t cp_vgt_iaprim_count_hi; // offset: 221  (0xDD)
0250     uint32_t cp_vgt_iavert_count_lo; // offset: 222  (0xDE)
0251     uint32_t cp_vgt_iavert_count_hi; // offset: 223  (0xDF)
0252     uint32_t cp_vgt_hsinvoc_count_lo; // offset: 224  (0xE0)
0253     uint32_t cp_vgt_hsinvoc_count_hi; // offset: 225  (0xE1)
0254     uint32_t cp_vgt_dsinvoc_count_lo; // offset: 226  (0xE2)
0255     uint32_t cp_vgt_dsinvoc_count_hi; // offset: 227  (0xE3)
0256     uint32_t cp_vgt_csinvoc_count_lo; // offset: 228  (0xE4)
0257     uint32_t cp_vgt_csinvoc_count_hi; // offset: 229  (0xE5)
0258     uint32_t reserved_230; // offset: 230  (0xE6)
0259     uint32_t reserved_231; // offset: 231  (0xE7)
0260     uint32_t reserved_232; // offset: 232  (0xE8)
0261     uint32_t reserved_233; // offset: 233  (0xE9)
0262     uint32_t reserved_234; // offset: 234  (0xEA)
0263     uint32_t reserved_235; // offset: 235  (0xEB)
0264     uint32_t reserved_236; // offset: 236  (0xEC)
0265     uint32_t reserved_237; // offset: 237  (0xED)
0266     uint32_t reserved_238; // offset: 238  (0xEE)
0267     uint32_t reserved_239; // offset: 239  (0xEF)
0268     uint32_t reserved_240; // offset: 240  (0xF0)
0269     uint32_t reserved_241; // offset: 241  (0xF1)
0270     uint32_t reserved_242; // offset: 242  (0xF2)
0271     uint32_t reserved_243; // offset: 243  (0xF3)
0272     uint32_t reserved_244; // offset: 244  (0xF4)
0273     uint32_t reserved_245; // offset: 245  (0xF5)
0274     uint32_t reserved_246; // offset: 246  (0xF6)
0275     uint32_t reserved_247; // offset: 247  (0xF7)
0276     uint32_t reserved_248; // offset: 248  (0xF8)
0277     uint32_t reserved_249; // offset: 249  (0xF9)
0278     uint32_t reserved_250; // offset: 250  (0xFA)
0279     uint32_t reserved_251; // offset: 251  (0xFB)
0280     uint32_t reserved_252; // offset: 252  (0xFC)
0281     uint32_t reserved_253; // offset: 253  (0xFD)
0282     uint32_t reserved_254; // offset: 254  (0xFE)
0283     uint32_t reserved_255; // offset: 255  (0xFF)
0284     uint32_t reserved_256; // offset: 256  (0x100)
0285     uint32_t reserved_257; // offset: 257  (0x101)
0286     uint32_t reserved_258; // offset: 258  (0x102)
0287     uint32_t reserved_259; // offset: 259  (0x103)
0288     uint32_t reserved_260; // offset: 260  (0x104)
0289     uint32_t reserved_261; // offset: 261  (0x105)
0290     uint32_t reserved_262; // offset: 262  (0x106)
0291     uint32_t reserved_263; // offset: 263  (0x107)
0292     uint32_t reserved_264; // offset: 264  (0x108)
0293     uint32_t reserved_265; // offset: 265  (0x109)
0294     uint32_t reserved_266; // offset: 266  (0x10A)
0295     uint32_t reserved_267; // offset: 267  (0x10B)
0296     uint32_t vgt_strmout_buffer_filled_size_0; // offset: 268  (0x10C)
0297     uint32_t vgt_strmout_buffer_filled_size_1; // offset: 269  (0x10D)
0298     uint32_t vgt_strmout_buffer_filled_size_2; // offset: 270  (0x10E)
0299     uint32_t vgt_strmout_buffer_filled_size_3; // offset: 271  (0x10F)
0300     uint32_t reserved_272; // offset: 272  (0x110)
0301     uint32_t reserved_273; // offset: 273  (0x111)
0302     uint32_t reserved_274; // offset: 274  (0x112)
0303     uint32_t reserved_275; // offset: 275  (0x113)
0304     uint32_t vgt_dma_max_size; // offset: 276  (0x114)
0305     uint32_t vgt_dma_num_instances; // offset: 277  (0x115)
0306     uint32_t reserved_278; // offset: 278  (0x116)
0307     uint32_t reserved_279; // offset: 279  (0x117)
0308     uint32_t reserved_280; // offset: 280  (0x118)
0309     uint32_t reserved_281; // offset: 281  (0x119)
0310     uint32_t reserved_282; // offset: 282  (0x11A)
0311     uint32_t reserved_283; // offset: 283  (0x11B)
0312     uint32_t reserved_284; // offset: 284  (0x11C)
0313     uint32_t reserved_285; // offset: 285  (0x11D)
0314     uint32_t reserved_286; // offset: 286  (0x11E)
0315     uint32_t reserved_287; // offset: 287  (0x11F)
0316     uint32_t it_set_base_ib_addr_lo; // offset: 288  (0x120)
0317     uint32_t it_set_base_ib_addr_hi; // offset: 289  (0x121)
0318     uint32_t reserved_290; // offset: 290  (0x122)
0319     uint32_t reserved_291; // offset: 291  (0x123)
0320     uint32_t reserved_292; // offset: 292  (0x124)
0321     uint32_t reserved_293; // offset: 293  (0x125)
0322     uint32_t reserved_294; // offset: 294  (0x126)
0323     uint32_t reserved_295; // offset: 295  (0x127)
0324     uint32_t reserved_296; // offset: 296  (0x128)
0325     uint32_t reserved_297; // offset: 297  (0x129)
0326     uint32_t reserved_298; // offset: 298  (0x12A)
0327     uint32_t reserved_299; // offset: 299  (0x12B)
0328     uint32_t reserved_300; // offset: 300  (0x12C)
0329     uint32_t reserved_301; // offset: 301  (0x12D)
0330     uint32_t reserved_302; // offset: 302  (0x12E)
0331     uint32_t reserved_303; // offset: 303  (0x12F)
0332     uint32_t reserved_304; // offset: 304  (0x130)
0333     uint32_t reserved_305; // offset: 305  (0x131)
0334     uint32_t reserved_306; // offset: 306  (0x132)
0335     uint32_t reserved_307; // offset: 307  (0x133)
0336     uint32_t reserved_308; // offset: 308  (0x134)
0337     uint32_t reserved_309; // offset: 309  (0x135)
0338     uint32_t reserved_310; // offset: 310  (0x136)
0339     uint32_t reserved_311; // offset: 311  (0x137)
0340     uint32_t reserved_312; // offset: 312  (0x138)
0341     uint32_t reserved_313; // offset: 313  (0x139)
0342     uint32_t reserved_314; // offset: 314  (0x13A)
0343     uint32_t reserved_315; // offset: 315  (0x13B)
0344     uint32_t reserved_316; // offset: 316  (0x13C)
0345     uint32_t reserved_317; // offset: 317  (0x13D)
0346     uint32_t reserved_318; // offset: 318  (0x13E)
0347     uint32_t reserved_319; // offset: 319  (0x13F)
0348     uint32_t reserved_320; // offset: 320  (0x140)
0349     uint32_t reserved_321; // offset: 321  (0x141)
0350     uint32_t reserved_322; // offset: 322  (0x142)
0351     uint32_t reserved_323; // offset: 323  (0x143)
0352     uint32_t reserved_324; // offset: 324  (0x144)
0353     uint32_t reserved_325; // offset: 325  (0x145)
0354     uint32_t reserved_326; // offset: 326  (0x146)
0355     uint32_t reserved_327; // offset: 327  (0x147)
0356     uint32_t reserved_328; // offset: 328  (0x148)
0357     uint32_t reserved_329; // offset: 329  (0x149)
0358     uint32_t reserved_330; // offset: 330  (0x14A)
0359     uint32_t reserved_331; // offset: 331  (0x14B)
0360     uint32_t reserved_332; // offset: 332  (0x14C)
0361     uint32_t reserved_333; // offset: 333  (0x14D)
0362     uint32_t reserved_334; // offset: 334  (0x14E)
0363     uint32_t reserved_335; // offset: 335  (0x14F)
0364     uint32_t reserved_336; // offset: 336  (0x150)
0365     uint32_t reserved_337; // offset: 337  (0x151)
0366     uint32_t reserved_338; // offset: 338  (0x152)
0367     uint32_t reserved_339; // offset: 339  (0x153)
0368     uint32_t reserved_340; // offset: 340  (0x154)
0369     uint32_t reserved_341; // offset: 341  (0x155)
0370     uint32_t reserved_342; // offset: 342  (0x156)
0371     uint32_t reserved_343; // offset: 343  (0x157)
0372     uint32_t reserved_344; // offset: 344  (0x158)
0373     uint32_t reserved_345; // offset: 345  (0x159)
0374     uint32_t reserved_346; // offset: 346  (0x15A)
0375     uint32_t reserved_347; // offset: 347  (0x15B)
0376     uint32_t reserved_348; // offset: 348  (0x15C)
0377     uint32_t reserved_349; // offset: 349  (0x15D)
0378     uint32_t reserved_350; // offset: 350  (0x15E)
0379     uint32_t reserved_351; // offset: 351  (0x15F)
0380     uint32_t reserved_352; // offset: 352  (0x160)
0381     uint32_t reserved_353; // offset: 353  (0x161)
0382     uint32_t reserved_354; // offset: 354  (0x162)
0383     uint32_t reserved_355; // offset: 355  (0x163)
0384     uint32_t spi_shader_pgm_rsrc3_ps; // offset: 356  (0x164)
0385     uint32_t spi_shader_pgm_rsrc3_vs; // offset: 357  (0x165)
0386     uint32_t spi_shader_pgm_rsrc3_gs; // offset: 358  (0x166)
0387     uint32_t spi_shader_pgm_rsrc3_hs; // offset: 359  (0x167)
0388     uint32_t spi_shader_pgm_rsrc4_ps; // offset: 360  (0x168)
0389     uint32_t spi_shader_pgm_rsrc4_vs; // offset: 361  (0x169)
0390     uint32_t spi_shader_pgm_rsrc4_gs; // offset: 362  (0x16A)
0391     uint32_t spi_shader_pgm_rsrc4_hs; // offset: 363  (0x16B)
0392     uint32_t db_occlusion_count0_low_00; // offset: 364  (0x16C)
0393     uint32_t db_occlusion_count0_hi_00; // offset: 365  (0x16D)
0394     uint32_t db_occlusion_count1_low_00; // offset: 366  (0x16E)
0395     uint32_t db_occlusion_count1_hi_00; // offset: 367  (0x16F)
0396     uint32_t db_occlusion_count2_low_00; // offset: 368  (0x170)
0397     uint32_t db_occlusion_count2_hi_00; // offset: 369  (0x171)
0398     uint32_t db_occlusion_count3_low_00; // offset: 370  (0x172)
0399     uint32_t db_occlusion_count3_hi_00; // offset: 371  (0x173)
0400     uint32_t db_occlusion_count0_low_01; // offset: 372  (0x174)
0401     uint32_t db_occlusion_count0_hi_01; // offset: 373  (0x175)
0402     uint32_t db_occlusion_count1_low_01; // offset: 374  (0x176)
0403     uint32_t db_occlusion_count1_hi_01; // offset: 375  (0x177)
0404     uint32_t db_occlusion_count2_low_01; // offset: 376  (0x178)
0405     uint32_t db_occlusion_count2_hi_01; // offset: 377  (0x179)
0406     uint32_t db_occlusion_count3_low_01; // offset: 378  (0x17A)
0407     uint32_t db_occlusion_count3_hi_01; // offset: 379  (0x17B)
0408     uint32_t db_occlusion_count0_low_02; // offset: 380  (0x17C)
0409     uint32_t db_occlusion_count0_hi_02; // offset: 381  (0x17D)
0410     uint32_t db_occlusion_count1_low_02; // offset: 382  (0x17E)
0411     uint32_t db_occlusion_count1_hi_02; // offset: 383  (0x17F)
0412     uint32_t db_occlusion_count2_low_02; // offset: 384  (0x180)
0413     uint32_t db_occlusion_count2_hi_02; // offset: 385  (0x181)
0414     uint32_t db_occlusion_count3_low_02; // offset: 386  (0x182)
0415     uint32_t db_occlusion_count3_hi_02; // offset: 387  (0x183)
0416     uint32_t db_occlusion_count0_low_03; // offset: 388  (0x184)
0417     uint32_t db_occlusion_count0_hi_03; // offset: 389  (0x185)
0418     uint32_t db_occlusion_count1_low_03; // offset: 390  (0x186)
0419     uint32_t db_occlusion_count1_hi_03; // offset: 391  (0x187)
0420     uint32_t db_occlusion_count2_low_03; // offset: 392  (0x188)
0421     uint32_t db_occlusion_count2_hi_03; // offset: 393  (0x189)
0422     uint32_t db_occlusion_count3_low_03; // offset: 394  (0x18A)
0423     uint32_t db_occlusion_count3_hi_03; // offset: 395  (0x18B)
0424     uint32_t db_occlusion_count0_low_04; // offset: 396  (0x18C)
0425     uint32_t db_occlusion_count0_hi_04; // offset: 397  (0x18D)
0426     uint32_t db_occlusion_count1_low_04; // offset: 398  (0x18E)
0427     uint32_t db_occlusion_count1_hi_04; // offset: 399  (0x18F)
0428     uint32_t db_occlusion_count2_low_04; // offset: 400  (0x190)
0429     uint32_t db_occlusion_count2_hi_04; // offset: 401  (0x191)
0430     uint32_t db_occlusion_count3_low_04; // offset: 402  (0x192)
0431     uint32_t db_occlusion_count3_hi_04; // offset: 403  (0x193)
0432     uint32_t db_occlusion_count0_low_05; // offset: 404  (0x194)
0433     uint32_t db_occlusion_count0_hi_05; // offset: 405  (0x195)
0434     uint32_t db_occlusion_count1_low_05; // offset: 406  (0x196)
0435     uint32_t db_occlusion_count1_hi_05; // offset: 407  (0x197)
0436     uint32_t db_occlusion_count2_low_05; // offset: 408  (0x198)
0437     uint32_t db_occlusion_count2_hi_05; // offset: 409  (0x199)
0438     uint32_t db_occlusion_count3_low_05; // offset: 410  (0x19A)
0439     uint32_t db_occlusion_count3_hi_05; // offset: 411  (0x19B)
0440     uint32_t db_occlusion_count0_low_06; // offset: 412  (0x19C)
0441     uint32_t db_occlusion_count0_hi_06; // offset: 413  (0x19D)
0442     uint32_t db_occlusion_count1_low_06; // offset: 414  (0x19E)
0443     uint32_t db_occlusion_count1_hi_06; // offset: 415  (0x19F)
0444     uint32_t db_occlusion_count2_low_06; // offset: 416  (0x1A0)
0445     uint32_t db_occlusion_count2_hi_06; // offset: 417  (0x1A1)
0446     uint32_t db_occlusion_count3_low_06; // offset: 418  (0x1A2)
0447     uint32_t db_occlusion_count3_hi_06; // offset: 419  (0x1A3)
0448     uint32_t db_occlusion_count0_low_07; // offset: 420  (0x1A4)
0449     uint32_t db_occlusion_count0_hi_07; // offset: 421  (0x1A5)
0450     uint32_t db_occlusion_count1_low_07; // offset: 422  (0x1A6)
0451     uint32_t db_occlusion_count1_hi_07; // offset: 423  (0x1A7)
0452     uint32_t db_occlusion_count2_low_07; // offset: 424  (0x1A8)
0453     uint32_t db_occlusion_count2_hi_07; // offset: 425  (0x1A9)
0454     uint32_t db_occlusion_count3_low_07; // offset: 426  (0x1AA)
0455     uint32_t db_occlusion_count3_hi_07; // offset: 427  (0x1AB)
0456     uint32_t db_occlusion_count0_low_10; // offset: 428  (0x1AC)
0457     uint32_t db_occlusion_count0_hi_10; // offset: 429  (0x1AD)
0458     uint32_t db_occlusion_count1_low_10; // offset: 430  (0x1AE)
0459     uint32_t db_occlusion_count1_hi_10; // offset: 431  (0x1AF)
0460     uint32_t db_occlusion_count2_low_10; // offset: 432  (0x1B0)
0461     uint32_t db_occlusion_count2_hi_10; // offset: 433  (0x1B1)
0462     uint32_t db_occlusion_count3_low_10; // offset: 434  (0x1B2)
0463     uint32_t db_occlusion_count3_hi_10; // offset: 435  (0x1B3)
0464     uint32_t db_occlusion_count0_low_11; // offset: 436  (0x1B4)
0465     uint32_t db_occlusion_count0_hi_11; // offset: 437  (0x1B5)
0466     uint32_t db_occlusion_count1_low_11; // offset: 438  (0x1B6)
0467     uint32_t db_occlusion_count1_hi_11; // offset: 439  (0x1B7)
0468     uint32_t db_occlusion_count2_low_11; // offset: 440  (0x1B8)
0469     uint32_t db_occlusion_count2_hi_11; // offset: 441  (0x1B9)
0470     uint32_t db_occlusion_count3_low_11; // offset: 442  (0x1BA)
0471     uint32_t db_occlusion_count3_hi_11; // offset: 443  (0x1BB)
0472     uint32_t db_occlusion_count0_low_12; // offset: 444  (0x1BC)
0473     uint32_t db_occlusion_count0_hi_12; // offset: 445  (0x1BD)
0474     uint32_t db_occlusion_count1_low_12; // offset: 446  (0x1BE)
0475     uint32_t db_occlusion_count1_hi_12; // offset: 447  (0x1BF)
0476     uint32_t db_occlusion_count2_low_12; // offset: 448  (0x1C0)
0477     uint32_t db_occlusion_count2_hi_12; // offset: 449  (0x1C1)
0478     uint32_t db_occlusion_count3_low_12; // offset: 450  (0x1C2)
0479     uint32_t db_occlusion_count3_hi_12; // offset: 451  (0x1C3)
0480     uint32_t db_occlusion_count0_low_13; // offset: 452  (0x1C4)
0481     uint32_t db_occlusion_count0_hi_13; // offset: 453  (0x1C5)
0482     uint32_t db_occlusion_count1_low_13; // offset: 454  (0x1C6)
0483     uint32_t db_occlusion_count1_hi_13; // offset: 455  (0x1C7)
0484     uint32_t db_occlusion_count2_low_13; // offset: 456  (0x1C8)
0485     uint32_t db_occlusion_count2_hi_13; // offset: 457  (0x1C9)
0486     uint32_t db_occlusion_count3_low_13; // offset: 458  (0x1CA)
0487     uint32_t db_occlusion_count3_hi_13; // offset: 459  (0x1CB)
0488     uint32_t db_occlusion_count0_low_14; // offset: 460  (0x1CC)
0489     uint32_t db_occlusion_count0_hi_14; // offset: 461  (0x1CD)
0490     uint32_t db_occlusion_count1_low_14; // offset: 462  (0x1CE)
0491     uint32_t db_occlusion_count1_hi_14; // offset: 463  (0x1CF)
0492     uint32_t db_occlusion_count2_low_14; // offset: 464  (0x1D0)
0493     uint32_t db_occlusion_count2_hi_14; // offset: 465  (0x1D1)
0494     uint32_t db_occlusion_count3_low_14; // offset: 466  (0x1D2)
0495     uint32_t db_occlusion_count3_hi_14; // offset: 467  (0x1D3)
0496     uint32_t db_occlusion_count0_low_15; // offset: 468  (0x1D4)
0497     uint32_t db_occlusion_count0_hi_15; // offset: 469  (0x1D5)
0498     uint32_t db_occlusion_count1_low_15; // offset: 470  (0x1D6)
0499     uint32_t db_occlusion_count1_hi_15; // offset: 471  (0x1D7)
0500     uint32_t db_occlusion_count2_low_15; // offset: 472  (0x1D8)
0501     uint32_t db_occlusion_count2_hi_15; // offset: 473  (0x1D9)
0502     uint32_t db_occlusion_count3_low_15; // offset: 474  (0x1DA)
0503     uint32_t db_occlusion_count3_hi_15; // offset: 475  (0x1DB)
0504     uint32_t db_occlusion_count0_low_16; // offset: 476  (0x1DC)
0505     uint32_t db_occlusion_count0_hi_16; // offset: 477  (0x1DD)
0506     uint32_t db_occlusion_count1_low_16; // offset: 478  (0x1DE)
0507     uint32_t db_occlusion_count1_hi_16; // offset: 479  (0x1DF)
0508     uint32_t db_occlusion_count2_low_16; // offset: 480  (0x1E0)
0509     uint32_t db_occlusion_count2_hi_16; // offset: 481  (0x1E1)
0510     uint32_t db_occlusion_count3_low_16; // offset: 482  (0x1E2)
0511     uint32_t db_occlusion_count3_hi_16; // offset: 483  (0x1E3)
0512     uint32_t db_occlusion_count0_low_17; // offset: 484  (0x1E4)
0513     uint32_t db_occlusion_count0_hi_17; // offset: 485  (0x1E5)
0514     uint32_t db_occlusion_count1_low_17; // offset: 486  (0x1E6)
0515     uint32_t db_occlusion_count1_hi_17; // offset: 487  (0x1E7)
0516     uint32_t db_occlusion_count2_low_17; // offset: 488  (0x1E8)
0517     uint32_t db_occlusion_count2_hi_17; // offset: 489  (0x1E9)
0518     uint32_t db_occlusion_count3_low_17; // offset: 490  (0x1EA)
0519     uint32_t db_occlusion_count3_hi_17; // offset: 491  (0x1EB)
0520     uint32_t reserved_492; // offset: 492  (0x1EC)
0521     uint32_t reserved_493; // offset: 493  (0x1ED)
0522     uint32_t reserved_494; // offset: 494  (0x1EE)
0523     uint32_t reserved_495; // offset: 495  (0x1EF)
0524     uint32_t reserved_496; // offset: 496  (0x1F0)
0525     uint32_t reserved_497; // offset: 497  (0x1F1)
0526     uint32_t reserved_498; // offset: 498  (0x1F2)
0527     uint32_t reserved_499; // offset: 499  (0x1F3)
0528     uint32_t reserved_500; // offset: 500  (0x1F4)
0529     uint32_t reserved_501; // offset: 501  (0x1F5)
0530     uint32_t reserved_502; // offset: 502  (0x1F6)
0531     uint32_t reserved_503; // offset: 503  (0x1F7)
0532     uint32_t reserved_504; // offset: 504  (0x1F8)
0533     uint32_t reserved_505; // offset: 505  (0x1F9)
0534     uint32_t reserved_506; // offset: 506  (0x1FA)
0535     uint32_t reserved_507; // offset: 507  (0x1FB)
0536     uint32_t reserved_508; // offset: 508  (0x1FC)
0537     uint32_t reserved_509; // offset: 509  (0x1FD)
0538     uint32_t reserved_510; // offset: 510  (0x1FE)
0539     uint32_t reserved_511; // offset: 511  (0x1FF)
0540 };
0541
0542 struct v11_sdma_mqd {
0543     uint32_t sdmax_rlcx_rb_cntl; // offset: 0  (0x0)
0544     uint32_t sdmax_rlcx_rb_base; // offset: 1  (0x1)
0545     uint32_t sdmax_rlcx_rb_base_hi; // offset: 2  (0x2)
0546     uint32_t sdmax_rlcx_rb_rptr; // offset: 3  (0x3)
0547     uint32_t sdmax_rlcx_rb_rptr_hi; // offset: 4  (0x4)
0548     uint32_t sdmax_rlcx_rb_wptr; // offset: 5  (0x5)
0549     uint32_t sdmax_rlcx_rb_wptr_hi; // offset: 6  (0x6)
0550     uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 7  (0x7)
0551     uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 8  (0x8)
0552     uint32_t sdmax_rlcx_ib_cntl; // offset: 9  (0x9)
0553     uint32_t sdmax_rlcx_ib_rptr; // offset: 10  (0xA)
0554     uint32_t sdmax_rlcx_ib_offset; // offset: 11  (0xB)
0555     uint32_t sdmax_rlcx_ib_base_lo; // offset: 12  (0xC)
0556     uint32_t sdmax_rlcx_ib_base_hi; // offset: 13  (0xD)
0557     uint32_t sdmax_rlcx_ib_size; // offset: 14  (0xE)
0558     uint32_t sdmax_rlcx_skip_cntl; // offset: 15  (0xF)
0559     uint32_t sdmax_rlcx_context_status; // offset: 16  (0x10)
0560     uint32_t sdmax_rlcx_doorbell; // offset: 17  (0x11)
0561     uint32_t sdmax_rlcx_doorbell_log; // offset: 18  (0x12)
0562     uint32_t sdmax_rlcx_doorbell_offset; // offset: 19  (0x13)
0563     uint32_t sdmax_rlcx_csa_addr_lo; // offset: 20  (0x14)
0564     uint32_t sdmax_rlcx_csa_addr_hi; // offset: 21  (0x15)
0565     uint32_t sdmax_rlcx_sched_cntl; // offset: 22  (0x16)
0566     uint32_t sdmax_rlcx_ib_sub_remain; // offset: 23  (0x17)
0567     uint32_t sdmax_rlcx_preempt; // offset: 24  (0x18)
0568     uint32_t sdmax_rlcx_dummy_reg; // offset: 25  (0x19)
0569     uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 26  (0x1A)
0570     uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 27  (0x1B)
0571     uint32_t sdmax_rlcx_rb_aql_cntl; // offset: 28  (0x1C)
0572     uint32_t sdmax_rlcx_minor_ptr_update; // offset: 29  (0x1D)
0573     uint32_t sdmax_rlcx_rb_preempt; // offset: 30  (0x1E)
0574     uint32_t sdmax_rlcx_midcmd_data0; // offset: 31  (0x1F)
0575     uint32_t sdmax_rlcx_midcmd_data1; // offset: 32  (0x20)
0576     uint32_t sdmax_rlcx_midcmd_data2; // offset: 33  (0x21)
0577     uint32_t sdmax_rlcx_midcmd_data3; // offset: 34  (0x22)
0578     uint32_t sdmax_rlcx_midcmd_data4; // offset: 35  (0x23)
0579     uint32_t sdmax_rlcx_midcmd_data5; // offset: 36  (0x24)
0580     uint32_t sdmax_rlcx_midcmd_data6; // offset: 37  (0x25)
0581     uint32_t sdmax_rlcx_midcmd_data7; // offset: 38  (0x26)
0582     uint32_t sdmax_rlcx_midcmd_data8; // offset: 39  (0x27)
0583     uint32_t sdmax_rlcx_midcmd_data9; // offset: 40  (0x28)
0584     uint32_t sdmax_rlcx_midcmd_data10; // offset: 41  (0x29)
0585     uint32_t sdmax_rlcx_midcmd_cntl; // offset: 42  (0x2A)
0586     uint32_t sdmax_rlcx_f32_dbg0; // offset: 43  (0x2B)
0587     uint32_t sdmax_rlcx_f32_dbg1; // offset: 44  (0x2C)
0588     uint32_t reserved_45; // offset: 45  (0x2D)
0589     uint32_t reserved_46; // offset: 46  (0x2E)
0590     uint32_t reserved_47; // offset: 47  (0x2F)
0591     uint32_t reserved_48; // offset: 48  (0x30)
0592     uint32_t reserved_49; // offset: 49  (0x31)
0593     uint32_t reserved_50; // offset: 50  (0x32)
0594     uint32_t reserved_51; // offset: 51  (0x33)
0595     uint32_t reserved_52; // offset: 52  (0x34)
0596     uint32_t reserved_53; // offset: 53  (0x35)
0597     uint32_t reserved_54; // offset: 54  (0x36)
0598     uint32_t reserved_55; // offset: 55  (0x37)
0599     uint32_t reserved_56; // offset: 56  (0x38)
0600     uint32_t reserved_57; // offset: 57  (0x39)
0601     uint32_t reserved_58; // offset: 58  (0x3A)
0602     uint32_t reserved_59; // offset: 59  (0x3B)
0603     uint32_t reserved_60; // offset: 60  (0x3C)
0604     uint32_t reserved_61; // offset: 61  (0x3D)
0605     uint32_t reserved_62; // offset: 62  (0x3E)
0606     uint32_t reserved_63; // offset: 63  (0x3F)
0607     uint32_t reserved_64; // offset: 64  (0x40)
0608     uint32_t reserved_65; // offset: 65  (0x41)
0609     uint32_t reserved_66; // offset: 66  (0x42)
0610     uint32_t reserved_67; // offset: 67  (0x43)
0611     uint32_t reserved_68; // offset: 68  (0x44)
0612     uint32_t reserved_69; // offset: 69  (0x45)
0613     uint32_t reserved_70; // offset: 70  (0x46)
0614     uint32_t reserved_71; // offset: 0  (0x47)
0615     uint32_t reserved_72; // offset: 1  (0x48)
0616     uint32_t reserved_73; // offset: 2  (0x49)
0617     uint32_t reserved_74; // offset: 3  (0x4A)
0618     uint32_t reserved_75; // offset: 4  (0x4B)
0619     uint32_t reserved_76; // offset: 5  (0x4C)
0620     uint32_t reserved_77; // offset: 6  (0x4D)
0621     uint32_t reserved_78; // offset: 7  (0x4E)
0622     uint32_t reserved_79; // offset: 79  (0x4F)
0623     uint32_t reserved_80; // offset: 80  (0x50)
0624     uint32_t reserved_81; // offset: 81  (0x51)
0625     uint32_t reserved_82; // offset: 82  (0x52)
0626     uint32_t reserved_83; // offset: 83  (0x53)
0627     uint32_t reserved_84; // offset: 84  (0x54)
0628     uint32_t reserved_85; // offset: 85  (0x55)
0629     uint32_t reserved_86; // offset: 86  (0x56)
0630     uint32_t reserved_87; // offset: 87  (0x57)
0631     uint32_t reserved_88; // offset: 88  (0x58)
0632     uint32_t reserved_89; // offset: 89  (0x59)
0633     uint32_t reserved_90; // offset: 90  (0x5A)
0634     uint32_t reserved_91; // offset: 91  (0x5B)
0635     uint32_t reserved_92; // offset: 92  (0x5C)
0636     uint32_t reserved_93; // offset: 93  (0x5D)
0637     uint32_t reserved_94; // offset: 94  (0x5E)
0638     uint32_t reserved_95; // offset: 95  (0x5F)
0639     uint32_t reserved_96; // offset: 96  (0x60)
0640     uint32_t reserved_97; // offset: 97  (0x61)
0641     uint32_t reserved_98; // offset: 98  (0x62)
0642     uint32_t reserved_99; // offset: 99  (0x63)
0643     uint32_t reserved_100; // offset: 100  (0x64)
0644     uint32_t reserved_101; // offset: 101  (0x65)
0645     uint32_t reserved_102; // offset: 102  (0x66)
0646     uint32_t reserved_103; // offset: 103  (0x67)
0647     uint32_t reserved_104; // offset: 104  (0x68)
0648     uint32_t reserved_105; // offset: 105  (0x69)
0649     uint32_t reserved_106; // offset: 106  (0x6A)
0650     uint32_t reserved_107; // offset: 107  (0x6B)
0651     uint32_t reserved_108; // offset: 108  (0x6C)
0652     uint32_t reserved_109; // offset: 109  (0x6D)
0653     uint32_t reserved_110; // offset: 110  (0x6E)
0654     uint32_t reserved_111; // offset: 111  (0x6F)
0655     uint32_t reserved_112; // offset: 112  (0x70)
0656     uint32_t reserved_113; // offset: 113  (0x71)
0657     uint32_t reserved_114; // offset: 114  (0x72)
0658     uint32_t reserved_115; // offset: 115  (0x73)
0659     uint32_t reserved_116; // offset: 116  (0x74)
0660     uint32_t reserved_117; // offset: 117  (0x75)
0661     uint32_t reserved_118; // offset: 118  (0x76)
0662     uint32_t reserved_119; // offset: 119  (0x77)
0663     uint32_t reserved_120; // offset: 120  (0x78)
0664     uint32_t reserved_121; // offset: 121  (0x79)
0665     uint32_t reserved_122; // offset: 122  (0x7A)
0666     uint32_t reserved_123; // offset: 123  (0x7B)
0667     uint32_t reserved_124; // offset: 124  (0x7C)
0668     uint32_t reserved_125; // offset: 125  (0x7D)
0669     /* reserved_126,127: repurposed for driver-internal use */
0670     uint32_t sdma_engine_id;
0671     uint32_t sdma_queue_id;
0672 };
0673
0674 struct v11_compute_mqd {
0675     uint32_t header; // offset: 0  (0x0)
0676     uint32_t compute_dispatch_initiator; // offset: 1  (0x1)
0677     uint32_t compute_dim_x; // offset: 2  (0x2)
0678     uint32_t compute_dim_y; // offset: 3  (0x3)
0679     uint32_t compute_dim_z; // offset: 4  (0x4)
0680     uint32_t compute_start_x; // offset: 5  (0x5)
0681     uint32_t compute_start_y; // offset: 6  (0x6)
0682     uint32_t compute_start_z; // offset: 7  (0x7)
0683     uint32_t compute_num_thread_x; // offset: 8  (0x8)
0684     uint32_t compute_num_thread_y; // offset: 9  (0x9)
0685     uint32_t compute_num_thread_z; // offset: 10  (0xA)
0686     uint32_t compute_pipelinestat_enable; // offset: 11  (0xB)
0687     uint32_t compute_perfcount_enable; // offset: 12  (0xC)
0688     uint32_t compute_pgm_lo; // offset: 13  (0xD)
0689     uint32_t compute_pgm_hi; // offset: 14  (0xE)
0690     uint32_t compute_dispatch_pkt_addr_lo; // offset: 15  (0xF)
0691     uint32_t compute_dispatch_pkt_addr_hi; // offset: 16  (0x10)
0692     uint32_t compute_dispatch_scratch_base_lo; // offset: 17  (0x11)
0693     uint32_t compute_dispatch_scratch_base_hi; // offset: 18  (0x12)
0694     uint32_t compute_pgm_rsrc1; // offset: 19  (0x13)
0695     uint32_t compute_pgm_rsrc2; // offset: 20  (0x14)
0696     uint32_t compute_vmid; // offset: 21  (0x15)
0697     uint32_t compute_resource_limits; // offset: 22  (0x16)
0698     uint32_t compute_static_thread_mgmt_se0; // offset: 23  (0x17)
0699     uint32_t compute_static_thread_mgmt_se1; // offset: 24  (0x18)
0700     uint32_t compute_tmpring_size; // offset: 25  (0x19)
0701     uint32_t compute_static_thread_mgmt_se2; // offset: 26  (0x1A)
0702     uint32_t compute_static_thread_mgmt_se3; // offset: 27  (0x1B)
0703     uint32_t compute_restart_x; // offset: 28  (0x1C)
0704     uint32_t compute_restart_y; // offset: 29  (0x1D)
0705     uint32_t compute_restart_z; // offset: 30  (0x1E)
0706     uint32_t compute_thread_trace_enable; // offset: 31  (0x1F)
0707     uint32_t compute_misc_reserved; // offset: 32  (0x20)
0708     uint32_t compute_dispatch_id; // offset: 33  (0x21)
0709     uint32_t compute_threadgroup_id; // offset: 34  (0x22)
0710     uint32_t compute_req_ctrl; // offset: 35  (0x23)
0711     uint32_t reserved_36; // offset: 36  (0x24)
0712     uint32_t compute_user_accum_0; // offset: 37  (0x25)
0713     uint32_t compute_user_accum_1; // offset: 38  (0x26)
0714     uint32_t compute_user_accum_2; // offset: 39  (0x27)
0715     uint32_t compute_user_accum_3; // offset: 40  (0x28)
0716     uint32_t compute_pgm_rsrc3; // offset: 41  (0x29)
0717     uint32_t compute_ddid_index; // offset: 42  (0x2A)
0718     uint32_t compute_shader_chksum; // offset: 43  (0x2B)
0719     uint32_t compute_static_thread_mgmt_se4; // offset: 44  (0x2C)
0720     uint32_t compute_static_thread_mgmt_se5; // offset: 45  (0x2D)
0721     uint32_t compute_static_thread_mgmt_se6; // offset: 46  (0x2E)
0722     uint32_t compute_static_thread_mgmt_se7; // offset: 47  (0x2F)
0723     uint32_t compute_dispatch_interleave; // offset: 48  (0x30)
0724     uint32_t compute_relaunch; // offset: 49  (0x31)
0725     uint32_t compute_wave_restore_addr_lo; // offset: 50  (0x32)
0726     uint32_t compute_wave_restore_addr_hi; // offset: 51  (0x33)
0727     uint32_t compute_wave_restore_control; // offset: 52  (0x34)
0728     uint32_t reserved_53; // offset: 53  (0x35)
0729     uint32_t reserved_54; // offset: 54  (0x36)
0730     uint32_t reserved_55; // offset: 55  (0x37)
0731     uint32_t reserved_56; // offset: 56  (0x38)
0732     uint32_t reserved_57; // offset: 57  (0x39)
0733     uint32_t reserved_58; // offset: 58  (0x3A)
0734     uint32_t reserved_59; // offset: 59  (0x3B)
0735     uint32_t reserved_60; // offset: 60  (0x3C)
0736     uint32_t reserved_61; // offset: 61  (0x3D)
0737     uint32_t reserved_62; // offset: 62  (0x3E)
0738     uint32_t reserved_63; // offset: 63  (0x3F)
0739     uint32_t reserved_64; // offset: 64  (0x40)
0740     uint32_t compute_user_data_0; // offset: 65  (0x41)
0741     uint32_t compute_user_data_1; // offset: 66  (0x42)
0742     uint32_t compute_user_data_2; // offset: 67  (0x43)
0743     uint32_t compute_user_data_3; // offset: 68  (0x44)
0744     uint32_t compute_user_data_4; // offset: 69  (0x45)
0745     uint32_t compute_user_data_5; // offset: 70  (0x46)
0746     uint32_t compute_user_data_6; // offset: 71  (0x47)
0747     uint32_t compute_user_data_7; // offset: 72  (0x48)
0748     uint32_t compute_user_data_8; // offset: 73  (0x49)
0749     uint32_t compute_user_data_9; // offset: 74  (0x4A)
0750     uint32_t compute_user_data_10; // offset: 75  (0x4B)
0751     uint32_t compute_user_data_11; // offset: 76  (0x4C)
0752     uint32_t compute_user_data_12; // offset: 77  (0x4D)
0753     uint32_t compute_user_data_13; // offset: 78  (0x4E)
0754     uint32_t compute_user_data_14; // offset: 79  (0x4F)
0755     uint32_t compute_user_data_15; // offset: 80  (0x50)
0756     uint32_t cp_compute_csinvoc_count_lo; // offset: 81  (0x51)
0757     uint32_t cp_compute_csinvoc_count_hi; // offset: 82  (0x52)
0758     uint32_t reserved_83; // offset: 83  (0x53)
0759     uint32_t reserved_84; // offset: 84  (0x54)
0760     uint32_t reserved_85; // offset: 85  (0x55)
0761     uint32_t cp_mqd_query_time_lo; // offset: 86  (0x56)
0762     uint32_t cp_mqd_query_time_hi; // offset: 87  (0x57)
0763     uint32_t cp_mqd_connect_start_time_lo; // offset: 88  (0x58)
0764     uint32_t cp_mqd_connect_start_time_hi; // offset: 89  (0x59)
0765     uint32_t cp_mqd_connect_end_time_lo; // offset: 90  (0x5A)
0766     uint32_t cp_mqd_connect_end_time_hi; // offset: 91  (0x5B)
0767     uint32_t cp_mqd_connect_end_wf_count; // offset: 92  (0x5C)
0768     uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93  (0x5D)
0769     uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94  (0x5E)
0770     uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95  (0x5F)
0771     uint32_t cp_mqd_readindex_lo; // offset: 96  (0x60)
0772     uint32_t cp_mqd_readindex_hi; // offset: 97  (0x61)
0773     uint32_t cp_mqd_save_start_time_lo; // offset: 98  (0x62)
0774     uint32_t cp_mqd_save_start_time_hi; // offset: 99  (0x63)
0775     uint32_t cp_mqd_save_end_time_lo; // offset: 100  (0x64)
0776     uint32_t cp_mqd_save_end_time_hi; // offset: 101  (0x65)
0777     uint32_t cp_mqd_restore_start_time_lo; // offset: 102  (0x66)
0778     uint32_t cp_mqd_restore_start_time_hi; // offset: 103  (0x67)
0779     uint32_t cp_mqd_restore_end_time_lo; // offset: 104  (0x68)
0780     uint32_t cp_mqd_restore_end_time_hi; // offset: 105  (0x69)
0781     uint32_t disable_queue; // offset: 106  (0x6A)
0782     uint32_t reserved_107; // offset: 107  (0x6B)
0783     uint32_t gds_cs_ctxsw_cnt0; // offset: 108  (0x6C)
0784     uint32_t gds_cs_ctxsw_cnt1; // offset: 109  (0x6D)
0785     uint32_t gds_cs_ctxsw_cnt2; // offset: 110  (0x6E)
0786     uint32_t gds_cs_ctxsw_cnt3; // offset: 111  (0x6F)
0787     uint32_t reserved_112; // offset: 112  (0x70)
0788     uint32_t reserved_113; // offset: 113  (0x71)
0789     uint32_t cp_pq_exe_status_lo; // offset: 114  (0x72)
0790     uint32_t cp_pq_exe_status_hi; // offset: 115  (0x73)
0791     uint32_t cp_packet_id_lo; // offset: 116  (0x74)
0792     uint32_t cp_packet_id_hi; // offset: 117  (0x75)
0793     uint32_t cp_packet_exe_status_lo; // offset: 118  (0x76)
0794     uint32_t cp_packet_exe_status_hi; // offset: 119  (0x77)
0795     uint32_t gds_save_base_addr_lo; // offset: 120  (0x78)
0796     uint32_t gds_save_base_addr_hi; // offset: 121  (0x79)
0797     uint32_t gds_save_mask_lo; // offset: 122  (0x7A)
0798     uint32_t gds_save_mask_hi; // offset: 123  (0x7B)
0799     uint32_t ctx_save_base_addr_lo; // offset: 124  (0x7C)
0800     uint32_t ctx_save_base_addr_hi; // offset: 125  (0x7D)
0801     uint32_t reserved_126; // offset: 126  (0x7E)
0802     uint32_t reserved_127; // offset: 127  (0x7F)
0803     uint32_t cp_mqd_base_addr_lo; // offset: 128  (0x80)
0804     uint32_t cp_mqd_base_addr_hi; // offset: 129  (0x81)
0805     uint32_t cp_hqd_active; // offset: 130  (0x82)
0806     uint32_t cp_hqd_vmid; // offset: 131  (0x83)
0807     uint32_t cp_hqd_persistent_state; // offset: 132  (0x84)
0808     uint32_t cp_hqd_pipe_priority; // offset: 133  (0x85)
0809     uint32_t cp_hqd_queue_priority; // offset: 134  (0x86)
0810     uint32_t cp_hqd_quantum; // offset: 135  (0x87)
0811     uint32_t cp_hqd_pq_base_lo; // offset: 136  (0x88)
0812     uint32_t cp_hqd_pq_base_hi; // offset: 137  (0x89)
0813     uint32_t cp_hqd_pq_rptr; // offset: 138  (0x8A)
0814     uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139  (0x8B)
0815     uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140  (0x8C)
0816     uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141  (0x8D)
0817     uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142  (0x8E)
0818     uint32_t cp_hqd_pq_doorbell_control; // offset: 143  (0x8F)
0819     uint32_t reserved_144; // offset: 144  (0x90)
0820     uint32_t cp_hqd_pq_control; // offset: 145  (0x91)
0821     uint32_t cp_hqd_ib_base_addr_lo; // offset: 146  (0x92)
0822     uint32_t cp_hqd_ib_base_addr_hi; // offset: 147  (0x93)
0823     uint32_t cp_hqd_ib_rptr; // offset: 148  (0x94)
0824     uint32_t cp_hqd_ib_control; // offset: 149  (0x95)
0825     uint32_t cp_hqd_iq_timer; // offset: 150  (0x96)
0826     uint32_t cp_hqd_iq_rptr; // offset: 151  (0x97)
0827     uint32_t cp_hqd_dequeue_request; // offset: 152  (0x98)
0828     uint32_t cp_hqd_dma_offload; // offset: 153  (0x99)
0829     uint32_t cp_hqd_sema_cmd; // offset: 154  (0x9A)
0830     uint32_t cp_hqd_msg_type; // offset: 155  (0x9B)
0831     uint32_t cp_hqd_atomic0_preop_lo; // offset: 156  (0x9C)
0832     uint32_t cp_hqd_atomic0_preop_hi; // offset: 157  (0x9D)
0833     uint32_t cp_hqd_atomic1_preop_lo; // offset: 158  (0x9E)
0834     uint32_t cp_hqd_atomic1_preop_hi; // offset: 159  (0x9F)
0835     uint32_t cp_hqd_hq_status0; // offset: 160  (0xA0)
0836     uint32_t cp_hqd_hq_control0; // offset: 161  (0xA1)
0837     uint32_t cp_mqd_control; // offset: 162  (0xA2)
0838     uint32_t cp_hqd_hq_status1; // offset: 163  (0xA3)
0839     uint32_t cp_hqd_hq_control1; // offset: 164  (0xA4)
0840     uint32_t cp_hqd_eop_base_addr_lo; // offset: 165  (0xA5)
0841     uint32_t cp_hqd_eop_base_addr_hi; // offset: 166  (0xA6)
0842     uint32_t cp_hqd_eop_control; // offset: 167  (0xA7)
0843     uint32_t cp_hqd_eop_rptr; // offset: 168  (0xA8)
0844     uint32_t cp_hqd_eop_wptr; // offset: 169  (0xA9)
0845     uint32_t cp_hqd_eop_done_events; // offset: 170  (0xAA)
0846     uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171  (0xAB)
0847     uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172  (0xAC)
0848     uint32_t cp_hqd_ctx_save_control; // offset: 173  (0xAD)
0849     uint32_t cp_hqd_cntl_stack_offset; // offset: 174  (0xAE)
0850     uint32_t cp_hqd_cntl_stack_size; // offset: 175  (0xAF)
0851     uint32_t cp_hqd_wg_state_offset; // offset: 176  (0xB0)
0852     uint32_t cp_hqd_ctx_save_size; // offset: 177  (0xB1)
0853     uint32_t cp_hqd_gds_resource_state; // offset: 178  (0xB2)
0854     uint32_t cp_hqd_error; // offset: 179  (0xB3)
0855     uint32_t cp_hqd_eop_wptr_mem; // offset: 180  (0xB4)
0856     uint32_t cp_hqd_aql_control; // offset: 181  (0xB5)
0857     uint32_t cp_hqd_pq_wptr_lo; // offset: 182  (0xB6)
0858     uint32_t cp_hqd_pq_wptr_hi; // offset: 183  (0xB7)
0859     uint32_t reserved_184; // offset: 184  (0xB8)
0860     uint32_t reserved_185; // offset: 185  (0xB9)
0861     uint32_t reserved_186; // offset: 186  (0xBA)
0862     uint32_t reserved_187; // offset: 187  (0xBB)
0863     uint32_t reserved_188; // offset: 188  (0xBC)
0864     uint32_t reserved_189; // offset: 189  (0xBD)
0865     uint32_t reserved_190; // offset: 190  (0xBE)
0866     uint32_t reserved_191; // offset: 191  (0xBF)
0867     uint32_t iqtimer_pkt_header; // offset: 192  (0xC0)
0868     uint32_t iqtimer_pkt_dw0; // offset: 193  (0xC1)
0869     uint32_t iqtimer_pkt_dw1; // offset: 194  (0xC2)
0870     uint32_t iqtimer_pkt_dw2; // offset: 195  (0xC3)
0871     uint32_t iqtimer_pkt_dw3; // offset: 196  (0xC4)
0872     uint32_t iqtimer_pkt_dw4; // offset: 197  (0xC5)
0873     uint32_t iqtimer_pkt_dw5; // offset: 198  (0xC6)
0874     uint32_t iqtimer_pkt_dw6; // offset: 199  (0xC7)
0875     uint32_t iqtimer_pkt_dw7; // offset: 200  (0xC8)
0876     uint32_t iqtimer_pkt_dw8; // offset: 201  (0xC9)
0877     uint32_t iqtimer_pkt_dw9; // offset: 202  (0xCA)
0878     uint32_t iqtimer_pkt_dw10; // offset: 203  (0xCB)
0879     uint32_t iqtimer_pkt_dw11; // offset: 204  (0xCC)
0880     uint32_t iqtimer_pkt_dw12; // offset: 205  (0xCD)
0881     uint32_t iqtimer_pkt_dw13; // offset: 206  (0xCE)
0882     uint32_t iqtimer_pkt_dw14; // offset: 207  (0xCF)
0883     uint32_t iqtimer_pkt_dw15; // offset: 208  (0xD0)
0884     uint32_t iqtimer_pkt_dw16; // offset: 209  (0xD1)
0885     uint32_t iqtimer_pkt_dw17; // offset: 210  (0xD2)
0886     uint32_t iqtimer_pkt_dw18; // offset: 211  (0xD3)
0887     uint32_t iqtimer_pkt_dw19; // offset: 212  (0xD4)
0888     uint32_t iqtimer_pkt_dw20; // offset: 213  (0xD5)
0889     uint32_t iqtimer_pkt_dw21; // offset: 214  (0xD6)
0890     uint32_t iqtimer_pkt_dw22; // offset: 215  (0xD7)
0891     uint32_t iqtimer_pkt_dw23; // offset: 216  (0xD8)
0892     uint32_t iqtimer_pkt_dw24; // offset: 217  (0xD9)
0893     uint32_t iqtimer_pkt_dw25; // offset: 218  (0xDA)
0894     uint32_t iqtimer_pkt_dw26; // offset: 219  (0xDB)
0895     uint32_t iqtimer_pkt_dw27; // offset: 220  (0xDC)
0896     uint32_t iqtimer_pkt_dw28; // offset: 221  (0xDD)
0897     uint32_t iqtimer_pkt_dw29; // offset: 222  (0xDE)
0898     uint32_t iqtimer_pkt_dw30; // offset: 223  (0xDF)
0899     uint32_t iqtimer_pkt_dw31; // offset: 224  (0xE0)
0900     uint32_t reserved_225; // offset: 225  (0xE1)
0901     uint32_t reserved_226; // offset: 226  (0xE2)
0902     uint32_t reserved_227; // offset: 227  (0xE3)
0903     uint32_t set_resources_header; // offset: 228  (0xE4)
0904     uint32_t set_resources_dw1; // offset: 229  (0xE5)
0905     uint32_t set_resources_dw2; // offset: 230  (0xE6)
0906     uint32_t set_resources_dw3; // offset: 231  (0xE7)
0907     uint32_t set_resources_dw4; // offset: 232  (0xE8)
0908     uint32_t set_resources_dw5; // offset: 233  (0xE9)
0909     uint32_t set_resources_dw6; // offset: 234  (0xEA)
0910     uint32_t set_resources_dw7; // offset: 235  (0xEB)
0911     uint32_t reserved_236; // offset: 236  (0xEC)
0912     uint32_t reserved_237; // offset: 237  (0xED)
0913     uint32_t reserved_238; // offset: 238  (0xEE)
0914     uint32_t reserved_239; // offset: 239  (0xEF)
0915     uint32_t queue_doorbell_id0; // offset: 240  (0xF0)
0916     uint32_t queue_doorbell_id1; // offset: 241  (0xF1)
0917     uint32_t queue_doorbell_id2; // offset: 242  (0xF2)
0918     uint32_t queue_doorbell_id3; // offset: 243  (0xF3)
0919     uint32_t queue_doorbell_id4; // offset: 244  (0xF4)
0920     uint32_t queue_doorbell_id5; // offset: 245  (0xF5)
0921     uint32_t queue_doorbell_id6; // offset: 246  (0xF6)
0922     uint32_t queue_doorbell_id7; // offset: 247  (0xF7)
0923     uint32_t queue_doorbell_id8; // offset: 248  (0xF8)
0924     uint32_t queue_doorbell_id9; // offset: 249  (0xF9)
0925     uint32_t queue_doorbell_id10; // offset: 250  (0xFA)
0926     uint32_t queue_doorbell_id11; // offset: 251  (0xFB)
0927     uint32_t queue_doorbell_id12; // offset: 252  (0xFC)
0928     uint32_t queue_doorbell_id13; // offset: 253  (0xFD)
0929     uint32_t queue_doorbell_id14; // offset: 254  (0xFE)
0930     uint32_t queue_doorbell_id15; // offset: 255  (0xFF)
0931     uint32_t control_buf_addr_lo; // offset: 256  (0x100)
0932     uint32_t control_buf_addr_hi; // offset: 257  (0x101)
0933     uint32_t control_buf_wptr_lo; // offset: 258  (0x102)
0934     uint32_t control_buf_wptr_hi; // offset: 259  (0x103)
0935     uint32_t control_buf_dptr_lo; // offset: 260  (0x104)
0936     uint32_t control_buf_dptr_hi; // offset: 261  (0x105)
0937     uint32_t control_buf_num_entries; // offset: 262  (0x106)
0938     uint32_t draw_ring_addr_lo; // offset: 263  (0x107)
0939     uint32_t draw_ring_addr_hi; // offset: 264  (0x108)
0940     uint32_t reserved_265; // offset: 265  (0x109)
0941     uint32_t reserved_266; // offset: 266  (0x10A)
0942     uint32_t reserved_267; // offset: 267  (0x10B)
0943     uint32_t reserved_268; // offset: 268  (0x10C)
0944     uint32_t reserved_269; // offset: 269  (0x10D)
0945     uint32_t reserved_270; // offset: 270  (0x10E)
0946     uint32_t reserved_271; // offset: 271  (0x10F)
0947     uint32_t reserved_272; // offset: 272  (0x110)
0948     uint32_t reserved_273; // offset: 273  (0x111)
0949     uint32_t reserved_274; // offset: 274  (0x112)
0950     uint32_t reserved_275; // offset: 275  (0x113)
0951     uint32_t reserved_276; // offset: 276  (0x114)
0952     uint32_t reserved_277; // offset: 277  (0x115)
0953     uint32_t reserved_278; // offset: 278  (0x116)
0954     uint32_t reserved_279; // offset: 279  (0x117)
0955     uint32_t reserved_280; // offset: 280  (0x118)
0956     uint32_t reserved_281; // offset: 281  (0x119)
0957     uint32_t reserved_282; // offset: 282  (0x11A)
0958     uint32_t reserved_283; // offset: 283  (0x11B)
0959     uint32_t reserved_284; // offset: 284  (0x11C)
0960     uint32_t reserved_285; // offset: 285  (0x11D)
0961     uint32_t reserved_286; // offset: 286  (0x11E)
0962     uint32_t reserved_287; // offset: 287  (0x11F)
0963     uint32_t reserved_288; // offset: 288  (0x120)
0964     uint32_t reserved_289; // offset: 289  (0x121)
0965     uint32_t reserved_290; // offset: 290  (0x122)
0966     uint32_t reserved_291; // offset: 291  (0x123)
0967     uint32_t reserved_292; // offset: 292  (0x124)
0968     uint32_t reserved_293; // offset: 293  (0x125)
0969     uint32_t reserved_294; // offset: 294  (0x126)
0970     uint32_t reserved_295; // offset: 295  (0x127)
0971     uint32_t reserved_296; // offset: 296  (0x128)
0972     uint32_t reserved_297; // offset: 297  (0x129)
0973     uint32_t reserved_298; // offset: 298  (0x12A)
0974     uint32_t reserved_299; // offset: 299  (0x12B)
0975     uint32_t reserved_300; // offset: 300  (0x12C)
0976     uint32_t reserved_301; // offset: 301  (0x12D)
0977     uint32_t reserved_302; // offset: 302  (0x12E)
0978     uint32_t reserved_303; // offset: 303  (0x12F)
0979     uint32_t reserved_304; // offset: 304  (0x130)
0980     uint32_t reserved_305; // offset: 305  (0x131)
0981     uint32_t reserved_306; // offset: 306  (0x132)
0982     uint32_t reserved_307; // offset: 307  (0x133)
0983     uint32_t reserved_308; // offset: 308  (0x134)
0984     uint32_t reserved_309; // offset: 309  (0x135)
0985     uint32_t reserved_310; // offset: 310  (0x136)
0986     uint32_t reserved_311; // offset: 311  (0x137)
0987     uint32_t reserved_312; // offset: 312  (0x138)
0988     uint32_t reserved_313; // offset: 313  (0x139)
0989     uint32_t reserved_314; // offset: 314  (0x13A)
0990     uint32_t reserved_315; // offset: 315  (0x13B)
0991     uint32_t reserved_316; // offset: 316  (0x13C)
0992     uint32_t reserved_317; // offset: 317  (0x13D)
0993     uint32_t reserved_318; // offset: 318  (0x13E)
0994     uint32_t reserved_319; // offset: 319  (0x13F)
0995     uint32_t reserved_320; // offset: 320  (0x140)
0996     uint32_t reserved_321; // offset: 321  (0x141)
0997     uint32_t reserved_322; // offset: 322  (0x142)
0998     uint32_t reserved_323; // offset: 323  (0x143)
0999     uint32_t reserved_324; // offset: 324  (0x144)
1000     uint32_t reserved_325; // offset: 325  (0x145)
1001     uint32_t reserved_326; // offset: 326  (0x146)
1002     uint32_t reserved_327; // offset: 327  (0x147)
1003     uint32_t reserved_328; // offset: 328  (0x148)
1004     uint32_t reserved_329; // offset: 329  (0x149)
1005     uint32_t reserved_330; // offset: 330  (0x14A)
1006     uint32_t reserved_331; // offset: 331  (0x14B)
1007     uint32_t reserved_332; // offset: 332  (0x14C)
1008     uint32_t reserved_333; // offset: 333  (0x14D)
1009     uint32_t reserved_334; // offset: 334  (0x14E)
1010     uint32_t reserved_335; // offset: 335  (0x14F)
1011     uint32_t reserved_336; // offset: 336  (0x150)
1012     uint32_t reserved_337; // offset: 337  (0x151)
1013     uint32_t reserved_338; // offset: 338  (0x152)
1014     uint32_t reserved_339; // offset: 339  (0x153)
1015     uint32_t reserved_340; // offset: 340  (0x154)
1016     uint32_t reserved_341; // offset: 341  (0x155)
1017     uint32_t reserved_342; // offset: 342  (0x156)
1018     uint32_t reserved_343; // offset: 343  (0x157)
1019     uint32_t reserved_344; // offset: 344  (0x158)
1020     uint32_t reserved_345; // offset: 345  (0x159)
1021     uint32_t reserved_346; // offset: 346  (0x15A)
1022     uint32_t reserved_347; // offset: 347  (0x15B)
1023     uint32_t reserved_348; // offset: 348  (0x15C)
1024     uint32_t reserved_349; // offset: 349  (0x15D)
1025     uint32_t reserved_350; // offset: 350  (0x15E)
1026     uint32_t reserved_351; // offset: 351  (0x15F)
1027     uint32_t reserved_352; // offset: 352  (0x160)
1028     uint32_t reserved_353; // offset: 353  (0x161)
1029     uint32_t reserved_354; // offset: 354  (0x162)
1030     uint32_t reserved_355; // offset: 355  (0x163)
1031     uint32_t reserved_356; // offset: 356  (0x164)
1032     uint32_t reserved_357; // offset: 357  (0x165)
1033     uint32_t reserved_358; // offset: 358  (0x166)
1034     uint32_t reserved_359; // offset: 359  (0x167)
1035     uint32_t reserved_360; // offset: 360  (0x168)
1036     uint32_t reserved_361; // offset: 361  (0x169)
1037     uint32_t reserved_362; // offset: 362  (0x16A)
1038     uint32_t reserved_363; // offset: 363  (0x16B)
1039     uint32_t reserved_364; // offset: 364  (0x16C)
1040     uint32_t reserved_365; // offset: 365  (0x16D)
1041     uint32_t reserved_366; // offset: 366  (0x16E)
1042     uint32_t reserved_367; // offset: 367  (0x16F)
1043     uint32_t reserved_368; // offset: 368  (0x170)
1044     uint32_t reserved_369; // offset: 369  (0x171)
1045     uint32_t reserved_370; // offset: 370  (0x172)
1046     uint32_t reserved_371; // offset: 371  (0x173)
1047     uint32_t reserved_372; // offset: 372  (0x174)
1048     uint32_t reserved_373; // offset: 373  (0x175)
1049     uint32_t reserved_374; // offset: 374  (0x176)
1050     uint32_t reserved_375; // offset: 375  (0x177)
1051     uint32_t reserved_376; // offset: 376  (0x178)
1052     uint32_t reserved_377; // offset: 377  (0x179)
1053     uint32_t reserved_378; // offset: 378  (0x17A)
1054     uint32_t reserved_379; // offset: 379  (0x17B)
1055     uint32_t reserved_380; // offset: 380  (0x17C)
1056     uint32_t reserved_381; // offset: 381  (0x17D)
1057     uint32_t reserved_382; // offset: 382  (0x17E)
1058     uint32_t reserved_383; // offset: 383  (0x17F)
1059     uint32_t reserved_384; // offset: 384  (0x180)
1060     uint32_t reserved_385; // offset: 385  (0x181)
1061     uint32_t reserved_386; // offset: 386  (0x182)
1062     uint32_t reserved_387; // offset: 387  (0x183)
1063     uint32_t reserved_388; // offset: 388  (0x184)
1064     uint32_t reserved_389; // offset: 389  (0x185)
1065     uint32_t reserved_390; // offset: 390  (0x186)
1066     uint32_t reserved_391; // offset: 391  (0x187)
1067     uint32_t reserved_392; // offset: 392  (0x188)
1068     uint32_t reserved_393; // offset: 393  (0x189)
1069     uint32_t reserved_394; // offset: 394  (0x18A)
1070     uint32_t reserved_395; // offset: 395  (0x18B)
1071     uint32_t reserved_396; // offset: 396  (0x18C)
1072     uint32_t reserved_397; // offset: 397  (0x18D)
1073     uint32_t reserved_398; // offset: 398  (0x18E)
1074     uint32_t reserved_399; // offset: 399  (0x18F)
1075     uint32_t reserved_400; // offset: 400  (0x190)
1076     uint32_t reserved_401; // offset: 401  (0x191)
1077     uint32_t reserved_402; // offset: 402  (0x192)
1078     uint32_t reserved_403; // offset: 403  (0x193)
1079     uint32_t reserved_404; // offset: 404  (0x194)
1080     uint32_t reserved_405; // offset: 405  (0x195)
1081     uint32_t reserved_406; // offset: 406  (0x196)
1082     uint32_t reserved_407; // offset: 407  (0x197)
1083     uint32_t reserved_408; // offset: 408  (0x198)
1084     uint32_t reserved_409; // offset: 409  (0x199)
1085     uint32_t reserved_410; // offset: 410  (0x19A)
1086     uint32_t reserved_411; // offset: 411  (0x19B)
1087     uint32_t reserved_412; // offset: 412  (0x19C)
1088     uint32_t reserved_413; // offset: 413  (0x19D)
1089     uint32_t reserved_414; // offset: 414  (0x19E)
1090     uint32_t reserved_415; // offset: 415  (0x19F)
1091     uint32_t reserved_416; // offset: 416  (0x1A0)
1092     uint32_t reserved_417; // offset: 417  (0x1A1)
1093     uint32_t reserved_418; // offset: 418  (0x1A2)
1094     uint32_t reserved_419; // offset: 419  (0x1A3)
1095     uint32_t reserved_420; // offset: 420  (0x1A4)
1096     uint32_t reserved_421; // offset: 421  (0x1A5)
1097     uint32_t reserved_422; // offset: 422  (0x1A6)
1098     uint32_t reserved_423; // offset: 423  (0x1A7)
1099     uint32_t reserved_424; // offset: 424  (0x1A8)
1100     uint32_t reserved_425; // offset: 425  (0x1A9)
1101     uint32_t reserved_426; // offset: 426  (0x1AA)
1102     uint32_t reserved_427; // offset: 427  (0x1AB)
1103     uint32_t reserved_428; // offset: 428  (0x1AC)
1104     uint32_t reserved_429; // offset: 429  (0x1AD)
1105     uint32_t reserved_430; // offset: 430  (0x1AE)
1106     uint32_t reserved_431; // offset: 431  (0x1AF)
1107     uint32_t reserved_432; // offset: 432  (0x1B0)
1108     uint32_t reserved_433; // offset: 433  (0x1B1)
1109     uint32_t reserved_434; // offset: 434  (0x1B2)
1110     uint32_t reserved_435; // offset: 435  (0x1B3)
1111     uint32_t reserved_436; // offset: 436  (0x1B4)
1112     uint32_t reserved_437; // offset: 437  (0x1B5)
1113     uint32_t reserved_438; // offset: 438  (0x1B6)
1114     uint32_t reserved_439; // offset: 439  (0x1B7)
1115     uint32_t reserved_440; // offset: 440  (0x1B8)
1116     uint32_t reserved_441; // offset: 441  (0x1B9)
1117     uint32_t reserved_442; // offset: 442  (0x1BA)
1118     uint32_t reserved_443; // offset: 443  (0x1BB)
1119     uint32_t reserved_444; // offset: 444  (0x1BC)
1120     uint32_t reserved_445; // offset: 445  (0x1BD)
1121     uint32_t reserved_446; // offset: 446  (0x1BE)
1122     uint32_t reserved_447; // offset: 447  (0x1BF)
1123     uint32_t gws_0_val; // offset: 448  (0x1C0)
1124     uint32_t gws_1_val; // offset: 449  (0x1C1)
1125     uint32_t gws_2_val; // offset: 450  (0x1C2)
1126     uint32_t gws_3_val; // offset: 451  (0x1C3)
1127     uint32_t gws_4_val; // offset: 452  (0x1C4)
1128     uint32_t gws_5_val; // offset: 453  (0x1C5)
1129     uint32_t gws_6_val; // offset: 454  (0x1C6)
1130     uint32_t gws_7_val; // offset: 455  (0x1C7)
1131     uint32_t gws_8_val; // offset: 456  (0x1C8)
1132     uint32_t gws_9_val; // offset: 457  (0x1C9)
1133     uint32_t gws_10_val; // offset: 458  (0x1CA)
1134     uint32_t gws_11_val; // offset: 459  (0x1CB)
1135     uint32_t gws_12_val; // offset: 460  (0x1CC)
1136     uint32_t gws_13_val; // offset: 461  (0x1CD)
1137     uint32_t gws_14_val; // offset: 462  (0x1CE)
1138     uint32_t gws_15_val; // offset: 463  (0x1CF)
1139     uint32_t gws_16_val; // offset: 464  (0x1D0)
1140     uint32_t gws_17_val; // offset: 465  (0x1D1)
1141     uint32_t gws_18_val; // offset: 466  (0x1D2)
1142     uint32_t gws_19_val; // offset: 467  (0x1D3)
1143     uint32_t gws_20_val; // offset: 468  (0x1D4)
1144     uint32_t gws_21_val; // offset: 469  (0x1D5)
1145     uint32_t gws_22_val; // offset: 470  (0x1D6)
1146     uint32_t gws_23_val; // offset: 471  (0x1D7)
1147     uint32_t gws_24_val; // offset: 472  (0x1D8)
1148     uint32_t gws_25_val; // offset: 473  (0x1D9)
1149     uint32_t gws_26_val; // offset: 474  (0x1DA)
1150     uint32_t gws_27_val; // offset: 475  (0x1DB)
1151     uint32_t gws_28_val; // offset: 476  (0x1DC)
1152     uint32_t gws_29_val; // offset: 477  (0x1DD)
1153     uint32_t gws_30_val; // offset: 478  (0x1DE)
1154     uint32_t gws_31_val; // offset: 479  (0x1DF)
1155     uint32_t gws_32_val; // offset: 480  (0x1E0)
1156     uint32_t gws_33_val; // offset: 481  (0x1E1)
1157     uint32_t gws_34_val; // offset: 482  (0x1E2)
1158     uint32_t gws_35_val; // offset: 483  (0x1E3)
1159     uint32_t gws_36_val; // offset: 484  (0x1E4)
1160     uint32_t gws_37_val; // offset: 485  (0x1E5)
1161     uint32_t gws_38_val; // offset: 486  (0x1E6)
1162     uint32_t gws_39_val; // offset: 487  (0x1E7)
1163     uint32_t gws_40_val; // offset: 488  (0x1E8)
1164     uint32_t gws_41_val; // offset: 489  (0x1E9)
1165     uint32_t gws_42_val; // offset: 490  (0x1EA)
1166     uint32_t gws_43_val; // offset: 491  (0x1EB)
1167     uint32_t gws_44_val; // offset: 492  (0x1EC)
1168     uint32_t gws_45_val; // offset: 493  (0x1ED)
1169     uint32_t gws_46_val; // offset: 494  (0x1EE)
1170     uint32_t gws_47_val; // offset: 495  (0x1EF)
1171     uint32_t gws_48_val; // offset: 496  (0x1F0)
1172     uint32_t gws_49_val; // offset: 497  (0x1F1)
1173     uint32_t gws_50_val; // offset: 498  (0x1F2)
1174     uint32_t gws_51_val; // offset: 499  (0x1F3)
1175     uint32_t gws_52_val; // offset: 500  (0x1F4)
1176     uint32_t gws_53_val; // offset: 501  (0x1F5)
1177     uint32_t gws_54_val; // offset: 502  (0x1F6)
1178     uint32_t gws_55_val; // offset: 503  (0x1F7)
1179     uint32_t gws_56_val; // offset: 504  (0x1F8)
1180     uint32_t gws_57_val; // offset: 505  (0x1F9)
1181     uint32_t gws_58_val; // offset: 506  (0x1FA)
1182     uint32_t gws_59_val; // offset: 507  (0x1FB)
1183     uint32_t gws_60_val; // offset: 508  (0x1FC)
1184     uint32_t gws_61_val; // offset: 509  (0x1FD)
1185     uint32_t gws_62_val; // offset: 510  (0x1FE)
1186     uint32_t gws_63_val; // offset: 511  (0x1FF)
1187 };
1188
1189 #endif /* V11_STRUCTS_H_ */