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0001 /*
0002  * Copyright (C) 2019  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _sienna_cichlid_ip_offset_HEADER
0022 #define _sienna_cichlid_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                        7
0025 #define MAX_SEGMENT                                         5
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 };
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0 } } } };
0046 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
0047                                         { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
0048                                         { { 0x00017000, 0x02402000, 0, 0, 0 } },
0049                                         { { 0x00017200, 0x02402400, 0, 0, 0 } },
0050                                         { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
0051                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0 } },
0052                                         { { 0x0001B400, 0x0242E000, 0, 0, 0 } } } };
0053 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0 } } } };
0060 static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0 } } } };
0067 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0068                                         { { 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0 } } } };
0074 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0075                                         { { 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0 } } } };
0088 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
0089                                         { { 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0 } } } };
0095 static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0 } } } };
0102 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0 } } } };
0109 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0 } } } };
0116 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
0117                                         { { 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
0124                                         { { 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0 } } } };
0130 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
0131                                         { { 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0 } } } };
0137 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0 } } } };
0144 static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
0145                                         { { 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0 } } } };
0151 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
0152                                         { { 0, 0, 0, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0 } } } };
0158 static const struct IP_BASE SDMA1_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0 } },
0159                                         { { 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0 } } } };
0165 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
0166                                         { { 0, 0, 0, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0 } },
0168                                         { { 0, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0 } } } };
0172 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
0173                                         { { 0, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0 } },
0175                                         { { 0, 0, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0 } } } };
0179 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0 } },
0180                                         { { 0x00054000, 0x02425C00, 0, 0, 0 } },
0181                                         { { 0x00094000, 0x02426000, 0, 0, 0 } },
0182                                         { { 0x000D4000, 0x02426400, 0, 0, 0 } },
0183                                         { { 0x00114000, 0x02426800, 0, 0, 0 } },
0184                                         { { 0x00154000, 0x02426C00, 0, 0, 0 } },
0185                                         { { 0x00194000, 0x02427000, 0, 0, 0 } } } };
0186 static const struct IP_BASE USB0_BASE = { { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0 } },
0191                                         { { 0, 0, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0 } } } };
0193 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
0194                                         { { 0x00007B00, 0x00012000, 0x02445000, 0, 0 } },
0195                                         { { 0, 0, 0, 0, 0 } },
0196                                         { { 0, 0, 0, 0, 0 } },
0197                                         { { 0, 0, 0, 0, 0 } },
0198                                         { { 0, 0, 0, 0, 0 } },
0199                                         { { 0, 0, 0, 0, 0 } } } };
0200 
0201 
0202 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0203 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0204 #define ATHUB_BASE__INST0_SEG2                     0
0205 #define ATHUB_BASE__INST0_SEG3                     0
0206 #define ATHUB_BASE__INST0_SEG4                     0
0207 
0208 #define ATHUB_BASE__INST1_SEG0                     0
0209 #define ATHUB_BASE__INST1_SEG1                     0
0210 #define ATHUB_BASE__INST1_SEG2                     0
0211 #define ATHUB_BASE__INST1_SEG3                     0
0212 #define ATHUB_BASE__INST1_SEG4                     0
0213 
0214 #define ATHUB_BASE__INST2_SEG0                     0
0215 #define ATHUB_BASE__INST2_SEG1                     0
0216 #define ATHUB_BASE__INST2_SEG2                     0
0217 #define ATHUB_BASE__INST2_SEG3                     0
0218 #define ATHUB_BASE__INST2_SEG4                     0
0219 
0220 #define ATHUB_BASE__INST3_SEG0                     0
0221 #define ATHUB_BASE__INST3_SEG1                     0
0222 #define ATHUB_BASE__INST3_SEG2                     0
0223 #define ATHUB_BASE__INST3_SEG3                     0
0224 #define ATHUB_BASE__INST3_SEG4                     0
0225 
0226 #define ATHUB_BASE__INST4_SEG0                     0
0227 #define ATHUB_BASE__INST4_SEG1                     0
0228 #define ATHUB_BASE__INST4_SEG2                     0
0229 #define ATHUB_BASE__INST4_SEG3                     0
0230 #define ATHUB_BASE__INST4_SEG4                     0
0231 
0232 #define ATHUB_BASE__INST5_SEG0                     0
0233 #define ATHUB_BASE__INST5_SEG1                     0
0234 #define ATHUB_BASE__INST5_SEG2                     0
0235 #define ATHUB_BASE__INST5_SEG3                     0
0236 #define ATHUB_BASE__INST5_SEG4                     0
0237 
0238 #define ATHUB_BASE__INST6_SEG0                     0
0239 #define ATHUB_BASE__INST6_SEG1                     0
0240 #define ATHUB_BASE__INST6_SEG2                     0
0241 #define ATHUB_BASE__INST6_SEG3                     0
0242 #define ATHUB_BASE__INST6_SEG4                     0
0243 
0244 #define CLK_BASE__INST0_SEG0                       0x00016C00
0245 #define CLK_BASE__INST0_SEG1                       0x02401800
0246 #define CLK_BASE__INST0_SEG2                       0
0247 #define CLK_BASE__INST0_SEG3                       0
0248 #define CLK_BASE__INST0_SEG4                       0
0249 
0250 #define CLK_BASE__INST1_SEG0                       0x00016E00
0251 #define CLK_BASE__INST1_SEG1                       0x02401C00
0252 #define CLK_BASE__INST1_SEG2                       0
0253 #define CLK_BASE__INST1_SEG3                       0
0254 #define CLK_BASE__INST1_SEG4                       0
0255 
0256 #define CLK_BASE__INST2_SEG0                       0x00017000
0257 #define CLK_BASE__INST2_SEG1                       0x02402000
0258 #define CLK_BASE__INST2_SEG2                       0
0259 #define CLK_BASE__INST2_SEG3                       0
0260 #define CLK_BASE__INST2_SEG4                       0
0261 
0262 #define CLK_BASE__INST3_SEG0                       0x00017200
0263 #define CLK_BASE__INST3_SEG1                       0x02402400
0264 #define CLK_BASE__INST3_SEG2                       0
0265 #define CLK_BASE__INST3_SEG3                       0
0266 #define CLK_BASE__INST3_SEG4                       0
0267 
0268 #define CLK_BASE__INST4_SEG0                       0x0001B000
0269 #define CLK_BASE__INST4_SEG1                       0x0242D800
0270 #define CLK_BASE__INST4_SEG2                       0
0271 #define CLK_BASE__INST4_SEG3                       0
0272 #define CLK_BASE__INST4_SEG4                       0
0273 
0274 #define CLK_BASE__INST5_SEG0                       0x0001B200
0275 #define CLK_BASE__INST5_SEG1                       0x0242DC00
0276 #define CLK_BASE__INST5_SEG2                       0
0277 #define CLK_BASE__INST5_SEG3                       0
0278 #define CLK_BASE__INST5_SEG4                       0
0279 
0280 #define CLK_BASE__INST6_SEG0                       0x0001B400
0281 #define CLK_BASE__INST6_SEG1                       0x0242E000
0282 #define CLK_BASE__INST6_SEG2                       0
0283 #define CLK_BASE__INST6_SEG3                       0
0284 #define CLK_BASE__INST6_SEG4                       0
0285 
0286 #define DF_BASE__INST0_SEG0                        0x00007000
0287 #define DF_BASE__INST0_SEG1                        0x0240B800
0288 #define DF_BASE__INST0_SEG2                        0
0289 #define DF_BASE__INST0_SEG3                        0
0290 #define DF_BASE__INST0_SEG4                        0
0291 
0292 #define DF_BASE__INST1_SEG0                        0
0293 #define DF_BASE__INST1_SEG1                        0
0294 #define DF_BASE__INST1_SEG2                        0
0295 #define DF_BASE__INST1_SEG3                        0
0296 #define DF_BASE__INST1_SEG4                        0
0297 
0298 #define DF_BASE__INST2_SEG0                        0
0299 #define DF_BASE__INST2_SEG1                        0
0300 #define DF_BASE__INST2_SEG2                        0
0301 #define DF_BASE__INST2_SEG3                        0
0302 #define DF_BASE__INST2_SEG4                        0
0303 
0304 #define DF_BASE__INST3_SEG0                        0
0305 #define DF_BASE__INST3_SEG1                        0
0306 #define DF_BASE__INST3_SEG2                        0
0307 #define DF_BASE__INST3_SEG3                        0
0308 #define DF_BASE__INST3_SEG4                        0
0309 
0310 #define DF_BASE__INST4_SEG0                        0
0311 #define DF_BASE__INST4_SEG1                        0
0312 #define DF_BASE__INST4_SEG2                        0
0313 #define DF_BASE__INST4_SEG3                        0
0314 #define DF_BASE__INST4_SEG4                        0
0315 
0316 #define DF_BASE__INST5_SEG0                        0
0317 #define DF_BASE__INST5_SEG1                        0
0318 #define DF_BASE__INST5_SEG2                        0
0319 #define DF_BASE__INST5_SEG3                        0
0320 #define DF_BASE__INST5_SEG4                        0
0321 
0322 #define DF_BASE__INST6_SEG0                        0
0323 #define DF_BASE__INST6_SEG1                        0
0324 #define DF_BASE__INST6_SEG2                        0
0325 #define DF_BASE__INST6_SEG3                        0
0326 #define DF_BASE__INST6_SEG4                        0
0327 
0328 #define DIO_BASE__INST0_SEG0                       0x02404000
0329 #define DIO_BASE__INST0_SEG1                       0
0330 #define DIO_BASE__INST0_SEG2                       0
0331 #define DIO_BASE__INST0_SEG3                       0
0332 #define DIO_BASE__INST0_SEG4                       0
0333 
0334 #define DIO_BASE__INST1_SEG0                       0
0335 #define DIO_BASE__INST1_SEG1                       0
0336 #define DIO_BASE__INST1_SEG2                       0
0337 #define DIO_BASE__INST1_SEG3                       0
0338 #define DIO_BASE__INST1_SEG4                       0
0339 
0340 #define DIO_BASE__INST2_SEG0                       0
0341 #define DIO_BASE__INST2_SEG1                       0
0342 #define DIO_BASE__INST2_SEG2                       0
0343 #define DIO_BASE__INST2_SEG3                       0
0344 #define DIO_BASE__INST2_SEG4                       0
0345 
0346 #define DIO_BASE__INST3_SEG0                       0
0347 #define DIO_BASE__INST3_SEG1                       0
0348 #define DIO_BASE__INST3_SEG2                       0
0349 #define DIO_BASE__INST3_SEG3                       0
0350 #define DIO_BASE__INST3_SEG4                       0
0351 
0352 #define DIO_BASE__INST4_SEG0                       0
0353 #define DIO_BASE__INST4_SEG1                       0
0354 #define DIO_BASE__INST4_SEG2                       0
0355 #define DIO_BASE__INST4_SEG3                       0
0356 #define DIO_BASE__INST4_SEG4                       0
0357 
0358 #define DIO_BASE__INST5_SEG0                       0
0359 #define DIO_BASE__INST5_SEG1                       0
0360 #define DIO_BASE__INST5_SEG2                       0
0361 #define DIO_BASE__INST5_SEG3                       0
0362 #define DIO_BASE__INST5_SEG4                       0
0363 
0364 #define DIO_BASE__INST6_SEG0                       0
0365 #define DIO_BASE__INST6_SEG1                       0
0366 #define DIO_BASE__INST6_SEG2                       0
0367 #define DIO_BASE__INST6_SEG3                       0
0368 #define DIO_BASE__INST6_SEG4                       0
0369 
0370 #define DCN_BASE__INST0_SEG0                       0x00000012
0371 #define DCN_BASE__INST0_SEG1                       0x000000C0
0372 #define DCN_BASE__INST0_SEG2                       0x000034C0
0373 #define DCN_BASE__INST0_SEG3                       0x00009000
0374 #define DCN_BASE__INST0_SEG4                       0x02403C00
0375 
0376 #define DCN_BASE__INST1_SEG0                       0
0377 #define DCN_BASE__INST1_SEG1                       0
0378 #define DCN_BASE__INST1_SEG2                       0
0379 #define DCN_BASE__INST1_SEG3                       0
0380 #define DCN_BASE__INST1_SEG4                       0
0381 
0382 #define DCN_BASE__INST2_SEG0                       0
0383 #define DCN_BASE__INST2_SEG1                       0
0384 #define DCN_BASE__INST2_SEG2                       0
0385 #define DCN_BASE__INST2_SEG3                       0
0386 #define DCN_BASE__INST2_SEG4                       0
0387 
0388 #define DCN_BASE__INST3_SEG0                       0
0389 #define DCN_BASE__INST3_SEG1                       0
0390 #define DCN_BASE__INST3_SEG2                       0
0391 #define DCN_BASE__INST3_SEG3                       0
0392 #define DCN_BASE__INST3_SEG4                       0
0393 
0394 #define DCN_BASE__INST4_SEG0                       0
0395 #define DCN_BASE__INST4_SEG1                       0
0396 #define DCN_BASE__INST4_SEG2                       0
0397 #define DCN_BASE__INST4_SEG3                       0
0398 #define DCN_BASE__INST4_SEG4                       0
0399 
0400 #define DCN_BASE__INST5_SEG0                       0
0401 #define DCN_BASE__INST5_SEG1                       0
0402 #define DCN_BASE__INST5_SEG2                       0
0403 #define DCN_BASE__INST5_SEG3                       0
0404 #define DCN_BASE__INST5_SEG4                       0
0405 
0406 #define DCN_BASE__INST6_SEG0                       0
0407 #define DCN_BASE__INST6_SEG1                       0
0408 #define DCN_BASE__INST6_SEG2                       0
0409 #define DCN_BASE__INST6_SEG3                       0
0410 #define DCN_BASE__INST6_SEG4                       0
0411 
0412 #define DPCS_BASE__INST0_SEG0                      0x00000012
0413 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0414 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0415 #define DPCS_BASE__INST0_SEG3                      0x00009000
0416 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0417 
0418 #define DPCS_BASE__INST1_SEG0                      0
0419 #define DPCS_BASE__INST1_SEG1                      0
0420 #define DPCS_BASE__INST1_SEG2                      0
0421 #define DPCS_BASE__INST1_SEG3                      0
0422 #define DPCS_BASE__INST1_SEG4                      0
0423 
0424 #define DPCS_BASE__INST2_SEG0                      0
0425 #define DPCS_BASE__INST2_SEG1                      0
0426 #define DPCS_BASE__INST2_SEG2                      0
0427 #define DPCS_BASE__INST2_SEG3                      0
0428 #define DPCS_BASE__INST2_SEG4                      0
0429 
0430 #define DPCS_BASE__INST3_SEG0                      0
0431 #define DPCS_BASE__INST3_SEG1                      0
0432 #define DPCS_BASE__INST3_SEG2                      0
0433 #define DPCS_BASE__INST3_SEG3                      0
0434 #define DPCS_BASE__INST3_SEG4                      0
0435 
0436 #define DPCS_BASE__INST4_SEG0                      0
0437 #define DPCS_BASE__INST4_SEG1                      0
0438 #define DPCS_BASE__INST4_SEG2                      0
0439 #define DPCS_BASE__INST4_SEG3                      0
0440 #define DPCS_BASE__INST4_SEG4                      0
0441 
0442 #define DPCS_BASE__INST5_SEG0                      0
0443 #define DPCS_BASE__INST5_SEG1                      0
0444 #define DPCS_BASE__INST5_SEG2                      0
0445 #define DPCS_BASE__INST5_SEG3                      0
0446 #define DPCS_BASE__INST5_SEG4                      0
0447 
0448 #define DPCS_BASE__INST6_SEG0                      0
0449 #define DPCS_BASE__INST6_SEG1                      0
0450 #define DPCS_BASE__INST6_SEG2                      0
0451 #define DPCS_BASE__INST6_SEG3                      0
0452 #define DPCS_BASE__INST6_SEG4                      0
0453 
0454 #define FUSE_BASE__INST0_SEG0                      0x00017400
0455 #define FUSE_BASE__INST0_SEG1                      0x02401400
0456 #define FUSE_BASE__INST0_SEG2                      0
0457 #define FUSE_BASE__INST0_SEG3                      0
0458 #define FUSE_BASE__INST0_SEG4                      0
0459 
0460 #define FUSE_BASE__INST1_SEG0                      0
0461 #define FUSE_BASE__INST1_SEG1                      0
0462 #define FUSE_BASE__INST1_SEG2                      0
0463 #define FUSE_BASE__INST1_SEG3                      0
0464 #define FUSE_BASE__INST1_SEG4                      0
0465 
0466 #define FUSE_BASE__INST2_SEG0                      0
0467 #define FUSE_BASE__INST2_SEG1                      0
0468 #define FUSE_BASE__INST2_SEG2                      0
0469 #define FUSE_BASE__INST2_SEG3                      0
0470 #define FUSE_BASE__INST2_SEG4                      0
0471 
0472 #define FUSE_BASE__INST3_SEG0                      0
0473 #define FUSE_BASE__INST3_SEG1                      0
0474 #define FUSE_BASE__INST3_SEG2                      0
0475 #define FUSE_BASE__INST3_SEG3                      0
0476 #define FUSE_BASE__INST3_SEG4                      0
0477 
0478 #define FUSE_BASE__INST4_SEG0                      0
0479 #define FUSE_BASE__INST4_SEG1                      0
0480 #define FUSE_BASE__INST4_SEG2                      0
0481 #define FUSE_BASE__INST4_SEG3                      0
0482 #define FUSE_BASE__INST4_SEG4                      0
0483 
0484 #define FUSE_BASE__INST5_SEG0                      0
0485 #define FUSE_BASE__INST5_SEG1                      0
0486 #define FUSE_BASE__INST5_SEG2                      0
0487 #define FUSE_BASE__INST5_SEG3                      0
0488 #define FUSE_BASE__INST5_SEG4                      0
0489 
0490 #define FUSE_BASE__INST6_SEG0                      0
0491 #define FUSE_BASE__INST6_SEG1                      0
0492 #define FUSE_BASE__INST6_SEG2                      0
0493 #define FUSE_BASE__INST6_SEG3                      0
0494 #define FUSE_BASE__INST6_SEG4                      0
0495 
0496 #define GC_BASE__INST0_SEG0                        0x00001260
0497 #define GC_BASE__INST0_SEG1                        0x0000A000
0498 #define GC_BASE__INST0_SEG2                        0x0001C000
0499 #define GC_BASE__INST0_SEG3                        0x02402C00
0500 #define GC_BASE__INST0_SEG4                        0
0501 
0502 #define GC_BASE__INST1_SEG0                        0
0503 #define GC_BASE__INST1_SEG1                        0
0504 #define GC_BASE__INST1_SEG2                        0
0505 #define GC_BASE__INST1_SEG3                        0
0506 #define GC_BASE__INST1_SEG4                        0
0507 
0508 #define GC_BASE__INST2_SEG0                        0
0509 #define GC_BASE__INST2_SEG1                        0
0510 #define GC_BASE__INST2_SEG2                        0
0511 #define GC_BASE__INST2_SEG3                        0
0512 #define GC_BASE__INST2_SEG4                        0
0513 
0514 #define GC_BASE__INST3_SEG0                        0
0515 #define GC_BASE__INST3_SEG1                        0
0516 #define GC_BASE__INST3_SEG2                        0
0517 #define GC_BASE__INST3_SEG3                        0
0518 #define GC_BASE__INST3_SEG4                        0
0519 
0520 #define GC_BASE__INST4_SEG0                        0
0521 #define GC_BASE__INST4_SEG1                        0
0522 #define GC_BASE__INST4_SEG2                        0
0523 #define GC_BASE__INST4_SEG3                        0
0524 #define GC_BASE__INST4_SEG4                        0
0525 
0526 #define GC_BASE__INST5_SEG0                        0
0527 #define GC_BASE__INST5_SEG1                        0
0528 #define GC_BASE__INST5_SEG2                        0
0529 #define GC_BASE__INST5_SEG3                        0
0530 #define GC_BASE__INST5_SEG4                        0
0531 
0532 #define GC_BASE__INST6_SEG0                        0
0533 #define GC_BASE__INST6_SEG1                        0
0534 #define GC_BASE__INST6_SEG2                        0
0535 #define GC_BASE__INST6_SEG3                        0
0536 #define GC_BASE__INST6_SEG4                        0
0537 
0538 #define HDA_BASE__INST0_SEG0                       0x004C0000
0539 #define HDA_BASE__INST0_SEG1                       0x02404800
0540 #define HDA_BASE__INST0_SEG2                       0
0541 #define HDA_BASE__INST0_SEG3                       0
0542 #define HDA_BASE__INST0_SEG4                       0
0543 
0544 #define HDA_BASE__INST1_SEG0                       0
0545 #define HDA_BASE__INST1_SEG1                       0
0546 #define HDA_BASE__INST1_SEG2                       0
0547 #define HDA_BASE__INST1_SEG3                       0
0548 #define HDA_BASE__INST1_SEG4                       0
0549 
0550 #define HDA_BASE__INST2_SEG0                       0
0551 #define HDA_BASE__INST2_SEG1                       0
0552 #define HDA_BASE__INST2_SEG2                       0
0553 #define HDA_BASE__INST2_SEG3                       0
0554 #define HDA_BASE__INST2_SEG4                       0
0555 
0556 #define HDA_BASE__INST3_SEG0                       0
0557 #define HDA_BASE__INST3_SEG1                       0
0558 #define HDA_BASE__INST3_SEG2                       0
0559 #define HDA_BASE__INST3_SEG3                       0
0560 #define HDA_BASE__INST3_SEG4                       0
0561 
0562 #define HDA_BASE__INST4_SEG0                       0
0563 #define HDA_BASE__INST4_SEG1                       0
0564 #define HDA_BASE__INST4_SEG2                       0
0565 #define HDA_BASE__INST4_SEG3                       0
0566 #define HDA_BASE__INST4_SEG4                       0
0567 
0568 #define HDA_BASE__INST5_SEG0                       0
0569 #define HDA_BASE__INST5_SEG1                       0
0570 #define HDA_BASE__INST5_SEG2                       0
0571 #define HDA_BASE__INST5_SEG3                       0
0572 #define HDA_BASE__INST5_SEG4                       0
0573 
0574 #define HDA_BASE__INST6_SEG0                       0
0575 #define HDA_BASE__INST6_SEG1                       0
0576 #define HDA_BASE__INST6_SEG2                       0
0577 #define HDA_BASE__INST6_SEG3                       0
0578 #define HDA_BASE__INST6_SEG4                       0
0579 
0580 #define HDP_BASE__INST0_SEG0                       0x00000F20
0581 #define HDP_BASE__INST0_SEG1                       0x0240A400
0582 #define HDP_BASE__INST0_SEG2                       0
0583 #define HDP_BASE__INST0_SEG3                       0
0584 #define HDP_BASE__INST0_SEG4                       0
0585 
0586 #define HDP_BASE__INST1_SEG0                       0
0587 #define HDP_BASE__INST1_SEG1                       0
0588 #define HDP_BASE__INST1_SEG2                       0
0589 #define HDP_BASE__INST1_SEG3                       0
0590 #define HDP_BASE__INST1_SEG4                       0
0591 
0592 #define HDP_BASE__INST2_SEG0                       0
0593 #define HDP_BASE__INST2_SEG1                       0
0594 #define HDP_BASE__INST2_SEG2                       0
0595 #define HDP_BASE__INST2_SEG3                       0
0596 #define HDP_BASE__INST2_SEG4                       0
0597 
0598 #define HDP_BASE__INST3_SEG0                       0
0599 #define HDP_BASE__INST3_SEG1                       0
0600 #define HDP_BASE__INST3_SEG2                       0
0601 #define HDP_BASE__INST3_SEG3                       0
0602 #define HDP_BASE__INST3_SEG4                       0
0603 
0604 #define HDP_BASE__INST4_SEG0                       0
0605 #define HDP_BASE__INST4_SEG1                       0
0606 #define HDP_BASE__INST4_SEG2                       0
0607 #define HDP_BASE__INST4_SEG3                       0
0608 #define HDP_BASE__INST4_SEG4                       0
0609 
0610 #define HDP_BASE__INST5_SEG0                       0
0611 #define HDP_BASE__INST5_SEG1                       0
0612 #define HDP_BASE__INST5_SEG2                       0
0613 #define HDP_BASE__INST5_SEG3                       0
0614 #define HDP_BASE__INST5_SEG4                       0
0615 
0616 #define HDP_BASE__INST6_SEG0                       0
0617 #define HDP_BASE__INST6_SEG1                       0
0618 #define HDP_BASE__INST6_SEG2                       0
0619 #define HDP_BASE__INST6_SEG3                       0
0620 #define HDP_BASE__INST6_SEG4                       0
0621 
0622 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0623 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0624 #define MMHUB_BASE__INST0_SEG2                     0
0625 #define MMHUB_BASE__INST0_SEG3                     0
0626 #define MMHUB_BASE__INST0_SEG4                     0
0627 
0628 #define MMHUB_BASE__INST1_SEG0                     0
0629 #define MMHUB_BASE__INST1_SEG1                     0
0630 #define MMHUB_BASE__INST1_SEG2                     0
0631 #define MMHUB_BASE__INST1_SEG3                     0
0632 #define MMHUB_BASE__INST1_SEG4                     0
0633 
0634 #define MMHUB_BASE__INST2_SEG0                     0
0635 #define MMHUB_BASE__INST2_SEG1                     0
0636 #define MMHUB_BASE__INST2_SEG2                     0
0637 #define MMHUB_BASE__INST2_SEG3                     0
0638 #define MMHUB_BASE__INST2_SEG4                     0
0639 
0640 #define MMHUB_BASE__INST3_SEG0                     0
0641 #define MMHUB_BASE__INST3_SEG1                     0
0642 #define MMHUB_BASE__INST3_SEG2                     0
0643 #define MMHUB_BASE__INST3_SEG3                     0
0644 #define MMHUB_BASE__INST3_SEG4                     0
0645 
0646 #define MMHUB_BASE__INST4_SEG0                     0
0647 #define MMHUB_BASE__INST4_SEG1                     0
0648 #define MMHUB_BASE__INST4_SEG2                     0
0649 #define MMHUB_BASE__INST4_SEG3                     0
0650 #define MMHUB_BASE__INST4_SEG4                     0
0651 
0652 #define MMHUB_BASE__INST5_SEG0                     0
0653 #define MMHUB_BASE__INST5_SEG1                     0
0654 #define MMHUB_BASE__INST5_SEG2                     0
0655 #define MMHUB_BASE__INST5_SEG3                     0
0656 #define MMHUB_BASE__INST5_SEG4                     0
0657 
0658 #define MMHUB_BASE__INST6_SEG0                     0
0659 #define MMHUB_BASE__INST6_SEG1                     0
0660 #define MMHUB_BASE__INST6_SEG2                     0
0661 #define MMHUB_BASE__INST6_SEG3                     0
0662 #define MMHUB_BASE__INST6_SEG4                     0
0663 
0664 #define MP0_BASE__INST0_SEG0                       0x00016000
0665 #define MP0_BASE__INST0_SEG1                       0x00DC0000
0666 #define MP0_BASE__INST0_SEG2                       0x00E00000
0667 #define MP0_BASE__INST0_SEG3                       0x00E40000
0668 #define MP0_BASE__INST0_SEG4                       0x0243FC00
0669 
0670 #define MP0_BASE__INST1_SEG0                       0
0671 #define MP0_BASE__INST1_SEG1                       0
0672 #define MP0_BASE__INST1_SEG2                       0
0673 #define MP0_BASE__INST1_SEG3                       0
0674 #define MP0_BASE__INST1_SEG4                       0
0675 
0676 #define MP0_BASE__INST2_SEG0                       0
0677 #define MP0_BASE__INST2_SEG1                       0
0678 #define MP0_BASE__INST2_SEG2                       0
0679 #define MP0_BASE__INST2_SEG3                       0
0680 #define MP0_BASE__INST2_SEG4                       0
0681 
0682 #define MP0_BASE__INST3_SEG0                       0
0683 #define MP0_BASE__INST3_SEG1                       0
0684 #define MP0_BASE__INST3_SEG2                       0
0685 #define MP0_BASE__INST3_SEG3                       0
0686 #define MP0_BASE__INST3_SEG4                       0
0687 
0688 #define MP0_BASE__INST4_SEG0                       0
0689 #define MP0_BASE__INST4_SEG1                       0
0690 #define MP0_BASE__INST4_SEG2                       0
0691 #define MP0_BASE__INST4_SEG3                       0
0692 #define MP0_BASE__INST4_SEG4                       0
0693 
0694 #define MP0_BASE__INST5_SEG0                       0
0695 #define MP0_BASE__INST5_SEG1                       0
0696 #define MP0_BASE__INST5_SEG2                       0
0697 #define MP0_BASE__INST5_SEG3                       0
0698 #define MP0_BASE__INST5_SEG4                       0
0699 
0700 #define MP0_BASE__INST6_SEG0                       0
0701 #define MP0_BASE__INST6_SEG1                       0
0702 #define MP0_BASE__INST6_SEG2                       0
0703 #define MP0_BASE__INST6_SEG3                       0
0704 #define MP0_BASE__INST6_SEG4                       0
0705 
0706 #define MP1_BASE__INST0_SEG0                       0x00016000
0707 #define MP1_BASE__INST0_SEG1                       0x00DC0000
0708 #define MP1_BASE__INST0_SEG2                       0x00E00000
0709 #define MP1_BASE__INST0_SEG3                       0x00E40000
0710 #define MP1_BASE__INST0_SEG4                       0x0243FC00
0711 
0712 #define MP1_BASE__INST1_SEG0                       0
0713 #define MP1_BASE__INST1_SEG1                       0
0714 #define MP1_BASE__INST1_SEG2                       0
0715 #define MP1_BASE__INST1_SEG3                       0
0716 #define MP1_BASE__INST1_SEG4                       0
0717 
0718 #define MP1_BASE__INST2_SEG0                       0
0719 #define MP1_BASE__INST2_SEG1                       0
0720 #define MP1_BASE__INST2_SEG2                       0
0721 #define MP1_BASE__INST2_SEG3                       0
0722 #define MP1_BASE__INST2_SEG4                       0
0723 
0724 #define MP1_BASE__INST3_SEG0                       0
0725 #define MP1_BASE__INST3_SEG1                       0
0726 #define MP1_BASE__INST3_SEG2                       0
0727 #define MP1_BASE__INST3_SEG3                       0
0728 #define MP1_BASE__INST3_SEG4                       0
0729 
0730 #define MP1_BASE__INST4_SEG0                       0
0731 #define MP1_BASE__INST4_SEG1                       0
0732 #define MP1_BASE__INST4_SEG2                       0
0733 #define MP1_BASE__INST4_SEG3                       0
0734 #define MP1_BASE__INST4_SEG4                       0
0735 
0736 #define MP1_BASE__INST5_SEG0                       0
0737 #define MP1_BASE__INST5_SEG1                       0
0738 #define MP1_BASE__INST5_SEG2                       0
0739 #define MP1_BASE__INST5_SEG3                       0
0740 #define MP1_BASE__INST5_SEG4                       0
0741 
0742 #define MP1_BASE__INST6_SEG0                       0
0743 #define MP1_BASE__INST6_SEG1                       0
0744 #define MP1_BASE__INST6_SEG2                       0
0745 #define MP1_BASE__INST6_SEG3                       0
0746 #define MP1_BASE__INST6_SEG4                       0
0747 
0748 #define NBIO_BASE__INST0_SEG0                      0x00000000
0749 #define NBIO_BASE__INST0_SEG1                      0x00000014
0750 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0751 #define NBIO_BASE__INST0_SEG3                      0x00010400
0752 #define NBIO_BASE__INST0_SEG4                      0x0241B000
0753 
0754 #define NBIO_BASE__INST1_SEG0                      0
0755 #define NBIO_BASE__INST1_SEG1                      0
0756 #define NBIO_BASE__INST1_SEG2                      0
0757 #define NBIO_BASE__INST1_SEG3                      0
0758 #define NBIO_BASE__INST1_SEG4                      0
0759 
0760 #define NBIO_BASE__INST2_SEG0                      0
0761 #define NBIO_BASE__INST2_SEG1                      0
0762 #define NBIO_BASE__INST2_SEG2                      0
0763 #define NBIO_BASE__INST2_SEG3                      0
0764 #define NBIO_BASE__INST2_SEG4                      0
0765 
0766 #define NBIO_BASE__INST3_SEG0                      0
0767 #define NBIO_BASE__INST3_SEG1                      0
0768 #define NBIO_BASE__INST3_SEG2                      0
0769 #define NBIO_BASE__INST3_SEG3                      0
0770 #define NBIO_BASE__INST3_SEG4                      0
0771 
0772 #define NBIO_BASE__INST4_SEG0                      0
0773 #define NBIO_BASE__INST4_SEG1                      0
0774 #define NBIO_BASE__INST4_SEG2                      0
0775 #define NBIO_BASE__INST4_SEG3                      0
0776 #define NBIO_BASE__INST4_SEG4                      0
0777 
0778 #define NBIO_BASE__INST5_SEG0                      0
0779 #define NBIO_BASE__INST5_SEG1                      0
0780 #define NBIO_BASE__INST5_SEG2                      0
0781 #define NBIO_BASE__INST5_SEG3                      0
0782 #define NBIO_BASE__INST5_SEG4                      0
0783 
0784 #define NBIO_BASE__INST6_SEG0                      0
0785 #define NBIO_BASE__INST6_SEG1                      0
0786 #define NBIO_BASE__INST6_SEG2                      0
0787 #define NBIO_BASE__INST6_SEG3                      0
0788 #define NBIO_BASE__INST6_SEG4                      0
0789 
0790 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0791 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
0792 #define OSSSYS_BASE__INST0_SEG2                    0
0793 #define OSSSYS_BASE__INST0_SEG3                    0
0794 #define OSSSYS_BASE__INST0_SEG4                    0
0795 
0796 #define OSSSYS_BASE__INST1_SEG0                    0
0797 #define OSSSYS_BASE__INST1_SEG1                    0
0798 #define OSSSYS_BASE__INST1_SEG2                    0
0799 #define OSSSYS_BASE__INST1_SEG3                    0
0800 #define OSSSYS_BASE__INST1_SEG4                    0
0801 
0802 #define OSSSYS_BASE__INST2_SEG0                    0
0803 #define OSSSYS_BASE__INST2_SEG1                    0
0804 #define OSSSYS_BASE__INST2_SEG2                    0
0805 #define OSSSYS_BASE__INST2_SEG3                    0
0806 #define OSSSYS_BASE__INST2_SEG4                    0
0807 
0808 #define OSSSYS_BASE__INST3_SEG0                    0
0809 #define OSSSYS_BASE__INST3_SEG1                    0
0810 #define OSSSYS_BASE__INST3_SEG2                    0
0811 #define OSSSYS_BASE__INST3_SEG3                    0
0812 #define OSSSYS_BASE__INST3_SEG4                    0
0813 
0814 #define OSSSYS_BASE__INST4_SEG0                    0
0815 #define OSSSYS_BASE__INST4_SEG1                    0
0816 #define OSSSYS_BASE__INST4_SEG2                    0
0817 #define OSSSYS_BASE__INST4_SEG3                    0
0818 #define OSSSYS_BASE__INST4_SEG4                    0
0819 
0820 #define OSSSYS_BASE__INST5_SEG0                    0
0821 #define OSSSYS_BASE__INST5_SEG1                    0
0822 #define OSSSYS_BASE__INST5_SEG2                    0
0823 #define OSSSYS_BASE__INST5_SEG3                    0
0824 #define OSSSYS_BASE__INST5_SEG4                    0
0825 
0826 #define OSSSYS_BASE__INST6_SEG0                    0
0827 #define OSSSYS_BASE__INST6_SEG1                    0
0828 #define OSSSYS_BASE__INST6_SEG2                    0
0829 #define OSSSYS_BASE__INST6_SEG3                    0
0830 #define OSSSYS_BASE__INST6_SEG4                    0
0831 
0832 #define PCIE0_BASE__INST0_SEG0                     0x00000000
0833 #define PCIE0_BASE__INST0_SEG1                     0x00000014
0834 #define PCIE0_BASE__INST0_SEG2                     0x00000D20
0835 #define PCIE0_BASE__INST0_SEG3                     0x00010400
0836 #define PCIE0_BASE__INST0_SEG4                     0x0241B000
0837 
0838 #define PCIE0_BASE__INST1_SEG0                     0
0839 #define PCIE0_BASE__INST1_SEG1                     0
0840 #define PCIE0_BASE__INST1_SEG2                     0
0841 #define PCIE0_BASE__INST1_SEG3                     0
0842 #define PCIE0_BASE__INST1_SEG4                     0
0843 
0844 #define PCIE0_BASE__INST2_SEG0                     0
0845 #define PCIE0_BASE__INST2_SEG1                     0
0846 #define PCIE0_BASE__INST2_SEG2                     0
0847 #define PCIE0_BASE__INST2_SEG3                     0
0848 #define PCIE0_BASE__INST2_SEG4                     0
0849 
0850 #define PCIE0_BASE__INST3_SEG0                     0
0851 #define PCIE0_BASE__INST3_SEG1                     0
0852 #define PCIE0_BASE__INST3_SEG2                     0
0853 #define PCIE0_BASE__INST3_SEG3                     0
0854 #define PCIE0_BASE__INST3_SEG4                     0
0855 
0856 #define PCIE0_BASE__INST4_SEG0                     0
0857 #define PCIE0_BASE__INST4_SEG1                     0
0858 #define PCIE0_BASE__INST4_SEG2                     0
0859 #define PCIE0_BASE__INST4_SEG3                     0
0860 #define PCIE0_BASE__INST4_SEG4                     0
0861 
0862 #define PCIE0_BASE__INST5_SEG0                     0
0863 #define PCIE0_BASE__INST5_SEG1                     0
0864 #define PCIE0_BASE__INST5_SEG2                     0
0865 #define PCIE0_BASE__INST5_SEG3                     0
0866 #define PCIE0_BASE__INST5_SEG4                     0
0867 
0868 #define PCIE0_BASE__INST6_SEG0                     0
0869 #define PCIE0_BASE__INST6_SEG1                     0
0870 #define PCIE0_BASE__INST6_SEG2                     0
0871 #define PCIE0_BASE__INST6_SEG3                     0
0872 #define PCIE0_BASE__INST6_SEG4                     0
0873 
0874 #define SDMA0_BASE__INST0_SEG0                     0x00001260
0875 #define SDMA0_BASE__INST0_SEG1                     0x0000A000
0876 #define SDMA0_BASE__INST0_SEG2                     0x0001C000
0877 #define SDMA0_BASE__INST0_SEG3                     0x02402C00
0878 #define SDMA0_BASE__INST0_SEG4                     0
0879 
0880 #define SDMA0_BASE__INST1_SEG0                     0
0881 #define SDMA0_BASE__INST1_SEG1                     0
0882 #define SDMA0_BASE__INST1_SEG2                     0
0883 #define SDMA0_BASE__INST1_SEG3                     0
0884 #define SDMA0_BASE__INST1_SEG4                     0
0885 
0886 #define SDMA0_BASE__INST2_SEG0                     0
0887 #define SDMA0_BASE__INST2_SEG1                     0
0888 #define SDMA0_BASE__INST2_SEG2                     0
0889 #define SDMA0_BASE__INST2_SEG3                     0
0890 #define SDMA0_BASE__INST2_SEG4                     0
0891 
0892 #define SDMA0_BASE__INST3_SEG0                     0
0893 #define SDMA0_BASE__INST3_SEG1                     0
0894 #define SDMA0_BASE__INST3_SEG2                     0
0895 #define SDMA0_BASE__INST3_SEG3                     0
0896 #define SDMA0_BASE__INST3_SEG4                     0
0897 
0898 #define SDMA0_BASE__INST4_SEG0                     0
0899 #define SDMA0_BASE__INST4_SEG1                     0
0900 #define SDMA0_BASE__INST4_SEG2                     0
0901 #define SDMA0_BASE__INST4_SEG3                     0
0902 #define SDMA0_BASE__INST4_SEG4                     0
0903 
0904 #define SDMA0_BASE__INST5_SEG0                     0
0905 #define SDMA0_BASE__INST5_SEG1                     0
0906 #define SDMA0_BASE__INST5_SEG2                     0
0907 #define SDMA0_BASE__INST5_SEG3                     0
0908 #define SDMA0_BASE__INST5_SEG4                     0
0909 
0910 #define SDMA0_BASE__INST6_SEG0                     0
0911 #define SDMA0_BASE__INST6_SEG1                     0
0912 #define SDMA0_BASE__INST6_SEG2                     0
0913 #define SDMA0_BASE__INST6_SEG3                     0
0914 #define SDMA0_BASE__INST6_SEG4                     0
0915 
0916 #define SDMA1_BASE__INST0_SEG0                     0x00001260
0917 #define SDMA1_BASE__INST0_SEG1                     0x0000A000
0918 #define SDMA1_BASE__INST0_SEG2                     0x0001C000
0919 #define SDMA1_BASE__INST0_SEG3                     0x02402C00
0920 #define SDMA1_BASE__INST0_SEG4                     0
0921 
0922 #define SDMA1_BASE__INST1_SEG0                     0
0923 #define SDMA1_BASE__INST1_SEG1                     0
0924 #define SDMA1_BASE__INST1_SEG2                     0
0925 #define SDMA1_BASE__INST1_SEG3                     0
0926 #define SDMA1_BASE__INST1_SEG4                     0
0927 
0928 #define SDMA1_BASE__INST2_SEG0                     0
0929 #define SDMA1_BASE__INST2_SEG1                     0
0930 #define SDMA1_BASE__INST2_SEG2                     0
0931 #define SDMA1_BASE__INST2_SEG3                     0
0932 #define SDMA1_BASE__INST2_SEG4                     0
0933 
0934 #define SDMA1_BASE__INST3_SEG0                     0
0935 #define SDMA1_BASE__INST3_SEG1                     0
0936 #define SDMA1_BASE__INST3_SEG2                     0
0937 #define SDMA1_BASE__INST3_SEG3                     0
0938 #define SDMA1_BASE__INST3_SEG4                     0
0939 
0940 #define SDMA1_BASE__INST4_SEG0                     0
0941 #define SDMA1_BASE__INST4_SEG1                     0
0942 #define SDMA1_BASE__INST4_SEG2                     0
0943 #define SDMA1_BASE__INST4_SEG3                     0
0944 #define SDMA1_BASE__INST4_SEG4                     0
0945 
0946 #define SDMA1_BASE__INST5_SEG0                     0
0947 #define SDMA1_BASE__INST5_SEG1                     0
0948 #define SDMA1_BASE__INST5_SEG2                     0
0949 #define SDMA1_BASE__INST5_SEG3                     0
0950 #define SDMA1_BASE__INST5_SEG4                     0
0951 
0952 #define SDMA1_BASE__INST6_SEG0                     0
0953 #define SDMA1_BASE__INST6_SEG1                     0
0954 #define SDMA1_BASE__INST6_SEG2                     0
0955 #define SDMA1_BASE__INST6_SEG3                     0
0956 #define SDMA1_BASE__INST6_SEG4                     0
0957 
0958 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0959 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0960 #define SMUIO_BASE__INST0_SEG2                     0x00440000
0961 #define SMUIO_BASE__INST0_SEG3                     0x02401000
0962 #define SMUIO_BASE__INST0_SEG4                     0
0963 
0964 #define SMUIO_BASE__INST1_SEG0                     0
0965 #define SMUIO_BASE__INST1_SEG1                     0
0966 #define SMUIO_BASE__INST1_SEG2                     0
0967 #define SMUIO_BASE__INST1_SEG3                     0
0968 #define SMUIO_BASE__INST1_SEG4                     0
0969 
0970 #define SMUIO_BASE__INST2_SEG0                     0
0971 #define SMUIO_BASE__INST2_SEG1                     0
0972 #define SMUIO_BASE__INST2_SEG2                     0
0973 #define SMUIO_BASE__INST2_SEG3                     0
0974 #define SMUIO_BASE__INST2_SEG4                     0
0975 
0976 #define SMUIO_BASE__INST3_SEG0                     0
0977 #define SMUIO_BASE__INST3_SEG1                     0
0978 #define SMUIO_BASE__INST3_SEG2                     0
0979 #define SMUIO_BASE__INST3_SEG3                     0
0980 #define SMUIO_BASE__INST3_SEG4                     0
0981 
0982 #define SMUIO_BASE__INST4_SEG0                     0
0983 #define SMUIO_BASE__INST4_SEG1                     0
0984 #define SMUIO_BASE__INST4_SEG2                     0
0985 #define SMUIO_BASE__INST4_SEG3                     0
0986 #define SMUIO_BASE__INST4_SEG4                     0
0987 
0988 #define SMUIO_BASE__INST5_SEG0                     0
0989 #define SMUIO_BASE__INST5_SEG1                     0
0990 #define SMUIO_BASE__INST5_SEG2                     0
0991 #define SMUIO_BASE__INST5_SEG3                     0
0992 #define SMUIO_BASE__INST5_SEG4                     0
0993 
0994 #define SMUIO_BASE__INST6_SEG0                     0
0995 #define SMUIO_BASE__INST6_SEG1                     0
0996 #define SMUIO_BASE__INST6_SEG2                     0
0997 #define SMUIO_BASE__INST6_SEG3                     0
0998 #define SMUIO_BASE__INST6_SEG4                     0
0999 
1000 #define THM_BASE__INST0_SEG0                       0x00016600
1001 #define THM_BASE__INST0_SEG1                       0x02400C00
1002 #define THM_BASE__INST0_SEG2                       0
1003 #define THM_BASE__INST0_SEG3                       0
1004 #define THM_BASE__INST0_SEG4                       0
1005 
1006 #define THM_BASE__INST1_SEG0                       0
1007 #define THM_BASE__INST1_SEG1                       0
1008 #define THM_BASE__INST1_SEG2                       0
1009 #define THM_BASE__INST1_SEG3                       0
1010 #define THM_BASE__INST1_SEG4                       0
1011 
1012 #define THM_BASE__INST2_SEG0                       0
1013 #define THM_BASE__INST2_SEG1                       0
1014 #define THM_BASE__INST2_SEG2                       0
1015 #define THM_BASE__INST2_SEG3                       0
1016 #define THM_BASE__INST2_SEG4                       0
1017 
1018 #define THM_BASE__INST3_SEG0                       0
1019 #define THM_BASE__INST3_SEG1                       0
1020 #define THM_BASE__INST3_SEG2                       0
1021 #define THM_BASE__INST3_SEG3                       0
1022 #define THM_BASE__INST3_SEG4                       0
1023 
1024 #define THM_BASE__INST4_SEG0                       0
1025 #define THM_BASE__INST4_SEG1                       0
1026 #define THM_BASE__INST4_SEG2                       0
1027 #define THM_BASE__INST4_SEG3                       0
1028 #define THM_BASE__INST4_SEG4                       0
1029 
1030 #define THM_BASE__INST5_SEG0                       0
1031 #define THM_BASE__INST5_SEG1                       0
1032 #define THM_BASE__INST5_SEG2                       0
1033 #define THM_BASE__INST5_SEG3                       0
1034 #define THM_BASE__INST5_SEG4                       0
1035 
1036 #define THM_BASE__INST6_SEG0                       0
1037 #define THM_BASE__INST6_SEG1                       0
1038 #define THM_BASE__INST6_SEG2                       0
1039 #define THM_BASE__INST6_SEG3                       0
1040 #define THM_BASE__INST6_SEG4                       0
1041 
1042 #define UMC_BASE__INST0_SEG0                       0x00014000
1043 #define UMC_BASE__INST0_SEG1                       0x02425800
1044 #define UMC_BASE__INST0_SEG2                       0
1045 #define UMC_BASE__INST0_SEG3                       0
1046 #define UMC_BASE__INST0_SEG4                       0
1047 
1048 #define UMC_BASE__INST1_SEG0                       0x00054000
1049 #define UMC_BASE__INST1_SEG1                       0x02425C00
1050 #define UMC_BASE__INST1_SEG2                       0
1051 #define UMC_BASE__INST1_SEG3                       0
1052 #define UMC_BASE__INST1_SEG4                       0
1053 
1054 #define UMC_BASE__INST2_SEG0                       0x00094000
1055 #define UMC_BASE__INST2_SEG1                       0x02426000
1056 #define UMC_BASE__INST2_SEG2                       0
1057 #define UMC_BASE__INST2_SEG3                       0
1058 #define UMC_BASE__INST2_SEG4                       0
1059 
1060 #define UMC_BASE__INST3_SEG0                       0x000D4000
1061 #define UMC_BASE__INST3_SEG1                       0x02426400
1062 #define UMC_BASE__INST3_SEG2                       0
1063 #define UMC_BASE__INST3_SEG3                       0
1064 #define UMC_BASE__INST3_SEG4                       0
1065 
1066 #define UMC_BASE__INST4_SEG0                       0x00114000
1067 #define UMC_BASE__INST4_SEG1                       0x02426800
1068 #define UMC_BASE__INST4_SEG2                       0
1069 #define UMC_BASE__INST4_SEG3                       0
1070 #define UMC_BASE__INST4_SEG4                       0
1071 
1072 #define UMC_BASE__INST5_SEG0                       0x00154000
1073 #define UMC_BASE__INST5_SEG1                       0x02426C00
1074 #define UMC_BASE__INST5_SEG2                       0
1075 #define UMC_BASE__INST5_SEG3                       0
1076 #define UMC_BASE__INST5_SEG4                       0
1077 
1078 #define UMC_BASE__INST6_SEG0                       0x00194000
1079 #define UMC_BASE__INST6_SEG1                       0x02427000
1080 #define UMC_BASE__INST6_SEG2                       0
1081 #define UMC_BASE__INST6_SEG3                       0
1082 #define UMC_BASE__INST6_SEG4                       0
1083 
1084 #define USB0_BASE__INST0_SEG0                      0x0242A800
1085 #define USB0_BASE__INST0_SEG1                      0x05B00000
1086 #define USB0_BASE__INST0_SEG2                      0
1087 #define USB0_BASE__INST0_SEG3                      0
1088 #define USB0_BASE__INST0_SEG4                      0
1089 
1090 #define USB0_BASE__INST1_SEG0                      0
1091 #define USB0_BASE__INST1_SEG1                      0
1092 #define USB0_BASE__INST1_SEG2                      0
1093 #define USB0_BASE__INST1_SEG3                      0
1094 #define USB0_BASE__INST1_SEG4                      0
1095 
1096 #define USB0_BASE__INST2_SEG0                      0
1097 #define USB0_BASE__INST2_SEG1                      0
1098 #define USB0_BASE__INST2_SEG2                      0
1099 #define USB0_BASE__INST2_SEG3                      0
1100 #define USB0_BASE__INST2_SEG4                      0
1101 
1102 #define USB0_BASE__INST3_SEG0                      0
1103 #define USB0_BASE__INST3_SEG1                      0
1104 #define USB0_BASE__INST3_SEG2                      0
1105 #define USB0_BASE__INST3_SEG3                      0
1106 #define USB0_BASE__INST3_SEG4                      0
1107 
1108 #define USB0_BASE__INST4_SEG0                      0
1109 #define USB0_BASE__INST4_SEG1                      0
1110 #define USB0_BASE__INST4_SEG2                      0
1111 #define USB0_BASE__INST4_SEG3                      0
1112 #define USB0_BASE__INST4_SEG4                      0
1113 
1114 #define USB0_BASE__INST5_SEG0                      0
1115 #define USB0_BASE__INST5_SEG1                      0
1116 #define USB0_BASE__INST5_SEG2                      0
1117 #define USB0_BASE__INST5_SEG3                      0
1118 #define USB0_BASE__INST5_SEG4                      0
1119 
1120 #define USB0_BASE__INST6_SEG0                      0
1121 #define USB0_BASE__INST6_SEG1                      0
1122 #define USB0_BASE__INST6_SEG2                      0
1123 #define USB0_BASE__INST6_SEG3                      0
1124 #define USB0_BASE__INST6_SEG4                      0
1125 
1126 #define VCN_BASE__INST0_SEG0                       0x00007800
1127 #define VCN_BASE__INST0_SEG1                       0x00007E00
1128 #define VCN_BASE__INST0_SEG2                       0x02403000
1129 #define VCN_BASE__INST0_SEG3                       0
1130 #define VCN_BASE__INST0_SEG4                       0
1131 
1132 #define VCN_BASE__INST1_SEG0                       0x00007B00
1133 #define VCN_BASE__INST1_SEG1                       0x00012000
1134 #define VCN_BASE__INST1_SEG2                       0x02445000
1135 #define VCN_BASE__INST1_SEG3                       0
1136 #define VCN_BASE__INST1_SEG4                       0
1137 
1138 #define VCN_BASE__INST2_SEG0                       0
1139 #define VCN_BASE__INST2_SEG1                       0
1140 #define VCN_BASE__INST2_SEG2                       0
1141 #define VCN_BASE__INST2_SEG3                       0
1142 #define VCN_BASE__INST2_SEG4                       0
1143 
1144 #define VCN_BASE__INST3_SEG0                       0
1145 #define VCN_BASE__INST3_SEG1                       0
1146 #define VCN_BASE__INST3_SEG2                       0
1147 #define VCN_BASE__INST3_SEG3                       0
1148 #define VCN_BASE__INST3_SEG4                       0
1149 
1150 #define VCN_BASE__INST4_SEG0                       0
1151 #define VCN_BASE__INST4_SEG1                       0
1152 #define VCN_BASE__INST4_SEG2                       0
1153 #define VCN_BASE__INST4_SEG3                       0
1154 #define VCN_BASE__INST4_SEG4                       0
1155 
1156 #define VCN_BASE__INST5_SEG0                       0
1157 #define VCN_BASE__INST5_SEG1                       0
1158 #define VCN_BASE__INST5_SEG2                       0
1159 #define VCN_BASE__INST5_SEG3                       0
1160 #define VCN_BASE__INST5_SEG4                       0
1161 
1162 #define VCN_BASE__INST6_SEG0                       0
1163 #define VCN_BASE__INST6_SEG1                       0
1164 #define VCN_BASE__INST6_SEG2                       0
1165 #define VCN_BASE__INST6_SEG3                       0
1166 #define VCN_BASE__INST6_SEG4                       0
1167 
1168 #endif
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