Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright (C) 2019  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _renoir_ip_offset_HEADER
0022 #define _renoir_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                       7
0025 #define MAX_SEGMENT                                        5
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 };
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0 } } } };
0046 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
0047                                         { { 0, 0, 0, 0, 0 } },
0048                                         { { 0, 0, 0, 0, 0 } },
0049                                         { { 0, 0, 0, 0, 0 } },
0050                                         { { 0, 0, 0, 0, 0 } },
0051                                         { { 0, 0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0 } } } };
0053 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
0054                                         { { 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0 } } } };
0060 static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0 } } } };
0067 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0 } } } };
0074 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
0075                                         { { 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0082                                         { { 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0 } } } };
0088 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0089                                         { { 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0 } } } };
0095 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0 } } } };
0102 static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0 } } } };
0109 static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0 } } } };
0116 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
0117                                         { { 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0 } } } };
0130 static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0 } } } };
0137 static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
0138                                         { { 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0 } } } };
0144 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0 } } } };
0151 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
0152                                         { { 0, 0, 0, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0 } } } };
0158 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
0159                                         { { 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0 } } } };
0165 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
0166                                         { { 0, 0, 0, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0 } },
0168                                         { { 0, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0 } } } };
0172 static const struct IP_BASE DCN_BASE   ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
0173                                         { { 0, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0 } },
0175                                         { { 0, 0, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0 } } } };
0177 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0 } },
0179                                         { { 0, 0, 0, 0, 0 } },
0180                                         { { 0, 0, 0, 0, 0 } },
0181                                         { { 0, 0, 0, 0, 0 } },
0182                                         { { 0, 0, 0, 0, 0 } },
0183                                         { { 0, 0, 0, 0, 0 } } } };
0184 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0 } },
0186                                         { { 0, 0, 0, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0 } } } };
0191 static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0 } },
0193                                         { { 0, 0, 0, 0, 0 } },
0194                                         { { 0, 0, 0, 0, 0 } },
0195                                         { { 0, 0, 0, 0, 0 } },
0196                                         { { 0, 0, 0, 0, 0 } },
0197                                         { { 0, 0, 0, 0, 0 } } } };
0198 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
0199                                         { { 0, 0, 0, 0, 0 } },
0200                                         { { 0, 0, 0, 0, 0 } },
0201                                         { { 0, 0, 0, 0, 0 } },
0202                                         { { 0, 0, 0, 0, 0 } },
0203                                         { { 0, 0, 0, 0, 0 } },
0204                                         { { 0, 0, 0, 0, 0 } } } };
0205 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
0206                                         { { 0, 0, 0, 0, 0 } },
0207                                         { { 0, 0, 0, 0, 0 } },
0208                                         { { 0, 0, 0, 0, 0 } },
0209                                         { { 0, 0, 0, 0, 0 } },
0210                                         { { 0, 0, 0, 0, 0 } },
0211                                         { { 0, 0, 0, 0, 0 } } } };
0212 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
0213                                         { { 0x00054000, 0x02425C00, 0, 0, 0 } },
0214                                         { { 0, 0, 0, 0, 0 } },
0215                                         { { 0, 0, 0, 0, 0 } },
0216                                         { { 0, 0, 0, 0, 0 } },
0217                                         { { 0, 0, 0, 0, 0 } },
0218                                         { { 0, 0, 0, 0, 0 } } } };
0219 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
0220                                         { { 0, 0, 0, 0, 0 } },
0221                                         { { 0, 0, 0, 0, 0 } },
0222                                         { { 0, 0, 0, 0, 0 } },
0223                                         { { 0, 0, 0, 0, 0 } },
0224                                         { { 0, 0, 0, 0, 0 } },
0225                                         { { 0, 0, 0, 0, 0 } } } };
0226 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
0227                                         { { 0, 0, 0, 0, 0 } },
0228                                         { { 0, 0, 0, 0, 0 } },
0229                                         { { 0, 0, 0, 0, 0 } },
0230                                         { { 0, 0, 0, 0, 0 } },
0231                                         { { 0, 0, 0, 0, 0 } },
0232                                         { { 0, 0, 0, 0, 0 } } } };
0233 
0234 
0235 #define ACP_BASE__INST0_SEG0                       0x02403800
0236 #define ACP_BASE__INST0_SEG1                       0x00480000
0237 #define ACP_BASE__INST0_SEG2                       0
0238 #define ACP_BASE__INST0_SEG3                       0
0239 #define ACP_BASE__INST0_SEG4                       0
0240 
0241 #define ACP_BASE__INST1_SEG0                       0
0242 #define ACP_BASE__INST1_SEG1                       0
0243 #define ACP_BASE__INST1_SEG2                       0
0244 #define ACP_BASE__INST1_SEG3                       0
0245 #define ACP_BASE__INST1_SEG4                       0
0246 
0247 #define ACP_BASE__INST2_SEG0                       0
0248 #define ACP_BASE__INST2_SEG1                       0
0249 #define ACP_BASE__INST2_SEG2                       0
0250 #define ACP_BASE__INST2_SEG3                       0
0251 #define ACP_BASE__INST2_SEG4                       0
0252 
0253 #define ACP_BASE__INST3_SEG0                       0
0254 #define ACP_BASE__INST3_SEG1                       0
0255 #define ACP_BASE__INST3_SEG2                       0
0256 #define ACP_BASE__INST3_SEG3                       0
0257 #define ACP_BASE__INST3_SEG4                       0
0258 
0259 #define ACP_BASE__INST4_SEG0                       0
0260 #define ACP_BASE__INST4_SEG1                       0
0261 #define ACP_BASE__INST4_SEG2                       0
0262 #define ACP_BASE__INST4_SEG3                       0
0263 #define ACP_BASE__INST4_SEG4                       0
0264 
0265 #define ACP_BASE__INST5_SEG0                       0
0266 #define ACP_BASE__INST5_SEG1                       0
0267 #define ACP_BASE__INST5_SEG2                       0
0268 #define ACP_BASE__INST5_SEG3                       0
0269 #define ACP_BASE__INST5_SEG4                       0
0270 
0271 #define ACP_BASE__INST6_SEG0                       0
0272 #define ACP_BASE__INST6_SEG1                       0
0273 #define ACP_BASE__INST6_SEG2                       0
0274 #define ACP_BASE__INST6_SEG3                       0
0275 #define ACP_BASE__INST6_SEG4                       0
0276 
0277 #define ATHUB_BASE__INST0_SEG0                     0x00000C20
0278 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0279 #define ATHUB_BASE__INST0_SEG2                     0
0280 #define ATHUB_BASE__INST0_SEG3                     0
0281 #define ATHUB_BASE__INST0_SEG4                     0
0282 
0283 #define ATHUB_BASE__INST1_SEG0                     0
0284 #define ATHUB_BASE__INST1_SEG1                     0
0285 #define ATHUB_BASE__INST1_SEG2                     0
0286 #define ATHUB_BASE__INST1_SEG3                     0
0287 #define ATHUB_BASE__INST1_SEG4                     0
0288 
0289 #define ATHUB_BASE__INST2_SEG0                     0
0290 #define ATHUB_BASE__INST2_SEG1                     0
0291 #define ATHUB_BASE__INST2_SEG2                     0
0292 #define ATHUB_BASE__INST2_SEG3                     0
0293 #define ATHUB_BASE__INST2_SEG4                     0
0294 
0295 #define ATHUB_BASE__INST3_SEG0                     0
0296 #define ATHUB_BASE__INST3_SEG1                     0
0297 #define ATHUB_BASE__INST3_SEG2                     0
0298 #define ATHUB_BASE__INST3_SEG3                     0
0299 #define ATHUB_BASE__INST3_SEG4                     0
0300 
0301 #define ATHUB_BASE__INST4_SEG0                     0
0302 #define ATHUB_BASE__INST4_SEG1                     0
0303 #define ATHUB_BASE__INST4_SEG2                     0
0304 #define ATHUB_BASE__INST4_SEG3                     0
0305 #define ATHUB_BASE__INST4_SEG4                     0
0306 
0307 #define ATHUB_BASE__INST5_SEG0                     0
0308 #define ATHUB_BASE__INST5_SEG1                     0
0309 #define ATHUB_BASE__INST5_SEG2                     0
0310 #define ATHUB_BASE__INST5_SEG3                     0
0311 #define ATHUB_BASE__INST5_SEG4                     0
0312 
0313 #define ATHUB_BASE__INST6_SEG0                     0
0314 #define ATHUB_BASE__INST6_SEG1                     0
0315 #define ATHUB_BASE__INST6_SEG2                     0
0316 #define ATHUB_BASE__INST6_SEG3                     0
0317 #define ATHUB_BASE__INST6_SEG4                     0
0318 
0319 #define CLK_BASE__INST0_SEG0                       0x00016C00
0320 #define CLK_BASE__INST0_SEG1                       0x00016E00
0321 #define CLK_BASE__INST0_SEG2                       0x00017000
0322 #define CLK_BASE__INST0_SEG3                       0x00017E00
0323 #define CLK_BASE__INST0_SEG4                       0
0324 
0325 #define CLK_BASE__INST1_SEG0                       0
0326 #define CLK_BASE__INST1_SEG1                       0
0327 #define CLK_BASE__INST1_SEG2                       0
0328 #define CLK_BASE__INST1_SEG3                       0
0329 #define CLK_BASE__INST1_SEG4                       0
0330 
0331 #define CLK_BASE__INST2_SEG0                       0
0332 #define CLK_BASE__INST2_SEG1                       0
0333 #define CLK_BASE__INST2_SEG2                       0
0334 #define CLK_BASE__INST2_SEG3                       0
0335 #define CLK_BASE__INST2_SEG4                       0
0336 
0337 #define CLK_BASE__INST3_SEG0                       0
0338 #define CLK_BASE__INST3_SEG1                       0
0339 #define CLK_BASE__INST3_SEG2                       0
0340 #define CLK_BASE__INST3_SEG3                       0
0341 #define CLK_BASE__INST3_SEG4                       0
0342 
0343 #define CLK_BASE__INST4_SEG0                       0
0344 #define CLK_BASE__INST4_SEG1                       0
0345 #define CLK_BASE__INST4_SEG2                       0
0346 #define CLK_BASE__INST4_SEG3                       0
0347 #define CLK_BASE__INST4_SEG4                       0
0348 
0349 #define CLK_BASE__INST5_SEG0                       0
0350 #define CLK_BASE__INST5_SEG1                       0
0351 #define CLK_BASE__INST5_SEG2                       0
0352 #define CLK_BASE__INST5_SEG3                       0
0353 #define CLK_BASE__INST5_SEG4                       0
0354 
0355 #define CLK_BASE__INST6_SEG0                       0
0356 #define CLK_BASE__INST6_SEG1                       0
0357 #define CLK_BASE__INST6_SEG2                       0
0358 #define CLK_BASE__INST6_SEG3                       0
0359 #define CLK_BASE__INST6_SEG4                       0
0360 
0361 #define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
0362 #define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
0363 #define DBGU_IO0_BASE__INST0_SEG2                  0
0364 #define DBGU_IO0_BASE__INST0_SEG3                  0
0365 #define DBGU_IO0_BASE__INST0_SEG4                  0
0366 
0367 #define DBGU_IO0_BASE__INST1_SEG0                  0
0368 #define DBGU_IO0_BASE__INST1_SEG1                  0
0369 #define DBGU_IO0_BASE__INST1_SEG2                  0
0370 #define DBGU_IO0_BASE__INST1_SEG3                  0
0371 #define DBGU_IO0_BASE__INST1_SEG4                  0
0372 
0373 #define DBGU_IO0_BASE__INST2_SEG0                  0
0374 #define DBGU_IO0_BASE__INST2_SEG1                  0
0375 #define DBGU_IO0_BASE__INST2_SEG2                  0
0376 #define DBGU_IO0_BASE__INST2_SEG3                  0
0377 #define DBGU_IO0_BASE__INST2_SEG4                  0
0378 
0379 #define DBGU_IO0_BASE__INST3_SEG0                  0
0380 #define DBGU_IO0_BASE__INST3_SEG1                  0
0381 #define DBGU_IO0_BASE__INST3_SEG2                  0
0382 #define DBGU_IO0_BASE__INST3_SEG3                  0
0383 #define DBGU_IO0_BASE__INST3_SEG4                  0
0384 
0385 #define DBGU_IO0_BASE__INST4_SEG0                  0
0386 #define DBGU_IO0_BASE__INST4_SEG1                  0
0387 #define DBGU_IO0_BASE__INST4_SEG2                  0
0388 #define DBGU_IO0_BASE__INST4_SEG3                  0
0389 #define DBGU_IO0_BASE__INST4_SEG4                  0
0390 
0391 #define DBGU_IO0_BASE__INST5_SEG0                  0
0392 #define DBGU_IO0_BASE__INST5_SEG1                  0
0393 #define DBGU_IO0_BASE__INST5_SEG2                  0
0394 #define DBGU_IO0_BASE__INST5_SEG3                  0
0395 #define DBGU_IO0_BASE__INST5_SEG4                  0
0396 
0397 #define DBGU_IO0_BASE__INST6_SEG0                  0
0398 #define DBGU_IO0_BASE__INST6_SEG1                  0
0399 #define DBGU_IO0_BASE__INST6_SEG2                  0
0400 #define DBGU_IO0_BASE__INST6_SEG3                  0
0401 #define DBGU_IO0_BASE__INST6_SEG4                  0
0402 
0403 #define DF_BASE__INST0_SEG0                        0x00007000
0404 #define DF_BASE__INST0_SEG1                        0x0240B800
0405 #define DF_BASE__INST0_SEG2                        0
0406 #define DF_BASE__INST0_SEG3                        0
0407 #define DF_BASE__INST0_SEG4                        0
0408 
0409 #define DF_BASE__INST1_SEG0                        0
0410 #define DF_BASE__INST1_SEG1                        0
0411 #define DF_BASE__INST1_SEG2                        0
0412 #define DF_BASE__INST1_SEG3                        0
0413 #define DF_BASE__INST1_SEG4                        0
0414 
0415 #define DF_BASE__INST2_SEG0                        0
0416 #define DF_BASE__INST2_SEG1                        0
0417 #define DF_BASE__INST2_SEG2                        0
0418 #define DF_BASE__INST2_SEG3                        0
0419 #define DF_BASE__INST2_SEG4                        0
0420 
0421 #define DF_BASE__INST3_SEG0                        0
0422 #define DF_BASE__INST3_SEG1                        0
0423 #define DF_BASE__INST3_SEG2                        0
0424 #define DF_BASE__INST3_SEG3                        0
0425 #define DF_BASE__INST3_SEG4                        0
0426 
0427 #define DF_BASE__INST4_SEG0                        0
0428 #define DF_BASE__INST4_SEG1                        0
0429 #define DF_BASE__INST4_SEG2                        0
0430 #define DF_BASE__INST4_SEG3                        0
0431 #define DF_BASE__INST4_SEG4                        0
0432 
0433 #define DF_BASE__INST5_SEG0                        0
0434 #define DF_BASE__INST5_SEG1                        0
0435 #define DF_BASE__INST5_SEG2                        0
0436 #define DF_BASE__INST5_SEG3                        0
0437 #define DF_BASE__INST5_SEG4                        0
0438 
0439 #define DF_BASE__INST6_SEG0                        0
0440 #define DF_BASE__INST6_SEG1                        0
0441 #define DF_BASE__INST6_SEG2                        0
0442 #define DF_BASE__INST6_SEG3                        0
0443 #define DF_BASE__INST6_SEG4                        0
0444 
0445 #define DIO_BASE__INST0_SEG0                       0x02404000
0446 #define DIO_BASE__INST0_SEG1                       0
0447 #define DIO_BASE__INST0_SEG2                       0
0448 #define DIO_BASE__INST0_SEG3                       0
0449 #define DIO_BASE__INST0_SEG4                       0
0450 
0451 #define DIO_BASE__INST1_SEG0                       0
0452 #define DIO_BASE__INST1_SEG1                       0
0453 #define DIO_BASE__INST1_SEG2                       0
0454 #define DIO_BASE__INST1_SEG3                       0
0455 #define DIO_BASE__INST1_SEG4                       0
0456 
0457 #define DIO_BASE__INST2_SEG0                       0
0458 #define DIO_BASE__INST2_SEG1                       0
0459 #define DIO_BASE__INST2_SEG2                       0
0460 #define DIO_BASE__INST2_SEG3                       0
0461 #define DIO_BASE__INST2_SEG4                       0
0462 
0463 #define DIO_BASE__INST3_SEG0                       0
0464 #define DIO_BASE__INST3_SEG1                       0
0465 #define DIO_BASE__INST3_SEG2                       0
0466 #define DIO_BASE__INST3_SEG3                       0
0467 #define DIO_BASE__INST3_SEG4                       0
0468 
0469 #define DIO_BASE__INST4_SEG0                       0
0470 #define DIO_BASE__INST4_SEG1                       0
0471 #define DIO_BASE__INST4_SEG2                       0
0472 #define DIO_BASE__INST4_SEG3                       0
0473 #define DIO_BASE__INST4_SEG4                       0
0474 
0475 #define DIO_BASE__INST5_SEG0                       0
0476 #define DIO_BASE__INST5_SEG1                       0
0477 #define DIO_BASE__INST5_SEG2                       0
0478 #define DIO_BASE__INST5_SEG3                       0
0479 #define DIO_BASE__INST5_SEG4                       0
0480 
0481 #define DIO_BASE__INST6_SEG0                       0
0482 #define DIO_BASE__INST6_SEG1                       0
0483 #define DIO_BASE__INST6_SEG2                       0
0484 #define DIO_BASE__INST6_SEG3                       0
0485 #define DIO_BASE__INST6_SEG4                       0
0486 
0487 #define DMU_BASE__INST0_SEG0                       0x00000012
0488 #define DMU_BASE__INST0_SEG1                       0x000000C0
0489 #define DMU_BASE__INST0_SEG2                       0x000034C0
0490 #define DMU_BASE__INST0_SEG3                       0x00009000
0491 #define DMU_BASE__INST0_SEG4                       0x02403C00
0492 
0493 #define DMU_BASE__INST1_SEG0                       0
0494 #define DMU_BASE__INST1_SEG1                       0
0495 #define DMU_BASE__INST1_SEG2                       0
0496 #define DMU_BASE__INST1_SEG3                       0
0497 #define DMU_BASE__INST1_SEG4                       0
0498 
0499 #define DMU_BASE__INST2_SEG0                       0
0500 #define DMU_BASE__INST2_SEG1                       0
0501 #define DMU_BASE__INST2_SEG2                       0
0502 #define DMU_BASE__INST2_SEG3                       0
0503 #define DMU_BASE__INST2_SEG4                       0
0504 
0505 #define DMU_BASE__INST3_SEG0                       0
0506 #define DMU_BASE__INST3_SEG1                       0
0507 #define DMU_BASE__INST3_SEG2                       0
0508 #define DMU_BASE__INST3_SEG3                       0
0509 #define DMU_BASE__INST3_SEG4                       0
0510 
0511 #define DMU_BASE__INST4_SEG0                       0
0512 #define DMU_BASE__INST4_SEG1                       0
0513 #define DMU_BASE__INST4_SEG2                       0
0514 #define DMU_BASE__INST4_SEG3                       0
0515 #define DMU_BASE__INST4_SEG4                       0
0516 
0517 #define DMU_BASE__INST5_SEG0                       0
0518 #define DMU_BASE__INST5_SEG1                       0
0519 #define DMU_BASE__INST5_SEG2                       0
0520 #define DMU_BASE__INST5_SEG3                       0
0521 #define DMU_BASE__INST5_SEG4                       0
0522 
0523 #define DMU_BASE__INST6_SEG0                       0
0524 #define DMU_BASE__INST6_SEG1                       0
0525 #define DMU_BASE__INST6_SEG2                       0
0526 #define DMU_BASE__INST6_SEG3                       0
0527 #define DMU_BASE__INST6_SEG4                       0
0528 
0529 #define DPCS_BASE__INST0_SEG0                      0x00000012
0530 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0531 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0532 #define DPCS_BASE__INST0_SEG3                      0x00009000
0533 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0534 
0535 #define DPCS_BASE__INST1_SEG0                      0
0536 #define DPCS_BASE__INST1_SEG1                      0
0537 #define DPCS_BASE__INST1_SEG2                      0
0538 #define DPCS_BASE__INST1_SEG3                      0
0539 #define DPCS_BASE__INST1_SEG4                      0
0540 
0541 #define DPCS_BASE__INST2_SEG0                      0
0542 #define DPCS_BASE__INST2_SEG1                      0
0543 #define DPCS_BASE__INST2_SEG2                      0
0544 #define DPCS_BASE__INST2_SEG3                      0
0545 #define DPCS_BASE__INST2_SEG4                      0
0546 
0547 #define DPCS_BASE__INST3_SEG0                      0
0548 #define DPCS_BASE__INST3_SEG1                      0
0549 #define DPCS_BASE__INST3_SEG2                      0
0550 #define DPCS_BASE__INST3_SEG3                      0
0551 #define DPCS_BASE__INST3_SEG4                      0
0552 
0553 #define DPCS_BASE__INST4_SEG0                      0
0554 #define DPCS_BASE__INST4_SEG1                      0
0555 #define DPCS_BASE__INST4_SEG2                      0
0556 #define DPCS_BASE__INST4_SEG3                      0
0557 #define DPCS_BASE__INST4_SEG4                      0
0558 
0559 #define DPCS_BASE__INST5_SEG0                      0
0560 #define DPCS_BASE__INST5_SEG1                      0
0561 #define DPCS_BASE__INST5_SEG2                      0
0562 #define DPCS_BASE__INST5_SEG3                      0
0563 #define DPCS_BASE__INST5_SEG4                      0
0564 
0565 #define DPCS_BASE__INST6_SEG0                      0
0566 #define DPCS_BASE__INST6_SEG1                      0
0567 #define DPCS_BASE__INST6_SEG2                      0
0568 #define DPCS_BASE__INST6_SEG3                      0
0569 #define DPCS_BASE__INST6_SEG4                      0
0570 
0571 #define FUSE_BASE__INST0_SEG0                      0x00017400
0572 #define FUSE_BASE__INST0_SEG1                      0x02401400
0573 #define FUSE_BASE__INST0_SEG2                      0
0574 #define FUSE_BASE__INST0_SEG3                      0
0575 #define FUSE_BASE__INST0_SEG4                      0
0576 
0577 #define FUSE_BASE__INST1_SEG0                      0
0578 #define FUSE_BASE__INST1_SEG1                      0
0579 #define FUSE_BASE__INST1_SEG2                      0
0580 #define FUSE_BASE__INST1_SEG3                      0
0581 #define FUSE_BASE__INST1_SEG4                      0
0582 
0583 #define FUSE_BASE__INST2_SEG0                      0
0584 #define FUSE_BASE__INST2_SEG1                      0
0585 #define FUSE_BASE__INST2_SEG2                      0
0586 #define FUSE_BASE__INST2_SEG3                      0
0587 #define FUSE_BASE__INST2_SEG4                      0
0588 
0589 #define FUSE_BASE__INST3_SEG0                      0
0590 #define FUSE_BASE__INST3_SEG1                      0
0591 #define FUSE_BASE__INST3_SEG2                      0
0592 #define FUSE_BASE__INST3_SEG3                      0
0593 #define FUSE_BASE__INST3_SEG4                      0
0594 
0595 #define FUSE_BASE__INST4_SEG0                      0
0596 #define FUSE_BASE__INST4_SEG1                      0
0597 #define FUSE_BASE__INST4_SEG2                      0
0598 #define FUSE_BASE__INST4_SEG3                      0
0599 #define FUSE_BASE__INST4_SEG4                      0
0600 
0601 #define FUSE_BASE__INST5_SEG0                      0
0602 #define FUSE_BASE__INST5_SEG1                      0
0603 #define FUSE_BASE__INST5_SEG2                      0
0604 #define FUSE_BASE__INST5_SEG3                      0
0605 #define FUSE_BASE__INST5_SEG4                      0
0606 
0607 #define FUSE_BASE__INST6_SEG0                      0
0608 #define FUSE_BASE__INST6_SEG1                      0
0609 #define FUSE_BASE__INST6_SEG2                      0
0610 #define FUSE_BASE__INST6_SEG3                      0
0611 #define FUSE_BASE__INST6_SEG4                      0
0612 
0613 #define GC_BASE__INST0_SEG0                        0x00002000
0614 #define GC_BASE__INST0_SEG1                        0x0000A000
0615 #define GC_BASE__INST0_SEG2                        0x02402C00
0616 #define GC_BASE__INST0_SEG3                        0
0617 #define GC_BASE__INST0_SEG4                        0
0618 
0619 #define GC_BASE__INST1_SEG0                        0
0620 #define GC_BASE__INST1_SEG1                        0
0621 #define GC_BASE__INST1_SEG2                        0
0622 #define GC_BASE__INST1_SEG3                        0
0623 #define GC_BASE__INST1_SEG4                        0
0624 
0625 #define GC_BASE__INST2_SEG0                        0
0626 #define GC_BASE__INST2_SEG1                        0
0627 #define GC_BASE__INST2_SEG2                        0
0628 #define GC_BASE__INST2_SEG3                        0
0629 #define GC_BASE__INST2_SEG4                        0
0630 
0631 #define GC_BASE__INST3_SEG0                        0
0632 #define GC_BASE__INST3_SEG1                        0
0633 #define GC_BASE__INST3_SEG2                        0
0634 #define GC_BASE__INST3_SEG3                        0
0635 #define GC_BASE__INST3_SEG4                        0
0636 
0637 #define GC_BASE__INST4_SEG0                        0
0638 #define GC_BASE__INST4_SEG1                        0
0639 #define GC_BASE__INST4_SEG2                        0
0640 #define GC_BASE__INST4_SEG3                        0
0641 #define GC_BASE__INST4_SEG4                        0
0642 
0643 #define GC_BASE__INST5_SEG0                        0
0644 #define GC_BASE__INST5_SEG1                        0
0645 #define GC_BASE__INST5_SEG2                        0
0646 #define GC_BASE__INST5_SEG3                        0
0647 #define GC_BASE__INST5_SEG4                        0
0648 
0649 #define GC_BASE__INST6_SEG0                        0
0650 #define GC_BASE__INST6_SEG1                        0
0651 #define GC_BASE__INST6_SEG2                        0
0652 #define GC_BASE__INST6_SEG3                        0
0653 #define GC_BASE__INST6_SEG4                        0
0654 
0655 #define HDA_BASE__INST0_SEG0                       0x02404800
0656 #define HDA_BASE__INST0_SEG1                       0x004C0000
0657 #define HDA_BASE__INST0_SEG2                       0
0658 #define HDA_BASE__INST0_SEG3                       0
0659 #define HDA_BASE__INST0_SEG4                       0
0660 
0661 #define HDA_BASE__INST1_SEG0                       0
0662 #define HDA_BASE__INST1_SEG1                       0
0663 #define HDA_BASE__INST1_SEG2                       0
0664 #define HDA_BASE__INST1_SEG3                       0
0665 #define HDA_BASE__INST1_SEG4                       0
0666 
0667 #define HDA_BASE__INST2_SEG0                       0
0668 #define HDA_BASE__INST2_SEG1                       0
0669 #define HDA_BASE__INST2_SEG2                       0
0670 #define HDA_BASE__INST2_SEG3                       0
0671 #define HDA_BASE__INST2_SEG4                       0
0672 
0673 #define HDA_BASE__INST3_SEG0                       0
0674 #define HDA_BASE__INST3_SEG1                       0
0675 #define HDA_BASE__INST3_SEG2                       0
0676 #define HDA_BASE__INST3_SEG3                       0
0677 #define HDA_BASE__INST3_SEG4                       0
0678 
0679 #define HDA_BASE__INST4_SEG0                       0
0680 #define HDA_BASE__INST4_SEG1                       0
0681 #define HDA_BASE__INST4_SEG2                       0
0682 #define HDA_BASE__INST4_SEG3                       0
0683 #define HDA_BASE__INST4_SEG4                       0
0684 
0685 #define HDA_BASE__INST5_SEG0                       0
0686 #define HDA_BASE__INST5_SEG1                       0
0687 #define HDA_BASE__INST5_SEG2                       0
0688 #define HDA_BASE__INST5_SEG3                       0
0689 #define HDA_BASE__INST5_SEG4                       0
0690 
0691 #define HDA_BASE__INST6_SEG0                       0
0692 #define HDA_BASE__INST6_SEG1                       0
0693 #define HDA_BASE__INST6_SEG2                       0
0694 #define HDA_BASE__INST6_SEG3                       0
0695 #define HDA_BASE__INST6_SEG4                       0
0696 
0697 #define HDP_BASE__INST0_SEG0                       0x00000F20
0698 #define HDP_BASE__INST0_SEG1                       0x0240A400
0699 #define HDP_BASE__INST0_SEG2                       0
0700 #define HDP_BASE__INST0_SEG3                       0
0701 #define HDP_BASE__INST0_SEG4                       0
0702 
0703 #define HDP_BASE__INST1_SEG0                       0
0704 #define HDP_BASE__INST1_SEG1                       0
0705 #define HDP_BASE__INST1_SEG2                       0
0706 #define HDP_BASE__INST1_SEG3                       0
0707 #define HDP_BASE__INST1_SEG4                       0
0708 
0709 #define HDP_BASE__INST2_SEG0                       0
0710 #define HDP_BASE__INST2_SEG1                       0
0711 #define HDP_BASE__INST2_SEG2                       0
0712 #define HDP_BASE__INST2_SEG3                       0
0713 #define HDP_BASE__INST2_SEG4                       0
0714 
0715 #define HDP_BASE__INST3_SEG0                       0
0716 #define HDP_BASE__INST3_SEG1                       0
0717 #define HDP_BASE__INST3_SEG2                       0
0718 #define HDP_BASE__INST3_SEG3                       0
0719 #define HDP_BASE__INST3_SEG4                       0
0720 
0721 #define HDP_BASE__INST4_SEG0                       0
0722 #define HDP_BASE__INST4_SEG1                       0
0723 #define HDP_BASE__INST4_SEG2                       0
0724 #define HDP_BASE__INST4_SEG3                       0
0725 #define HDP_BASE__INST4_SEG4                       0
0726 
0727 #define HDP_BASE__INST5_SEG0                       0
0728 #define HDP_BASE__INST5_SEG1                       0
0729 #define HDP_BASE__INST5_SEG2                       0
0730 #define HDP_BASE__INST5_SEG3                       0
0731 #define HDP_BASE__INST5_SEG4                       0
0732 
0733 #define HDP_BASE__INST6_SEG0                       0
0734 #define HDP_BASE__INST6_SEG1                       0
0735 #define HDP_BASE__INST6_SEG2                       0
0736 #define HDP_BASE__INST6_SEG3                       0
0737 #define HDP_BASE__INST6_SEG4                       0
0738 
0739 #define IOHC0_BASE__INST0_SEG0                     0x00010000
0740 #define IOHC0_BASE__INST0_SEG1                     0x02406000
0741 #define IOHC0_BASE__INST0_SEG2                     0x04EC0000
0742 #define IOHC0_BASE__INST0_SEG3                     0
0743 #define IOHC0_BASE__INST0_SEG4                     0
0744 
0745 #define IOHC0_BASE__INST1_SEG0                     0
0746 #define IOHC0_BASE__INST1_SEG1                     0
0747 #define IOHC0_BASE__INST1_SEG2                     0
0748 #define IOHC0_BASE__INST1_SEG3                     0
0749 #define IOHC0_BASE__INST1_SEG4                     0
0750 
0751 #define IOHC0_BASE__INST2_SEG0                     0
0752 #define IOHC0_BASE__INST2_SEG1                     0
0753 #define IOHC0_BASE__INST2_SEG2                     0
0754 #define IOHC0_BASE__INST2_SEG3                     0
0755 #define IOHC0_BASE__INST2_SEG4                     0
0756 
0757 #define IOHC0_BASE__INST3_SEG0                     0
0758 #define IOHC0_BASE__INST3_SEG1                     0
0759 #define IOHC0_BASE__INST3_SEG2                     0
0760 #define IOHC0_BASE__INST3_SEG3                     0
0761 #define IOHC0_BASE__INST3_SEG4                     0
0762 
0763 #define IOHC0_BASE__INST4_SEG0                     0
0764 #define IOHC0_BASE__INST4_SEG1                     0
0765 #define IOHC0_BASE__INST4_SEG2                     0
0766 #define IOHC0_BASE__INST4_SEG3                     0
0767 #define IOHC0_BASE__INST4_SEG4                     0
0768 
0769 #define IOHC0_BASE__INST5_SEG0                     0
0770 #define IOHC0_BASE__INST5_SEG1                     0
0771 #define IOHC0_BASE__INST5_SEG2                     0
0772 #define IOHC0_BASE__INST5_SEG3                     0
0773 #define IOHC0_BASE__INST5_SEG4                     0
0774 
0775 #define IOHC0_BASE__INST6_SEG0                     0
0776 #define IOHC0_BASE__INST6_SEG1                     0
0777 #define IOHC0_BASE__INST6_SEG2                     0
0778 #define IOHC0_BASE__INST6_SEG3                     0
0779 #define IOHC0_BASE__INST6_SEG4                     0
0780 
0781 #define ISP_BASE__INST0_SEG0                       0x00018000
0782 #define ISP_BASE__INST0_SEG1                       0x0240B000
0783 #define ISP_BASE__INST0_SEG2                       0
0784 #define ISP_BASE__INST0_SEG3                       0
0785 #define ISP_BASE__INST0_SEG4                       0
0786 
0787 #define ISP_BASE__INST1_SEG0                       0
0788 #define ISP_BASE__INST1_SEG1                       0
0789 #define ISP_BASE__INST1_SEG2                       0
0790 #define ISP_BASE__INST1_SEG3                       0
0791 #define ISP_BASE__INST1_SEG4                       0
0792 
0793 #define ISP_BASE__INST2_SEG0                       0
0794 #define ISP_BASE__INST2_SEG1                       0
0795 #define ISP_BASE__INST2_SEG2                       0
0796 #define ISP_BASE__INST2_SEG3                       0
0797 #define ISP_BASE__INST2_SEG4                       0
0798 
0799 #define ISP_BASE__INST3_SEG0                       0
0800 #define ISP_BASE__INST3_SEG1                       0
0801 #define ISP_BASE__INST3_SEG2                       0
0802 #define ISP_BASE__INST3_SEG3                       0
0803 #define ISP_BASE__INST3_SEG4                       0
0804 
0805 #define ISP_BASE__INST4_SEG0                       0
0806 #define ISP_BASE__INST4_SEG1                       0
0807 #define ISP_BASE__INST4_SEG2                       0
0808 #define ISP_BASE__INST4_SEG3                       0
0809 #define ISP_BASE__INST4_SEG4                       0
0810 
0811 #define ISP_BASE__INST5_SEG0                       0
0812 #define ISP_BASE__INST5_SEG1                       0
0813 #define ISP_BASE__INST5_SEG2                       0
0814 #define ISP_BASE__INST5_SEG3                       0
0815 #define ISP_BASE__INST5_SEG4                       0
0816 
0817 #define ISP_BASE__INST6_SEG0                       0
0818 #define ISP_BASE__INST6_SEG1                       0
0819 #define ISP_BASE__INST6_SEG2                       0
0820 #define ISP_BASE__INST6_SEG3                       0
0821 #define ISP_BASE__INST6_SEG4                       0
0822 
0823 #define L2IMU0_BASE__INST0_SEG0                    0x00007DC0
0824 #define L2IMU0_BASE__INST0_SEG1                    0x02407000
0825 #define L2IMU0_BASE__INST0_SEG2                    0x00900000
0826 #define L2IMU0_BASE__INST0_SEG3                    0x04FC0000
0827 #define L2IMU0_BASE__INST0_SEG4                    0x055C0000
0828 
0829 #define L2IMU0_BASE__INST1_SEG0                    0
0830 #define L2IMU0_BASE__INST1_SEG1                    0
0831 #define L2IMU0_BASE__INST1_SEG2                    0
0832 #define L2IMU0_BASE__INST1_SEG3                    0
0833 #define L2IMU0_BASE__INST1_SEG4                    0
0834 
0835 #define L2IMU0_BASE__INST2_SEG0                    0
0836 #define L2IMU0_BASE__INST2_SEG1                    0
0837 #define L2IMU0_BASE__INST2_SEG2                    0
0838 #define L2IMU0_BASE__INST2_SEG3                    0
0839 #define L2IMU0_BASE__INST2_SEG4                    0
0840 
0841 #define L2IMU0_BASE__INST3_SEG0                    0
0842 #define L2IMU0_BASE__INST3_SEG1                    0
0843 #define L2IMU0_BASE__INST3_SEG2                    0
0844 #define L2IMU0_BASE__INST3_SEG3                    0
0845 #define L2IMU0_BASE__INST3_SEG4                    0
0846 
0847 #define L2IMU0_BASE__INST4_SEG0                    0
0848 #define L2IMU0_BASE__INST4_SEG1                    0
0849 #define L2IMU0_BASE__INST4_SEG2                    0
0850 #define L2IMU0_BASE__INST4_SEG3                    0
0851 #define L2IMU0_BASE__INST4_SEG4                    0
0852 
0853 #define L2IMU0_BASE__INST5_SEG0                    0
0854 #define L2IMU0_BASE__INST5_SEG1                    0
0855 #define L2IMU0_BASE__INST5_SEG2                    0
0856 #define L2IMU0_BASE__INST5_SEG3                    0
0857 #define L2IMU0_BASE__INST5_SEG4                    0
0858 
0859 #define L2IMU0_BASE__INST6_SEG0                    0
0860 #define L2IMU0_BASE__INST6_SEG1                    0
0861 #define L2IMU0_BASE__INST6_SEG2                    0
0862 #define L2IMU0_BASE__INST6_SEG3                    0
0863 #define L2IMU0_BASE__INST6_SEG4                    0
0864 
0865 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0866 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0867 #define MMHUB_BASE__INST0_SEG2                     0
0868 #define MMHUB_BASE__INST0_SEG3                     0
0869 #define MMHUB_BASE__INST0_SEG4                     0
0870 
0871 #define MMHUB_BASE__INST1_SEG0                     0
0872 #define MMHUB_BASE__INST1_SEG1                     0
0873 #define MMHUB_BASE__INST1_SEG2                     0
0874 #define MMHUB_BASE__INST1_SEG3                     0
0875 #define MMHUB_BASE__INST1_SEG4                     0
0876 
0877 #define MMHUB_BASE__INST2_SEG0                     0
0878 #define MMHUB_BASE__INST2_SEG1                     0
0879 #define MMHUB_BASE__INST2_SEG2                     0
0880 #define MMHUB_BASE__INST2_SEG3                     0
0881 #define MMHUB_BASE__INST2_SEG4                     0
0882 
0883 #define MMHUB_BASE__INST3_SEG0                     0
0884 #define MMHUB_BASE__INST3_SEG1                     0
0885 #define MMHUB_BASE__INST3_SEG2                     0
0886 #define MMHUB_BASE__INST3_SEG3                     0
0887 #define MMHUB_BASE__INST3_SEG4                     0
0888 
0889 #define MMHUB_BASE__INST4_SEG0                     0
0890 #define MMHUB_BASE__INST4_SEG1                     0
0891 #define MMHUB_BASE__INST4_SEG2                     0
0892 #define MMHUB_BASE__INST4_SEG3                     0
0893 #define MMHUB_BASE__INST4_SEG4                     0
0894 
0895 #define MMHUB_BASE__INST5_SEG0                     0
0896 #define MMHUB_BASE__INST5_SEG1                     0
0897 #define MMHUB_BASE__INST5_SEG2                     0
0898 #define MMHUB_BASE__INST5_SEG3                     0
0899 #define MMHUB_BASE__INST5_SEG4                     0
0900 
0901 #define MMHUB_BASE__INST6_SEG0                     0
0902 #define MMHUB_BASE__INST6_SEG1                     0
0903 #define MMHUB_BASE__INST6_SEG2                     0
0904 #define MMHUB_BASE__INST6_SEG3                     0
0905 #define MMHUB_BASE__INST6_SEG4                     0
0906 
0907 #define MP0_BASE__INST0_SEG0                       0x00016000
0908 #define MP0_BASE__INST0_SEG1                       0x0243FC00
0909 #define MP0_BASE__INST0_SEG2                       0x00DC0000
0910 #define MP0_BASE__INST0_SEG3                       0x00E00000
0911 #define MP0_BASE__INST0_SEG4                       0x00E40000
0912 
0913 #define MP0_BASE__INST1_SEG0                       0
0914 #define MP0_BASE__INST1_SEG1                       0
0915 #define MP0_BASE__INST1_SEG2                       0
0916 #define MP0_BASE__INST1_SEG3                       0
0917 #define MP0_BASE__INST1_SEG4                       0
0918 
0919 #define MP0_BASE__INST2_SEG0                       0
0920 #define MP0_BASE__INST2_SEG1                       0
0921 #define MP0_BASE__INST2_SEG2                       0
0922 #define MP0_BASE__INST2_SEG3                       0
0923 #define MP0_BASE__INST2_SEG4                       0
0924 
0925 #define MP0_BASE__INST3_SEG0                       0
0926 #define MP0_BASE__INST3_SEG1                       0
0927 #define MP0_BASE__INST3_SEG2                       0
0928 #define MP0_BASE__INST3_SEG3                       0
0929 #define MP0_BASE__INST3_SEG4                       0
0930 
0931 #define MP0_BASE__INST4_SEG0                       0
0932 #define MP0_BASE__INST4_SEG1                       0
0933 #define MP0_BASE__INST4_SEG2                       0
0934 #define MP0_BASE__INST4_SEG3                       0
0935 #define MP0_BASE__INST4_SEG4                       0
0936 
0937 #define MP0_BASE__INST5_SEG0                       0
0938 #define MP0_BASE__INST5_SEG1                       0
0939 #define MP0_BASE__INST5_SEG2                       0
0940 #define MP0_BASE__INST5_SEG3                       0
0941 #define MP0_BASE__INST5_SEG4                       0
0942 
0943 #define MP0_BASE__INST6_SEG0                       0
0944 #define MP0_BASE__INST6_SEG1                       0
0945 #define MP0_BASE__INST6_SEG2                       0
0946 #define MP0_BASE__INST6_SEG3                       0
0947 #define MP0_BASE__INST6_SEG4                       0
0948 
0949 #define MP1_BASE__INST0_SEG0                       0x00016200
0950 #define MP1_BASE__INST0_SEG1                       0x02400400
0951 #define MP1_BASE__INST0_SEG2                       0x00E80000
0952 #define MP1_BASE__INST0_SEG3                       0x00EC0000
0953 #define MP1_BASE__INST0_SEG4                       0x00F00000
0954 
0955 #define MP1_BASE__INST1_SEG0                       0
0956 #define MP1_BASE__INST1_SEG1                       0
0957 #define MP1_BASE__INST1_SEG2                       0
0958 #define MP1_BASE__INST1_SEG3                       0
0959 #define MP1_BASE__INST1_SEG4                       0
0960 
0961 #define MP1_BASE__INST2_SEG0                       0
0962 #define MP1_BASE__INST2_SEG1                       0
0963 #define MP1_BASE__INST2_SEG2                       0
0964 #define MP1_BASE__INST2_SEG3                       0
0965 #define MP1_BASE__INST2_SEG4                       0
0966 
0967 #define MP1_BASE__INST3_SEG0                       0
0968 #define MP1_BASE__INST3_SEG1                       0
0969 #define MP1_BASE__INST3_SEG2                       0
0970 #define MP1_BASE__INST3_SEG3                       0
0971 #define MP1_BASE__INST3_SEG4                       0
0972 
0973 #define MP1_BASE__INST4_SEG0                       0
0974 #define MP1_BASE__INST4_SEG1                       0
0975 #define MP1_BASE__INST4_SEG2                       0
0976 #define MP1_BASE__INST4_SEG3                       0
0977 #define MP1_BASE__INST4_SEG4                       0
0978 
0979 #define MP1_BASE__INST5_SEG0                       0
0980 #define MP1_BASE__INST5_SEG1                       0
0981 #define MP1_BASE__INST5_SEG2                       0
0982 #define MP1_BASE__INST5_SEG3                       0
0983 #define MP1_BASE__INST5_SEG4                       0
0984 
0985 #define MP1_BASE__INST6_SEG0                       0
0986 #define MP1_BASE__INST6_SEG1                       0
0987 #define MP1_BASE__INST6_SEG2                       0
0988 #define MP1_BASE__INST6_SEG3                       0
0989 #define MP1_BASE__INST6_SEG4                       0
0990 
0991 #define NBIF0_BASE__INST0_SEG0                     0x00000000
0992 #define NBIF0_BASE__INST0_SEG1                     0x00000014
0993 #define NBIF0_BASE__INST0_SEG2                     0x00000D20
0994 #define NBIF0_BASE__INST0_SEG3                     0x00010400
0995 #define NBIF0_BASE__INST0_SEG4                     0x0241B000
0996 
0997 #define NBIF0_BASE__INST1_SEG0                     0
0998 #define NBIF0_BASE__INST1_SEG1                     0
0999 #define NBIF0_BASE__INST1_SEG2                     0
1000 #define NBIF0_BASE__INST1_SEG3                     0
1001 #define NBIF0_BASE__INST1_SEG4                     0
1002 
1003 #define NBIF0_BASE__INST2_SEG0                     0
1004 #define NBIF0_BASE__INST2_SEG1                     0
1005 #define NBIF0_BASE__INST2_SEG2                     0
1006 #define NBIF0_BASE__INST2_SEG3                     0
1007 #define NBIF0_BASE__INST2_SEG4                     0
1008 
1009 #define NBIF0_BASE__INST3_SEG0                     0
1010 #define NBIF0_BASE__INST3_SEG1                     0
1011 #define NBIF0_BASE__INST3_SEG2                     0
1012 #define NBIF0_BASE__INST3_SEG3                     0
1013 #define NBIF0_BASE__INST3_SEG4                     0
1014 
1015 #define NBIF0_BASE__INST4_SEG0                     0
1016 #define NBIF0_BASE__INST4_SEG1                     0
1017 #define NBIF0_BASE__INST4_SEG2                     0
1018 #define NBIF0_BASE__INST4_SEG3                     0
1019 #define NBIF0_BASE__INST4_SEG4                     0
1020 
1021 #define NBIF0_BASE__INST5_SEG0                     0
1022 #define NBIF0_BASE__INST5_SEG1                     0
1023 #define NBIF0_BASE__INST5_SEG2                     0
1024 #define NBIF0_BASE__INST5_SEG3                     0
1025 #define NBIF0_BASE__INST5_SEG4                     0
1026 
1027 #define NBIF0_BASE__INST6_SEG0                     0
1028 #define NBIF0_BASE__INST6_SEG1                     0
1029 #define NBIF0_BASE__INST6_SEG2                     0
1030 #define NBIF0_BASE__INST6_SEG3                     0
1031 #define NBIF0_BASE__INST6_SEG4                     0
1032 
1033 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
1034 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
1035 #define OSSSYS_BASE__INST0_SEG2                    0
1036 #define OSSSYS_BASE__INST0_SEG3                    0
1037 #define OSSSYS_BASE__INST0_SEG4                    0
1038 
1039 #define OSSSYS_BASE__INST1_SEG0                    0
1040 #define OSSSYS_BASE__INST1_SEG1                    0
1041 #define OSSSYS_BASE__INST1_SEG2                    0
1042 #define OSSSYS_BASE__INST1_SEG3                    0
1043 #define OSSSYS_BASE__INST1_SEG4                    0
1044 
1045 #define OSSSYS_BASE__INST2_SEG0                    0
1046 #define OSSSYS_BASE__INST2_SEG1                    0
1047 #define OSSSYS_BASE__INST2_SEG2                    0
1048 #define OSSSYS_BASE__INST2_SEG3                    0
1049 #define OSSSYS_BASE__INST2_SEG4                    0
1050 
1051 #define OSSSYS_BASE__INST3_SEG0                    0
1052 #define OSSSYS_BASE__INST3_SEG1                    0
1053 #define OSSSYS_BASE__INST3_SEG2                    0
1054 #define OSSSYS_BASE__INST3_SEG3                    0
1055 #define OSSSYS_BASE__INST3_SEG4                    0
1056 
1057 #define OSSSYS_BASE__INST4_SEG0                    0
1058 #define OSSSYS_BASE__INST4_SEG1                    0
1059 #define OSSSYS_BASE__INST4_SEG2                    0
1060 #define OSSSYS_BASE__INST4_SEG3                    0
1061 #define OSSSYS_BASE__INST4_SEG4                    0
1062 
1063 #define OSSSYS_BASE__INST5_SEG0                    0
1064 #define OSSSYS_BASE__INST5_SEG1                    0
1065 #define OSSSYS_BASE__INST5_SEG2                    0
1066 #define OSSSYS_BASE__INST5_SEG3                    0
1067 #define OSSSYS_BASE__INST5_SEG4                    0
1068 
1069 #define OSSSYS_BASE__INST6_SEG0                    0
1070 #define OSSSYS_BASE__INST6_SEG1                    0
1071 #define OSSSYS_BASE__INST6_SEG2                    0
1072 #define OSSSYS_BASE__INST6_SEG3                    0
1073 #define OSSSYS_BASE__INST6_SEG4                    0
1074 
1075 #define PCIE0_BASE__INST0_SEG0                     0x02411800
1076 #define PCIE0_BASE__INST0_SEG1                     0x04440000
1077 #define PCIE0_BASE__INST0_SEG2                     0
1078 #define PCIE0_BASE__INST0_SEG3                     0
1079 #define PCIE0_BASE__INST0_SEG4                     0
1080 
1081 #define PCIE0_BASE__INST1_SEG0                     0
1082 #define PCIE0_BASE__INST1_SEG1                     0
1083 #define PCIE0_BASE__INST1_SEG2                     0
1084 #define PCIE0_BASE__INST1_SEG3                     0
1085 #define PCIE0_BASE__INST1_SEG4                     0
1086 
1087 #define PCIE0_BASE__INST2_SEG0                     0
1088 #define PCIE0_BASE__INST2_SEG1                     0
1089 #define PCIE0_BASE__INST2_SEG2                     0
1090 #define PCIE0_BASE__INST2_SEG3                     0
1091 #define PCIE0_BASE__INST2_SEG4                     0
1092 
1093 #define PCIE0_BASE__INST3_SEG0                     0
1094 #define PCIE0_BASE__INST3_SEG1                     0
1095 #define PCIE0_BASE__INST3_SEG2                     0
1096 #define PCIE0_BASE__INST3_SEG3                     0
1097 #define PCIE0_BASE__INST3_SEG4                     0
1098 
1099 #define PCIE0_BASE__INST4_SEG0                     0
1100 #define PCIE0_BASE__INST4_SEG1                     0
1101 #define PCIE0_BASE__INST4_SEG2                     0
1102 #define PCIE0_BASE__INST4_SEG3                     0
1103 #define PCIE0_BASE__INST4_SEG4                     0
1104 
1105 #define PCIE0_BASE__INST5_SEG0                     0
1106 #define PCIE0_BASE__INST5_SEG1                     0
1107 #define PCIE0_BASE__INST5_SEG2                     0
1108 #define PCIE0_BASE__INST5_SEG3                     0
1109 #define PCIE0_BASE__INST5_SEG4                     0
1110 
1111 #define PCIE0_BASE__INST6_SEG0                     0
1112 #define PCIE0_BASE__INST6_SEG1                     0
1113 #define PCIE0_BASE__INST6_SEG2                     0
1114 #define PCIE0_BASE__INST6_SEG3                     0
1115 #define PCIE0_BASE__INST6_SEG4                     0
1116 
1117 #define SDMA0_BASE__INST0_SEG0                     0x00001260
1118 #define SDMA0_BASE__INST0_SEG1                     0x0240A800
1119 #define SDMA0_BASE__INST0_SEG2                     0
1120 #define SDMA0_BASE__INST0_SEG3                     0
1121 #define SDMA0_BASE__INST0_SEG4                     0
1122 
1123 #define SDMA0_BASE__INST1_SEG0                     0
1124 #define SDMA0_BASE__INST1_SEG1                     0
1125 #define SDMA0_BASE__INST1_SEG2                     0
1126 #define SDMA0_BASE__INST1_SEG3                     0
1127 #define SDMA0_BASE__INST1_SEG4                     0
1128 
1129 #define SDMA0_BASE__INST2_SEG0                     0
1130 #define SDMA0_BASE__INST2_SEG1                     0
1131 #define SDMA0_BASE__INST2_SEG2                     0
1132 #define SDMA0_BASE__INST2_SEG3                     0
1133 #define SDMA0_BASE__INST2_SEG4                     0
1134 
1135 #define SDMA0_BASE__INST3_SEG0                     0
1136 #define SDMA0_BASE__INST3_SEG1                     0
1137 #define SDMA0_BASE__INST3_SEG2                     0
1138 #define SDMA0_BASE__INST3_SEG3                     0
1139 #define SDMA0_BASE__INST3_SEG4                     0
1140 
1141 #define SDMA0_BASE__INST4_SEG0                     0
1142 #define SDMA0_BASE__INST4_SEG1                     0
1143 #define SDMA0_BASE__INST4_SEG2                     0
1144 #define SDMA0_BASE__INST4_SEG3                     0
1145 #define SDMA0_BASE__INST4_SEG4                     0
1146 
1147 #define SDMA0_BASE__INST5_SEG0                     0
1148 #define SDMA0_BASE__INST5_SEG1                     0
1149 #define SDMA0_BASE__INST5_SEG2                     0
1150 #define SDMA0_BASE__INST5_SEG3                     0
1151 #define SDMA0_BASE__INST5_SEG4                     0
1152 
1153 #define SDMA0_BASE__INST6_SEG0                     0
1154 #define SDMA0_BASE__INST6_SEG1                     0
1155 #define SDMA0_BASE__INST6_SEG2                     0
1156 #define SDMA0_BASE__INST6_SEG3                     0
1157 #define SDMA0_BASE__INST6_SEG4                     0
1158 
1159 #define SMUIO_BASE__INST0_SEG0                     0x00016800
1160 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
1161 #define SMUIO_BASE__INST0_SEG2                     0x02401000
1162 #define SMUIO_BASE__INST0_SEG3                     0x00440000
1163 #define SMUIO_BASE__INST0_SEG4                     0
1164 
1165 #define SMUIO_BASE__INST1_SEG0                     0
1166 #define SMUIO_BASE__INST1_SEG1                     0
1167 #define SMUIO_BASE__INST1_SEG2                     0
1168 #define SMUIO_BASE__INST1_SEG3                     0
1169 #define SMUIO_BASE__INST1_SEG4                     0
1170 
1171 #define SMUIO_BASE__INST2_SEG0                     0
1172 #define SMUIO_BASE__INST2_SEG1                     0
1173 #define SMUIO_BASE__INST2_SEG2                     0
1174 #define SMUIO_BASE__INST2_SEG3                     0
1175 #define SMUIO_BASE__INST2_SEG4                     0
1176 
1177 #define SMUIO_BASE__INST3_SEG0                     0
1178 #define SMUIO_BASE__INST3_SEG1                     0
1179 #define SMUIO_BASE__INST3_SEG2                     0
1180 #define SMUIO_BASE__INST3_SEG3                     0
1181 #define SMUIO_BASE__INST3_SEG4                     0
1182 
1183 #define SMUIO_BASE__INST4_SEG0                     0
1184 #define SMUIO_BASE__INST4_SEG1                     0
1185 #define SMUIO_BASE__INST4_SEG2                     0
1186 #define SMUIO_BASE__INST4_SEG3                     0
1187 #define SMUIO_BASE__INST4_SEG4                     0
1188 
1189 #define SMUIO_BASE__INST5_SEG0                     0
1190 #define SMUIO_BASE__INST5_SEG1                     0
1191 #define SMUIO_BASE__INST5_SEG2                     0
1192 #define SMUIO_BASE__INST5_SEG3                     0
1193 #define SMUIO_BASE__INST5_SEG4                     0
1194 
1195 #define SMUIO_BASE__INST6_SEG0                     0
1196 #define SMUIO_BASE__INST6_SEG1                     0
1197 #define SMUIO_BASE__INST6_SEG2                     0
1198 #define SMUIO_BASE__INST6_SEG3                     0
1199 #define SMUIO_BASE__INST6_SEG4                     0
1200 
1201 #define THM_BASE__INST0_SEG0                       0x00016600
1202 #define THM_BASE__INST0_SEG1                       0x02400C00
1203 #define THM_BASE__INST0_SEG2                       0
1204 #define THM_BASE__INST0_SEG3                       0
1205 #define THM_BASE__INST0_SEG4                       0
1206 
1207 #define THM_BASE__INST1_SEG0                       0
1208 #define THM_BASE__INST1_SEG1                       0
1209 #define THM_BASE__INST1_SEG2                       0
1210 #define THM_BASE__INST1_SEG3                       0
1211 #define THM_BASE__INST1_SEG4                       0
1212 
1213 #define THM_BASE__INST2_SEG0                       0
1214 #define THM_BASE__INST2_SEG1                       0
1215 #define THM_BASE__INST2_SEG2                       0
1216 #define THM_BASE__INST2_SEG3                       0
1217 #define THM_BASE__INST2_SEG4                       0
1218 
1219 #define THM_BASE__INST3_SEG0                       0
1220 #define THM_BASE__INST3_SEG1                       0
1221 #define THM_BASE__INST3_SEG2                       0
1222 #define THM_BASE__INST3_SEG3                       0
1223 #define THM_BASE__INST3_SEG4                       0
1224 
1225 #define THM_BASE__INST4_SEG0                       0
1226 #define THM_BASE__INST4_SEG1                       0
1227 #define THM_BASE__INST4_SEG2                       0
1228 #define THM_BASE__INST4_SEG3                       0
1229 #define THM_BASE__INST4_SEG4                       0
1230 
1231 #define THM_BASE__INST5_SEG0                       0
1232 #define THM_BASE__INST5_SEG1                       0
1233 #define THM_BASE__INST5_SEG2                       0
1234 #define THM_BASE__INST5_SEG3                       0
1235 #define THM_BASE__INST5_SEG4                       0
1236 
1237 #define THM_BASE__INST6_SEG0                       0
1238 #define THM_BASE__INST6_SEG1                       0
1239 #define THM_BASE__INST6_SEG2                       0
1240 #define THM_BASE__INST6_SEG3                       0
1241 #define THM_BASE__INST6_SEG4                       0
1242 
1243 #define UMC_BASE__INST0_SEG0                       0x00014000
1244 #define UMC_BASE__INST0_SEG1                       0x02425800
1245 #define UMC_BASE__INST0_SEG2                       0
1246 #define UMC_BASE__INST0_SEG3                       0
1247 #define UMC_BASE__INST0_SEG4                       0
1248 
1249 #define UMC_BASE__INST1_SEG0                       0x00054000
1250 #define UMC_BASE__INST1_SEG1                       0x02425C00
1251 #define UMC_BASE__INST1_SEG2                       0
1252 #define UMC_BASE__INST1_SEG3                       0
1253 #define UMC_BASE__INST1_SEG4                       0
1254 
1255 #define UMC_BASE__INST2_SEG0                       0
1256 #define UMC_BASE__INST2_SEG1                       0
1257 #define UMC_BASE__INST2_SEG2                       0
1258 #define UMC_BASE__INST2_SEG3                       0
1259 #define UMC_BASE__INST2_SEG4                       0
1260 
1261 #define UMC_BASE__INST3_SEG0                       0
1262 #define UMC_BASE__INST3_SEG1                       0
1263 #define UMC_BASE__INST3_SEG2                       0
1264 #define UMC_BASE__INST3_SEG3                       0
1265 #define UMC_BASE__INST3_SEG4                       0
1266 
1267 #define UMC_BASE__INST4_SEG0                       0
1268 #define UMC_BASE__INST4_SEG1                       0
1269 #define UMC_BASE__INST4_SEG2                       0
1270 #define UMC_BASE__INST4_SEG3                       0
1271 #define UMC_BASE__INST4_SEG4                       0
1272 
1273 #define UMC_BASE__INST5_SEG0                       0
1274 #define UMC_BASE__INST5_SEG1                       0
1275 #define UMC_BASE__INST5_SEG2                       0
1276 #define UMC_BASE__INST5_SEG3                       0
1277 #define UMC_BASE__INST5_SEG4                       0
1278 
1279 #define UMC_BASE__INST6_SEG0                       0
1280 #define UMC_BASE__INST6_SEG1                       0
1281 #define UMC_BASE__INST6_SEG2                       0
1282 #define UMC_BASE__INST6_SEG3                       0
1283 #define UMC_BASE__INST6_SEG4                       0
1284 
1285 #define USB0_BASE__INST0_SEG0                      0x0242A800
1286 #define USB0_BASE__INST0_SEG1                      0x05B00000
1287 #define USB0_BASE__INST0_SEG2                      0
1288 #define USB0_BASE__INST0_SEG3                      0
1289 #define USB0_BASE__INST0_SEG4                      0
1290 
1291 #define USB0_BASE__INST1_SEG0                      0
1292 #define USB0_BASE__INST1_SEG1                      0
1293 #define USB0_BASE__INST1_SEG2                      0
1294 #define USB0_BASE__INST1_SEG3                      0
1295 #define USB0_BASE__INST1_SEG4                      0
1296 
1297 #define USB0_BASE__INST2_SEG0                      0
1298 #define USB0_BASE__INST2_SEG1                      0
1299 #define USB0_BASE__INST2_SEG2                      0
1300 #define USB0_BASE__INST2_SEG3                      0
1301 #define USB0_BASE__INST2_SEG4                      0
1302 
1303 #define USB0_BASE__INST3_SEG0                      0
1304 #define USB0_BASE__INST3_SEG1                      0
1305 #define USB0_BASE__INST3_SEG2                      0
1306 #define USB0_BASE__INST3_SEG3                      0
1307 #define USB0_BASE__INST3_SEG4                      0
1308 
1309 #define USB0_BASE__INST4_SEG0                      0
1310 #define USB0_BASE__INST4_SEG1                      0
1311 #define USB0_BASE__INST4_SEG2                      0
1312 #define USB0_BASE__INST4_SEG3                      0
1313 #define USB0_BASE__INST4_SEG4                      0
1314 
1315 #define USB0_BASE__INST5_SEG0                      0
1316 #define USB0_BASE__INST5_SEG1                      0
1317 #define USB0_BASE__INST5_SEG2                      0
1318 #define USB0_BASE__INST5_SEG3                      0
1319 #define USB0_BASE__INST5_SEG4                      0
1320 
1321 #define USB0_BASE__INST6_SEG0                      0
1322 #define USB0_BASE__INST6_SEG1                      0
1323 #define USB0_BASE__INST6_SEG2                      0
1324 #define USB0_BASE__INST6_SEG3                      0
1325 #define USB0_BASE__INST6_SEG4                      0
1326 
1327 #define UVD0_BASE__INST0_SEG0                      0x00007800
1328 #define UVD0_BASE__INST0_SEG1                      0x00007E00
1329 #define UVD0_BASE__INST0_SEG2                      0x02403000
1330 #define UVD0_BASE__INST0_SEG3                      0
1331 #define UVD0_BASE__INST0_SEG4                      0
1332 
1333 #define UVD0_BASE__INST1_SEG0                      0
1334 #define UVD0_BASE__INST1_SEG1                      0
1335 #define UVD0_BASE__INST1_SEG2                      0
1336 #define UVD0_BASE__INST1_SEG3                      0
1337 #define UVD0_BASE__INST1_SEG4                      0
1338 
1339 #define UVD0_BASE__INST2_SEG0                      0
1340 #define UVD0_BASE__INST2_SEG1                      0
1341 #define UVD0_BASE__INST2_SEG2                      0
1342 #define UVD0_BASE__INST2_SEG3                      0
1343 #define UVD0_BASE__INST2_SEG4                      0
1344 
1345 #define UVD0_BASE__INST3_SEG0                      0
1346 #define UVD0_BASE__INST3_SEG1                      0
1347 #define UVD0_BASE__INST3_SEG2                      0
1348 #define UVD0_BASE__INST3_SEG3                      0
1349 #define UVD0_BASE__INST3_SEG4                      0
1350 
1351 #define UVD0_BASE__INST4_SEG0                      0
1352 #define UVD0_BASE__INST4_SEG1                      0
1353 #define UVD0_BASE__INST4_SEG2                      0
1354 #define UVD0_BASE__INST4_SEG3                      0
1355 #define UVD0_BASE__INST4_SEG4                      0
1356 
1357 #define UVD0_BASE__INST5_SEG0                      0
1358 #define UVD0_BASE__INST5_SEG1                      0
1359 #define UVD0_BASE__INST5_SEG2                      0
1360 #define UVD0_BASE__INST5_SEG3                      0
1361 #define UVD0_BASE__INST5_SEG4                      0
1362 
1363 #define UVD0_BASE__INST6_SEG0                      0
1364 #define UVD0_BASE__INST6_SEG1                      0
1365 #define UVD0_BASE__INST6_SEG2                      0
1366 #define UVD0_BASE__INST6_SEG3                      0
1367 #define UVD0_BASE__INST6_SEG4                      0
1368 
1369 #define DCN_BASE__INST0_SEG0                      0x00000012
1370 #define DCN_BASE__INST0_SEG1                      0x000000C0
1371 #define DCN_BASE__INST0_SEG2                      0x000034C0
1372 #define DCN_BASE__INST0_SEG3                      0
1373 #define DCN_BASE__INST0_SEG4                      0
1374 
1375 #define DCN_BASE__INST1_SEG0                      0
1376 #define DCN_BASE__INST1_SEG1                      0
1377 #define DCN_BASE__INST1_SEG2                      0
1378 #define DCN_BASE__INST1_SEG3                      0
1379 #define DCN_BASE__INST1_SEG4                      0
1380 
1381 #define DCN_BASE__INST2_SEG0                      0
1382 #define DCN_BASE__INST2_SEG1                      0
1383 #define DCN_BASE__INST2_SEG2                      0
1384 #define DCN_BASE__INST2_SEG3                      0
1385 #define DCN_BASE__INST2_SEG4                      0
1386 
1387 #define DCN_BASE__INST3_SEG0                      0
1388 #define DCN_BASE__INST3_SEG1                      0
1389 #define DCN_BASE__INST3_SEG2                      0
1390 #define DCN_BASE__INST3_SEG3                      0
1391 #define DCN_BASE__INST3_SEG4                      0
1392 
1393 #define DCN_BASE__INST4_SEG0                      0
1394 #define DCN_BASE__INST4_SEG1                      0
1395 #define DCN_BASE__INST4_SEG2                      0
1396 #define DCN_BASE__INST4_SEG3                      0
1397 #define DCN_BASE__INST4_SEG4                      0
1398 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!