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0001 /*
0002  * Copyright (C) 2019  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _navi12_ip_offset_HEADER
0022 #define _navi12_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                       7
0025 #define MAX_SEGMENT                                        5
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 };
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0 } } } };
0046 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
0047                                         { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
0048                                         { { 0x00017000, 0x02402000, 0, 0, 0 } },
0049                                         { { 0x00017200, 0x02402400, 0, 0, 0 } },
0050                                         { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
0051                                         { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0 } } } };
0053 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0 } } } };
0060 static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0 } } } };
0067 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0068                                         { { 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0 } } } };
0074 static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
0075                                         { { 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0 } } } };
0088 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0 } } } };
0095 static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0 } } } };
0102 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0 } } } };
0109 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0 } } } };
0116 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
0117                                         { { 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
0124                                         { { 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0 } } } };
0130 static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
0131                                         { { 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0 } } } };
0137 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0 } } } };
0144 static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0 } } } };
0151 static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
0152                                         { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0 } } } };
0158 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
0159                                         { { 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0 } } } };
0165 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
0166                                         { { 0, 0, 0, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0 } },
0168                                         { { 0, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0 } } } };
0172 static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
0173                                         { { 0x00054000, 0x02425C00, 0, 0, 0 } },
0174                                         { { 0x00094000, 0x02426000, 0, 0, 0 } },
0175                                         { { 0x000D4000, 0x02426400, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0 } } } };
0179 static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
0180                                         { { 0, 0, 0, 0, 0 } },
0181                                         { { 0, 0, 0, 0, 0 } },
0182                                         { { 0, 0, 0, 0, 0 } },
0183                                         { { 0, 0, 0, 0, 0 } },
0184                                         { { 0, 0, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0 } } } };
0186 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0 } },
0191                                         { { 0, 0, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0 } } } };
0193 
0194 
0195 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0196 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0197 #define ATHUB_BASE__INST0_SEG2                     0
0198 #define ATHUB_BASE__INST0_SEG3                     0
0199 #define ATHUB_BASE__INST0_SEG4                     0
0200 
0201 #define ATHUB_BASE__INST1_SEG0                     0
0202 #define ATHUB_BASE__INST1_SEG1                     0
0203 #define ATHUB_BASE__INST1_SEG2                     0
0204 #define ATHUB_BASE__INST1_SEG3                     0
0205 #define ATHUB_BASE__INST1_SEG4                     0
0206 
0207 #define ATHUB_BASE__INST2_SEG0                     0
0208 #define ATHUB_BASE__INST2_SEG1                     0
0209 #define ATHUB_BASE__INST2_SEG2                     0
0210 #define ATHUB_BASE__INST2_SEG3                     0
0211 #define ATHUB_BASE__INST2_SEG4                     0
0212 
0213 #define ATHUB_BASE__INST3_SEG0                     0
0214 #define ATHUB_BASE__INST3_SEG1                     0
0215 #define ATHUB_BASE__INST3_SEG2                     0
0216 #define ATHUB_BASE__INST3_SEG3                     0
0217 #define ATHUB_BASE__INST3_SEG4                     0
0218 
0219 #define ATHUB_BASE__INST4_SEG0                     0
0220 #define ATHUB_BASE__INST4_SEG1                     0
0221 #define ATHUB_BASE__INST4_SEG2                     0
0222 #define ATHUB_BASE__INST4_SEG3                     0
0223 #define ATHUB_BASE__INST4_SEG4                     0
0224 
0225 #define ATHUB_BASE__INST5_SEG0                     0
0226 #define ATHUB_BASE__INST5_SEG1                     0
0227 #define ATHUB_BASE__INST5_SEG2                     0
0228 #define ATHUB_BASE__INST5_SEG3                     0
0229 #define ATHUB_BASE__INST5_SEG4                     0
0230 
0231 #define ATHUB_BASE__INST6_SEG0                     0
0232 #define ATHUB_BASE__INST6_SEG1                     0
0233 #define ATHUB_BASE__INST6_SEG2                     0
0234 #define ATHUB_BASE__INST6_SEG3                     0
0235 #define ATHUB_BASE__INST6_SEG4                     0
0236 
0237 #define CLK_BASE__INST0_SEG0                       0x00016C00
0238 #define CLK_BASE__INST0_SEG1                       0x02401800
0239 #define CLK_BASE__INST0_SEG2                       0
0240 #define CLK_BASE__INST0_SEG3                       0
0241 #define CLK_BASE__INST0_SEG4                       0
0242 
0243 #define CLK_BASE__INST1_SEG0                       0x00016E00
0244 #define CLK_BASE__INST1_SEG1                       0x02401C00
0245 #define CLK_BASE__INST1_SEG2                       0
0246 #define CLK_BASE__INST1_SEG3                       0
0247 #define CLK_BASE__INST1_SEG4                       0
0248 
0249 #define CLK_BASE__INST2_SEG0                       0x00017000
0250 #define CLK_BASE__INST2_SEG1                       0x02402000
0251 #define CLK_BASE__INST2_SEG2                       0
0252 #define CLK_BASE__INST2_SEG3                       0
0253 #define CLK_BASE__INST2_SEG4                       0
0254 
0255 #define CLK_BASE__INST3_SEG0                       0x00017200
0256 #define CLK_BASE__INST3_SEG1                       0x02402400
0257 #define CLK_BASE__INST3_SEG2                       0
0258 #define CLK_BASE__INST3_SEG3                       0
0259 #define CLK_BASE__INST3_SEG4                       0
0260 
0261 #define CLK_BASE__INST4_SEG0                       0x0001B000
0262 #define CLK_BASE__INST4_SEG1                       0x0242D800
0263 #define CLK_BASE__INST4_SEG2                       0
0264 #define CLK_BASE__INST4_SEG3                       0
0265 #define CLK_BASE__INST4_SEG4                       0
0266 
0267 #define CLK_BASE__INST5_SEG0                       0x00017E00
0268 #define CLK_BASE__INST5_SEG1                       0x0240BC00
0269 #define CLK_BASE__INST5_SEG2                       0
0270 #define CLK_BASE__INST5_SEG3                       0
0271 #define CLK_BASE__INST5_SEG4                       0
0272 
0273 #define CLK_BASE__INST6_SEG0                       0
0274 #define CLK_BASE__INST6_SEG1                       0
0275 #define CLK_BASE__INST6_SEG2                       0
0276 #define CLK_BASE__INST6_SEG3                       0
0277 #define CLK_BASE__INST6_SEG4                       0
0278 
0279 #define DF_BASE__INST0_SEG0                        0x00007000
0280 #define DF_BASE__INST0_SEG1                        0x0240B800
0281 #define DF_BASE__INST0_SEG2                        0
0282 #define DF_BASE__INST0_SEG3                        0
0283 #define DF_BASE__INST0_SEG4                        0
0284 
0285 #define DF_BASE__INST1_SEG0                        0
0286 #define DF_BASE__INST1_SEG1                        0
0287 #define DF_BASE__INST1_SEG2                        0
0288 #define DF_BASE__INST1_SEG3                        0
0289 #define DF_BASE__INST1_SEG4                        0
0290 
0291 #define DF_BASE__INST2_SEG0                        0
0292 #define DF_BASE__INST2_SEG1                        0
0293 #define DF_BASE__INST2_SEG2                        0
0294 #define DF_BASE__INST2_SEG3                        0
0295 #define DF_BASE__INST2_SEG4                        0
0296 
0297 #define DF_BASE__INST3_SEG0                        0
0298 #define DF_BASE__INST3_SEG1                        0
0299 #define DF_BASE__INST3_SEG2                        0
0300 #define DF_BASE__INST3_SEG3                        0
0301 #define DF_BASE__INST3_SEG4                        0
0302 
0303 #define DF_BASE__INST4_SEG0                        0
0304 #define DF_BASE__INST4_SEG1                        0
0305 #define DF_BASE__INST4_SEG2                        0
0306 #define DF_BASE__INST4_SEG3                        0
0307 #define DF_BASE__INST4_SEG4                        0
0308 
0309 #define DF_BASE__INST5_SEG0                        0
0310 #define DF_BASE__INST5_SEG1                        0
0311 #define DF_BASE__INST5_SEG2                        0
0312 #define DF_BASE__INST5_SEG3                        0
0313 #define DF_BASE__INST5_SEG4                        0
0314 
0315 #define DF_BASE__INST6_SEG0                        0
0316 #define DF_BASE__INST6_SEG1                        0
0317 #define DF_BASE__INST6_SEG2                        0
0318 #define DF_BASE__INST6_SEG3                        0
0319 #define DF_BASE__INST6_SEG4                        0
0320 
0321 #define DIO_BASE__INST0_SEG0                       0x02404000
0322 #define DIO_BASE__INST0_SEG1                       0
0323 #define DIO_BASE__INST0_SEG2                       0
0324 #define DIO_BASE__INST0_SEG3                       0
0325 #define DIO_BASE__INST0_SEG4                       0
0326 
0327 #define DIO_BASE__INST1_SEG0                       0
0328 #define DIO_BASE__INST1_SEG1                       0
0329 #define DIO_BASE__INST1_SEG2                       0
0330 #define DIO_BASE__INST1_SEG3                       0
0331 #define DIO_BASE__INST1_SEG4                       0
0332 
0333 #define DIO_BASE__INST2_SEG0                       0
0334 #define DIO_BASE__INST2_SEG1                       0
0335 #define DIO_BASE__INST2_SEG2                       0
0336 #define DIO_BASE__INST2_SEG3                       0
0337 #define DIO_BASE__INST2_SEG4                       0
0338 
0339 #define DIO_BASE__INST3_SEG0                       0
0340 #define DIO_BASE__INST3_SEG1                       0
0341 #define DIO_BASE__INST3_SEG2                       0
0342 #define DIO_BASE__INST3_SEG3                       0
0343 #define DIO_BASE__INST3_SEG4                       0
0344 
0345 #define DIO_BASE__INST4_SEG0                       0
0346 #define DIO_BASE__INST4_SEG1                       0
0347 #define DIO_BASE__INST4_SEG2                       0
0348 #define DIO_BASE__INST4_SEG3                       0
0349 #define DIO_BASE__INST4_SEG4                       0
0350 
0351 #define DIO_BASE__INST5_SEG0                       0
0352 #define DIO_BASE__INST5_SEG1                       0
0353 #define DIO_BASE__INST5_SEG2                       0
0354 #define DIO_BASE__INST5_SEG3                       0
0355 #define DIO_BASE__INST5_SEG4                       0
0356 
0357 #define DIO_BASE__INST6_SEG0                       0
0358 #define DIO_BASE__INST6_SEG1                       0
0359 #define DIO_BASE__INST6_SEG2                       0
0360 #define DIO_BASE__INST6_SEG3                       0
0361 #define DIO_BASE__INST6_SEG4                       0
0362 
0363 #define DMU_BASE__INST0_SEG0                       0x00000012
0364 #define DMU_BASE__INST0_SEG1                       0x000000C0
0365 #define DMU_BASE__INST0_SEG2                       0x000034C0
0366 #define DMU_BASE__INST0_SEG3                       0x00009000
0367 #define DMU_BASE__INST0_SEG4                       0x02403C00
0368 
0369 #define DMU_BASE__INST1_SEG0                       0
0370 #define DMU_BASE__INST1_SEG1                       0
0371 #define DMU_BASE__INST1_SEG2                       0
0372 #define DMU_BASE__INST1_SEG3                       0
0373 #define DMU_BASE__INST1_SEG4                       0
0374 
0375 #define DMU_BASE__INST2_SEG0                       0
0376 #define DMU_BASE__INST2_SEG1                       0
0377 #define DMU_BASE__INST2_SEG2                       0
0378 #define DMU_BASE__INST2_SEG3                       0
0379 #define DMU_BASE__INST2_SEG4                       0
0380 
0381 #define DMU_BASE__INST3_SEG0                       0
0382 #define DMU_BASE__INST3_SEG1                       0
0383 #define DMU_BASE__INST3_SEG2                       0
0384 #define DMU_BASE__INST3_SEG3                       0
0385 #define DMU_BASE__INST3_SEG4                       0
0386 
0387 #define DMU_BASE__INST4_SEG0                       0
0388 #define DMU_BASE__INST4_SEG1                       0
0389 #define DMU_BASE__INST4_SEG2                       0
0390 #define DMU_BASE__INST4_SEG3                       0
0391 #define DMU_BASE__INST4_SEG4                       0
0392 
0393 #define DMU_BASE__INST5_SEG0                       0
0394 #define DMU_BASE__INST5_SEG1                       0
0395 #define DMU_BASE__INST5_SEG2                       0
0396 #define DMU_BASE__INST5_SEG3                       0
0397 #define DMU_BASE__INST5_SEG4                       0
0398 
0399 #define DMU_BASE__INST6_SEG0                       0
0400 #define DMU_BASE__INST6_SEG1                       0
0401 #define DMU_BASE__INST6_SEG2                       0
0402 #define DMU_BASE__INST6_SEG3                       0
0403 #define DMU_BASE__INST6_SEG4                       0
0404 
0405 #define DPCS_BASE__INST0_SEG0                      0x00000012
0406 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0407 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0408 #define DPCS_BASE__INST0_SEG3                      0x00009000
0409 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0410 
0411 #define DPCS_BASE__INST1_SEG0                      0
0412 #define DPCS_BASE__INST1_SEG1                      0
0413 #define DPCS_BASE__INST1_SEG2                      0
0414 #define DPCS_BASE__INST1_SEG3                      0
0415 #define DPCS_BASE__INST1_SEG4                      0
0416 
0417 #define DPCS_BASE__INST2_SEG0                      0
0418 #define DPCS_BASE__INST2_SEG1                      0
0419 #define DPCS_BASE__INST2_SEG2                      0
0420 #define DPCS_BASE__INST2_SEG3                      0
0421 #define DPCS_BASE__INST2_SEG4                      0
0422 
0423 #define DPCS_BASE__INST3_SEG0                      0
0424 #define DPCS_BASE__INST3_SEG1                      0
0425 #define DPCS_BASE__INST3_SEG2                      0
0426 #define DPCS_BASE__INST3_SEG3                      0
0427 #define DPCS_BASE__INST3_SEG4                      0
0428 
0429 #define DPCS_BASE__INST4_SEG0                      0
0430 #define DPCS_BASE__INST4_SEG1                      0
0431 #define DPCS_BASE__INST4_SEG2                      0
0432 #define DPCS_BASE__INST4_SEG3                      0
0433 #define DPCS_BASE__INST4_SEG4                      0
0434 
0435 #define DPCS_BASE__INST5_SEG0                      0
0436 #define DPCS_BASE__INST5_SEG1                      0
0437 #define DPCS_BASE__INST5_SEG2                      0
0438 #define DPCS_BASE__INST5_SEG3                      0
0439 #define DPCS_BASE__INST5_SEG4                      0
0440 
0441 #define DPCS_BASE__INST6_SEG0                      0
0442 #define DPCS_BASE__INST6_SEG1                      0
0443 #define DPCS_BASE__INST6_SEG2                      0
0444 #define DPCS_BASE__INST6_SEG3                      0
0445 #define DPCS_BASE__INST6_SEG4                      0
0446 
0447 #define FUSE_BASE__INST0_SEG0                      0x00017400
0448 #define FUSE_BASE__INST0_SEG1                      0x02401400
0449 #define FUSE_BASE__INST0_SEG2                      0
0450 #define FUSE_BASE__INST0_SEG3                      0
0451 #define FUSE_BASE__INST0_SEG4                      0
0452 
0453 #define FUSE_BASE__INST1_SEG0                      0
0454 #define FUSE_BASE__INST1_SEG1                      0
0455 #define FUSE_BASE__INST1_SEG2                      0
0456 #define FUSE_BASE__INST1_SEG3                      0
0457 #define FUSE_BASE__INST1_SEG4                      0
0458 
0459 #define FUSE_BASE__INST2_SEG0                      0
0460 #define FUSE_BASE__INST2_SEG1                      0
0461 #define FUSE_BASE__INST2_SEG2                      0
0462 #define FUSE_BASE__INST2_SEG3                      0
0463 #define FUSE_BASE__INST2_SEG4                      0
0464 
0465 #define FUSE_BASE__INST3_SEG0                      0
0466 #define FUSE_BASE__INST3_SEG1                      0
0467 #define FUSE_BASE__INST3_SEG2                      0
0468 #define FUSE_BASE__INST3_SEG3                      0
0469 #define FUSE_BASE__INST3_SEG4                      0
0470 
0471 #define FUSE_BASE__INST4_SEG0                      0
0472 #define FUSE_BASE__INST4_SEG1                      0
0473 #define FUSE_BASE__INST4_SEG2                      0
0474 #define FUSE_BASE__INST4_SEG3                      0
0475 #define FUSE_BASE__INST4_SEG4                      0
0476 
0477 #define FUSE_BASE__INST5_SEG0                      0
0478 #define FUSE_BASE__INST5_SEG1                      0
0479 #define FUSE_BASE__INST5_SEG2                      0
0480 #define FUSE_BASE__INST5_SEG3                      0
0481 #define FUSE_BASE__INST5_SEG4                      0
0482 
0483 #define FUSE_BASE__INST6_SEG0                      0
0484 #define FUSE_BASE__INST6_SEG1                      0
0485 #define FUSE_BASE__INST6_SEG2                      0
0486 #define FUSE_BASE__INST6_SEG3                      0
0487 #define FUSE_BASE__INST6_SEG4                      0
0488 
0489 #define GC_BASE__INST0_SEG0                        0x00001260
0490 #define GC_BASE__INST0_SEG1                        0x0000A000
0491 #define GC_BASE__INST0_SEG2                        0x02402C00
0492 #define GC_BASE__INST0_SEG3                        0
0493 #define GC_BASE__INST0_SEG4                        0
0494 
0495 #define GC_BASE__INST1_SEG0                        0
0496 #define GC_BASE__INST1_SEG1                        0
0497 #define GC_BASE__INST1_SEG2                        0
0498 #define GC_BASE__INST1_SEG3                        0
0499 #define GC_BASE__INST1_SEG4                        0
0500 
0501 #define GC_BASE__INST2_SEG0                        0
0502 #define GC_BASE__INST2_SEG1                        0
0503 #define GC_BASE__INST2_SEG2                        0
0504 #define GC_BASE__INST2_SEG3                        0
0505 #define GC_BASE__INST2_SEG4                        0
0506 
0507 #define GC_BASE__INST3_SEG0                        0
0508 #define GC_BASE__INST3_SEG1                        0
0509 #define GC_BASE__INST3_SEG2                        0
0510 #define GC_BASE__INST3_SEG3                        0
0511 #define GC_BASE__INST3_SEG4                        0
0512 
0513 #define GC_BASE__INST4_SEG0                        0
0514 #define GC_BASE__INST4_SEG1                        0
0515 #define GC_BASE__INST4_SEG2                        0
0516 #define GC_BASE__INST4_SEG3                        0
0517 #define GC_BASE__INST4_SEG4                        0
0518 
0519 #define GC_BASE__INST5_SEG0                        0
0520 #define GC_BASE__INST5_SEG1                        0
0521 #define GC_BASE__INST5_SEG2                        0
0522 #define GC_BASE__INST5_SEG3                        0
0523 #define GC_BASE__INST5_SEG4                        0
0524 
0525 #define GC_BASE__INST6_SEG0                        0
0526 #define GC_BASE__INST6_SEG1                        0
0527 #define GC_BASE__INST6_SEG2                        0
0528 #define GC_BASE__INST6_SEG3                        0
0529 #define GC_BASE__INST6_SEG4                        0
0530 
0531 #define HDA_BASE__INST0_SEG0                       0x004C0000
0532 #define HDA_BASE__INST0_SEG1                       0x02404800
0533 #define HDA_BASE__INST0_SEG2                       0
0534 #define HDA_BASE__INST0_SEG3                       0
0535 #define HDA_BASE__INST0_SEG4                       0
0536 
0537 #define HDA_BASE__INST1_SEG0                       0
0538 #define HDA_BASE__INST1_SEG1                       0
0539 #define HDA_BASE__INST1_SEG2                       0
0540 #define HDA_BASE__INST1_SEG3                       0
0541 #define HDA_BASE__INST1_SEG4                       0
0542 
0543 #define HDA_BASE__INST2_SEG0                       0
0544 #define HDA_BASE__INST2_SEG1                       0
0545 #define HDA_BASE__INST2_SEG2                       0
0546 #define HDA_BASE__INST2_SEG3                       0
0547 #define HDA_BASE__INST2_SEG4                       0
0548 
0549 #define HDA_BASE__INST3_SEG0                       0
0550 #define HDA_BASE__INST3_SEG1                       0
0551 #define HDA_BASE__INST3_SEG2                       0
0552 #define HDA_BASE__INST3_SEG3                       0
0553 #define HDA_BASE__INST3_SEG4                       0
0554 
0555 #define HDA_BASE__INST4_SEG0                       0
0556 #define HDA_BASE__INST4_SEG1                       0
0557 #define HDA_BASE__INST4_SEG2                       0
0558 #define HDA_BASE__INST4_SEG3                       0
0559 #define HDA_BASE__INST4_SEG4                       0
0560 
0561 #define HDA_BASE__INST5_SEG0                       0
0562 #define HDA_BASE__INST5_SEG1                       0
0563 #define HDA_BASE__INST5_SEG2                       0
0564 #define HDA_BASE__INST5_SEG3                       0
0565 #define HDA_BASE__INST5_SEG4                       0
0566 
0567 #define HDA_BASE__INST6_SEG0                       0
0568 #define HDA_BASE__INST6_SEG1                       0
0569 #define HDA_BASE__INST6_SEG2                       0
0570 #define HDA_BASE__INST6_SEG3                       0
0571 #define HDA_BASE__INST6_SEG4                       0
0572 
0573 #define HDP_BASE__INST0_SEG0                       0x00000F20
0574 #define HDP_BASE__INST0_SEG1                       0x0240A400
0575 #define HDP_BASE__INST0_SEG2                       0
0576 #define HDP_BASE__INST0_SEG3                       0
0577 #define HDP_BASE__INST0_SEG4                       0
0578 
0579 #define HDP_BASE__INST1_SEG0                       0
0580 #define HDP_BASE__INST1_SEG1                       0
0581 #define HDP_BASE__INST1_SEG2                       0
0582 #define HDP_BASE__INST1_SEG3                       0
0583 #define HDP_BASE__INST1_SEG4                       0
0584 
0585 #define HDP_BASE__INST2_SEG0                       0
0586 #define HDP_BASE__INST2_SEG1                       0
0587 #define HDP_BASE__INST2_SEG2                       0
0588 #define HDP_BASE__INST2_SEG3                       0
0589 #define HDP_BASE__INST2_SEG4                       0
0590 
0591 #define HDP_BASE__INST3_SEG0                       0
0592 #define HDP_BASE__INST3_SEG1                       0
0593 #define HDP_BASE__INST3_SEG2                       0
0594 #define HDP_BASE__INST3_SEG3                       0
0595 #define HDP_BASE__INST3_SEG4                       0
0596 
0597 #define HDP_BASE__INST4_SEG0                       0
0598 #define HDP_BASE__INST4_SEG1                       0
0599 #define HDP_BASE__INST4_SEG2                       0
0600 #define HDP_BASE__INST4_SEG3                       0
0601 #define HDP_BASE__INST4_SEG4                       0
0602 
0603 #define HDP_BASE__INST5_SEG0                       0
0604 #define HDP_BASE__INST5_SEG1                       0
0605 #define HDP_BASE__INST5_SEG2                       0
0606 #define HDP_BASE__INST5_SEG3                       0
0607 #define HDP_BASE__INST5_SEG4                       0
0608 
0609 #define HDP_BASE__INST6_SEG0                       0
0610 #define HDP_BASE__INST6_SEG1                       0
0611 #define HDP_BASE__INST6_SEG2                       0
0612 #define HDP_BASE__INST6_SEG3                       0
0613 #define HDP_BASE__INST6_SEG4                       0
0614 
0615 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0616 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0617 #define MMHUB_BASE__INST0_SEG2                     0
0618 #define MMHUB_BASE__INST0_SEG3                     0
0619 #define MMHUB_BASE__INST0_SEG4                     0
0620 
0621 #define MMHUB_BASE__INST1_SEG0                     0
0622 #define MMHUB_BASE__INST1_SEG1                     0
0623 #define MMHUB_BASE__INST1_SEG2                     0
0624 #define MMHUB_BASE__INST1_SEG3                     0
0625 #define MMHUB_BASE__INST1_SEG4                     0
0626 
0627 #define MMHUB_BASE__INST2_SEG0                     0
0628 #define MMHUB_BASE__INST2_SEG1                     0
0629 #define MMHUB_BASE__INST2_SEG2                     0
0630 #define MMHUB_BASE__INST2_SEG3                     0
0631 #define MMHUB_BASE__INST2_SEG4                     0
0632 
0633 #define MMHUB_BASE__INST3_SEG0                     0
0634 #define MMHUB_BASE__INST3_SEG1                     0
0635 #define MMHUB_BASE__INST3_SEG2                     0
0636 #define MMHUB_BASE__INST3_SEG3                     0
0637 #define MMHUB_BASE__INST3_SEG4                     0
0638 
0639 #define MMHUB_BASE__INST4_SEG0                     0
0640 #define MMHUB_BASE__INST4_SEG1                     0
0641 #define MMHUB_BASE__INST4_SEG2                     0
0642 #define MMHUB_BASE__INST4_SEG3                     0
0643 #define MMHUB_BASE__INST4_SEG4                     0
0644 
0645 #define MMHUB_BASE__INST5_SEG0                     0
0646 #define MMHUB_BASE__INST5_SEG1                     0
0647 #define MMHUB_BASE__INST5_SEG2                     0
0648 #define MMHUB_BASE__INST5_SEG3                     0
0649 #define MMHUB_BASE__INST5_SEG4                     0
0650 
0651 #define MMHUB_BASE__INST6_SEG0                     0
0652 #define MMHUB_BASE__INST6_SEG1                     0
0653 #define MMHUB_BASE__INST6_SEG2                     0
0654 #define MMHUB_BASE__INST6_SEG3                     0
0655 #define MMHUB_BASE__INST6_SEG4                     0
0656 
0657 #define MP0_BASE__INST0_SEG0                       0x00016000
0658 #define MP0_BASE__INST0_SEG1                       0x00DC0000
0659 #define MP0_BASE__INST0_SEG2                       0x00E00000
0660 #define MP0_BASE__INST0_SEG3                       0x00E40000
0661 #define MP0_BASE__INST0_SEG4                       0x0243FC00
0662 
0663 #define MP0_BASE__INST1_SEG0                       0
0664 #define MP0_BASE__INST1_SEG1                       0
0665 #define MP0_BASE__INST1_SEG2                       0
0666 #define MP0_BASE__INST1_SEG3                       0
0667 #define MP0_BASE__INST1_SEG4                       0
0668 
0669 #define MP0_BASE__INST2_SEG0                       0
0670 #define MP0_BASE__INST2_SEG1                       0
0671 #define MP0_BASE__INST2_SEG2                       0
0672 #define MP0_BASE__INST2_SEG3                       0
0673 #define MP0_BASE__INST2_SEG4                       0
0674 
0675 #define MP0_BASE__INST3_SEG0                       0
0676 #define MP0_BASE__INST3_SEG1                       0
0677 #define MP0_BASE__INST3_SEG2                       0
0678 #define MP0_BASE__INST3_SEG3                       0
0679 #define MP0_BASE__INST3_SEG4                       0
0680 
0681 #define MP0_BASE__INST4_SEG0                       0
0682 #define MP0_BASE__INST4_SEG1                       0
0683 #define MP0_BASE__INST4_SEG2                       0
0684 #define MP0_BASE__INST4_SEG3                       0
0685 #define MP0_BASE__INST4_SEG4                       0
0686 
0687 #define MP0_BASE__INST5_SEG0                       0
0688 #define MP0_BASE__INST5_SEG1                       0
0689 #define MP0_BASE__INST5_SEG2                       0
0690 #define MP0_BASE__INST5_SEG3                       0
0691 #define MP0_BASE__INST5_SEG4                       0
0692 
0693 #define MP0_BASE__INST6_SEG0                       0
0694 #define MP0_BASE__INST6_SEG1                       0
0695 #define MP0_BASE__INST6_SEG2                       0
0696 #define MP0_BASE__INST6_SEG3                       0
0697 #define MP0_BASE__INST6_SEG4                       0
0698 
0699 #define MP1_BASE__INST0_SEG0                       0x00016200
0700 #define MP1_BASE__INST0_SEG1                       0x00E80000
0701 #define MP1_BASE__INST0_SEG2                       0x00EC0000
0702 #define MP1_BASE__INST0_SEG3                       0x00F00000
0703 #define MP1_BASE__INST0_SEG4                       0x02400400
0704 
0705 #define MP1_BASE__INST1_SEG0                       0
0706 #define MP1_BASE__INST1_SEG1                       0
0707 #define MP1_BASE__INST1_SEG2                       0
0708 #define MP1_BASE__INST1_SEG3                       0
0709 #define MP1_BASE__INST1_SEG4                       0
0710 
0711 #define MP1_BASE__INST2_SEG0                       0
0712 #define MP1_BASE__INST2_SEG1                       0
0713 #define MP1_BASE__INST2_SEG2                       0
0714 #define MP1_BASE__INST2_SEG3                       0
0715 #define MP1_BASE__INST2_SEG4                       0
0716 
0717 #define MP1_BASE__INST3_SEG0                       0
0718 #define MP1_BASE__INST3_SEG1                       0
0719 #define MP1_BASE__INST3_SEG2                       0
0720 #define MP1_BASE__INST3_SEG3                       0
0721 #define MP1_BASE__INST3_SEG4                       0
0722 
0723 #define MP1_BASE__INST4_SEG0                       0
0724 #define MP1_BASE__INST4_SEG1                       0
0725 #define MP1_BASE__INST4_SEG2                       0
0726 #define MP1_BASE__INST4_SEG3                       0
0727 #define MP1_BASE__INST4_SEG4                       0
0728 
0729 #define MP1_BASE__INST5_SEG0                       0
0730 #define MP1_BASE__INST5_SEG1                       0
0731 #define MP1_BASE__INST5_SEG2                       0
0732 #define MP1_BASE__INST5_SEG3                       0
0733 #define MP1_BASE__INST5_SEG4                       0
0734 
0735 #define MP1_BASE__INST6_SEG0                       0
0736 #define MP1_BASE__INST6_SEG1                       0
0737 #define MP1_BASE__INST6_SEG2                       0
0738 #define MP1_BASE__INST6_SEG3                       0
0739 #define MP1_BASE__INST6_SEG4                       0
0740 
0741 #define NBIF0_BASE__INST0_SEG0                     0x00000000
0742 #define NBIF0_BASE__INST0_SEG1                     0x00000014
0743 #define NBIF0_BASE__INST0_SEG2                     0x00000D20
0744 #define NBIF0_BASE__INST0_SEG3                     0x00010400
0745 #define NBIF0_BASE__INST0_SEG4                     0x0241B000
0746 
0747 #define NBIF0_BASE__INST1_SEG0                     0
0748 #define NBIF0_BASE__INST1_SEG1                     0
0749 #define NBIF0_BASE__INST1_SEG2                     0
0750 #define NBIF0_BASE__INST1_SEG3                     0
0751 #define NBIF0_BASE__INST1_SEG4                     0
0752 
0753 #define NBIF0_BASE__INST2_SEG0                     0
0754 #define NBIF0_BASE__INST2_SEG1                     0
0755 #define NBIF0_BASE__INST2_SEG2                     0
0756 #define NBIF0_BASE__INST2_SEG3                     0
0757 #define NBIF0_BASE__INST2_SEG4                     0
0758 
0759 #define NBIF0_BASE__INST3_SEG0                     0
0760 #define NBIF0_BASE__INST3_SEG1                     0
0761 #define NBIF0_BASE__INST3_SEG2                     0
0762 #define NBIF0_BASE__INST3_SEG3                     0
0763 #define NBIF0_BASE__INST3_SEG4                     0
0764 
0765 #define NBIF0_BASE__INST4_SEG0                     0
0766 #define NBIF0_BASE__INST4_SEG1                     0
0767 #define NBIF0_BASE__INST4_SEG2                     0
0768 #define NBIF0_BASE__INST4_SEG3                     0
0769 #define NBIF0_BASE__INST4_SEG4                     0
0770 
0771 #define NBIF0_BASE__INST5_SEG0                     0
0772 #define NBIF0_BASE__INST5_SEG1                     0
0773 #define NBIF0_BASE__INST5_SEG2                     0
0774 #define NBIF0_BASE__INST5_SEG3                     0
0775 #define NBIF0_BASE__INST5_SEG4                     0
0776 
0777 #define NBIF0_BASE__INST6_SEG0                     0
0778 #define NBIF0_BASE__INST6_SEG1                     0
0779 #define NBIF0_BASE__INST6_SEG2                     0
0780 #define NBIF0_BASE__INST6_SEG3                     0
0781 #define NBIF0_BASE__INST6_SEG4                     0
0782 
0783 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0784 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
0785 #define OSSSYS_BASE__INST0_SEG2                    0
0786 #define OSSSYS_BASE__INST0_SEG3                    0
0787 #define OSSSYS_BASE__INST0_SEG4                    0
0788 
0789 #define OSSSYS_BASE__INST1_SEG0                    0
0790 #define OSSSYS_BASE__INST1_SEG1                    0
0791 #define OSSSYS_BASE__INST1_SEG2                    0
0792 #define OSSSYS_BASE__INST1_SEG3                    0
0793 #define OSSSYS_BASE__INST1_SEG4                    0
0794 
0795 #define OSSSYS_BASE__INST2_SEG0                    0
0796 #define OSSSYS_BASE__INST2_SEG1                    0
0797 #define OSSSYS_BASE__INST2_SEG2                    0
0798 #define OSSSYS_BASE__INST2_SEG3                    0
0799 #define OSSSYS_BASE__INST2_SEG4                    0
0800 
0801 #define OSSSYS_BASE__INST3_SEG0                    0
0802 #define OSSSYS_BASE__INST3_SEG1                    0
0803 #define OSSSYS_BASE__INST3_SEG2                    0
0804 #define OSSSYS_BASE__INST3_SEG3                    0
0805 #define OSSSYS_BASE__INST3_SEG4                    0
0806 
0807 #define OSSSYS_BASE__INST4_SEG0                    0
0808 #define OSSSYS_BASE__INST4_SEG1                    0
0809 #define OSSSYS_BASE__INST4_SEG2                    0
0810 #define OSSSYS_BASE__INST4_SEG3                    0
0811 #define OSSSYS_BASE__INST4_SEG4                    0
0812 
0813 #define OSSSYS_BASE__INST5_SEG0                    0
0814 #define OSSSYS_BASE__INST5_SEG1                    0
0815 #define OSSSYS_BASE__INST5_SEG2                    0
0816 #define OSSSYS_BASE__INST5_SEG3                    0
0817 #define OSSSYS_BASE__INST5_SEG4                    0
0818 
0819 #define OSSSYS_BASE__INST6_SEG0                    0
0820 #define OSSSYS_BASE__INST6_SEG1                    0
0821 #define OSSSYS_BASE__INST6_SEG2                    0
0822 #define OSSSYS_BASE__INST6_SEG3                    0
0823 #define OSSSYS_BASE__INST6_SEG4                    0
0824 
0825 #define PCIE0_BASE__INST0_SEG0                     0x02411800
0826 #define PCIE0_BASE__INST0_SEG1                     0x04440000
0827 #define PCIE0_BASE__INST0_SEG2                     0
0828 #define PCIE0_BASE__INST0_SEG3                     0
0829 #define PCIE0_BASE__INST0_SEG4                     0
0830 
0831 #define PCIE0_BASE__INST1_SEG0                     0
0832 #define PCIE0_BASE__INST1_SEG1                     0
0833 #define PCIE0_BASE__INST1_SEG2                     0
0834 #define PCIE0_BASE__INST1_SEG3                     0
0835 #define PCIE0_BASE__INST1_SEG4                     0
0836 
0837 #define PCIE0_BASE__INST2_SEG0                     0
0838 #define PCIE0_BASE__INST2_SEG1                     0
0839 #define PCIE0_BASE__INST2_SEG2                     0
0840 #define PCIE0_BASE__INST2_SEG3                     0
0841 #define PCIE0_BASE__INST2_SEG4                     0
0842 
0843 #define PCIE0_BASE__INST3_SEG0                     0
0844 #define PCIE0_BASE__INST3_SEG1                     0
0845 #define PCIE0_BASE__INST3_SEG2                     0
0846 #define PCIE0_BASE__INST3_SEG3                     0
0847 #define PCIE0_BASE__INST3_SEG4                     0
0848 
0849 #define PCIE0_BASE__INST4_SEG0                     0
0850 #define PCIE0_BASE__INST4_SEG1                     0
0851 #define PCIE0_BASE__INST4_SEG2                     0
0852 #define PCIE0_BASE__INST4_SEG3                     0
0853 #define PCIE0_BASE__INST4_SEG4                     0
0854 
0855 #define PCIE0_BASE__INST5_SEG0                     0
0856 #define PCIE0_BASE__INST5_SEG1                     0
0857 #define PCIE0_BASE__INST5_SEG2                     0
0858 #define PCIE0_BASE__INST5_SEG3                     0
0859 #define PCIE0_BASE__INST5_SEG4                     0
0860 
0861 #define PCIE0_BASE__INST6_SEG0                     0
0862 #define PCIE0_BASE__INST6_SEG1                     0
0863 #define PCIE0_BASE__INST6_SEG2                     0
0864 #define PCIE0_BASE__INST6_SEG3                     0
0865 #define PCIE0_BASE__INST6_SEG4                     0
0866 
0867 #define SDMA_BASE__INST0_SEG0                      0x00001260
0868 #define SDMA_BASE__INST0_SEG1                      0x0000A000
0869 #define SDMA_BASE__INST0_SEG2                      0x02402C00
0870 #define SDMA_BASE__INST0_SEG3                      0
0871 #define SDMA_BASE__INST0_SEG4                      0
0872 
0873 #define SDMA_BASE__INST1_SEG0                      0x00001260
0874 #define SDMA_BASE__INST1_SEG1                      0x0000A000
0875 #define SDMA_BASE__INST1_SEG2                      0x02402C00
0876 #define SDMA_BASE__INST1_SEG3                      0
0877 #define SDMA_BASE__INST1_SEG4                      0
0878 
0879 #define SDMA_BASE__INST2_SEG0                      0
0880 #define SDMA_BASE__INST2_SEG1                      0
0881 #define SDMA_BASE__INST2_SEG2                      0
0882 #define SDMA_BASE__INST2_SEG3                      0
0883 #define SDMA_BASE__INST2_SEG4                      0
0884 
0885 #define SDMA_BASE__INST3_SEG0                      0
0886 #define SDMA_BASE__INST3_SEG1                      0
0887 #define SDMA_BASE__INST3_SEG2                      0
0888 #define SDMA_BASE__INST3_SEG3                      0
0889 #define SDMA_BASE__INST3_SEG4                      0
0890 
0891 #define SDMA_BASE__INST4_SEG0                      0
0892 #define SDMA_BASE__INST4_SEG1                      0
0893 #define SDMA_BASE__INST4_SEG2                      0
0894 #define SDMA_BASE__INST4_SEG3                      0
0895 #define SDMA_BASE__INST4_SEG4                      0
0896 
0897 #define SDMA_BASE__INST5_SEG0                      0
0898 #define SDMA_BASE__INST5_SEG1                      0
0899 #define SDMA_BASE__INST5_SEG2                      0
0900 #define SDMA_BASE__INST5_SEG3                      0
0901 #define SDMA_BASE__INST5_SEG4                      0
0902 
0903 #define SDMA_BASE__INST6_SEG0                      0
0904 #define SDMA_BASE__INST6_SEG1                      0
0905 #define SDMA_BASE__INST6_SEG2                      0
0906 #define SDMA_BASE__INST6_SEG3                      0
0907 #define SDMA_BASE__INST6_SEG4                      0
0908 
0909 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0910 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0911 #define SMUIO_BASE__INST0_SEG2                     0x00440000
0912 #define SMUIO_BASE__INST0_SEG3                     0x02401000
0913 #define SMUIO_BASE__INST0_SEG4                     0
0914 
0915 #define SMUIO_BASE__INST1_SEG0                     0
0916 #define SMUIO_BASE__INST1_SEG1                     0
0917 #define SMUIO_BASE__INST1_SEG2                     0
0918 #define SMUIO_BASE__INST1_SEG3                     0
0919 #define SMUIO_BASE__INST1_SEG4                     0
0920 
0921 #define SMUIO_BASE__INST2_SEG0                     0
0922 #define SMUIO_BASE__INST2_SEG1                     0
0923 #define SMUIO_BASE__INST2_SEG2                     0
0924 #define SMUIO_BASE__INST2_SEG3                     0
0925 #define SMUIO_BASE__INST2_SEG4                     0
0926 
0927 #define SMUIO_BASE__INST3_SEG0                     0
0928 #define SMUIO_BASE__INST3_SEG1                     0
0929 #define SMUIO_BASE__INST3_SEG2                     0
0930 #define SMUIO_BASE__INST3_SEG3                     0
0931 #define SMUIO_BASE__INST3_SEG4                     0
0932 
0933 #define SMUIO_BASE__INST4_SEG0                     0
0934 #define SMUIO_BASE__INST4_SEG1                     0
0935 #define SMUIO_BASE__INST4_SEG2                     0
0936 #define SMUIO_BASE__INST4_SEG3                     0
0937 #define SMUIO_BASE__INST4_SEG4                     0
0938 
0939 #define SMUIO_BASE__INST5_SEG0                     0
0940 #define SMUIO_BASE__INST5_SEG1                     0
0941 #define SMUIO_BASE__INST5_SEG2                     0
0942 #define SMUIO_BASE__INST5_SEG3                     0
0943 #define SMUIO_BASE__INST5_SEG4                     0
0944 
0945 #define SMUIO_BASE__INST6_SEG0                     0
0946 #define SMUIO_BASE__INST6_SEG1                     0
0947 #define SMUIO_BASE__INST6_SEG2                     0
0948 #define SMUIO_BASE__INST6_SEG3                     0
0949 #define SMUIO_BASE__INST6_SEG4                     0
0950 
0951 #define THM_BASE__INST0_SEG0                       0x00016600
0952 #define THM_BASE__INST0_SEG1                       0x02400C00
0953 #define THM_BASE__INST0_SEG2                       0
0954 #define THM_BASE__INST0_SEG3                       0
0955 #define THM_BASE__INST0_SEG4                       0
0956 
0957 #define THM_BASE__INST1_SEG0                       0
0958 #define THM_BASE__INST1_SEG1                       0
0959 #define THM_BASE__INST1_SEG2                       0
0960 #define THM_BASE__INST1_SEG3                       0
0961 #define THM_BASE__INST1_SEG4                       0
0962 
0963 #define THM_BASE__INST2_SEG0                       0
0964 #define THM_BASE__INST2_SEG1                       0
0965 #define THM_BASE__INST2_SEG2                       0
0966 #define THM_BASE__INST2_SEG3                       0
0967 #define THM_BASE__INST2_SEG4                       0
0968 
0969 #define THM_BASE__INST3_SEG0                       0
0970 #define THM_BASE__INST3_SEG1                       0
0971 #define THM_BASE__INST3_SEG2                       0
0972 #define THM_BASE__INST3_SEG3                       0
0973 #define THM_BASE__INST3_SEG4                       0
0974 
0975 #define THM_BASE__INST4_SEG0                       0
0976 #define THM_BASE__INST4_SEG1                       0
0977 #define THM_BASE__INST4_SEG2                       0
0978 #define THM_BASE__INST4_SEG3                       0
0979 #define THM_BASE__INST4_SEG4                       0
0980 
0981 #define THM_BASE__INST5_SEG0                       0
0982 #define THM_BASE__INST5_SEG1                       0
0983 #define THM_BASE__INST5_SEG2                       0
0984 #define THM_BASE__INST5_SEG3                       0
0985 #define THM_BASE__INST5_SEG4                       0
0986 
0987 #define THM_BASE__INST6_SEG0                       0
0988 #define THM_BASE__INST6_SEG1                       0
0989 #define THM_BASE__INST6_SEG2                       0
0990 #define THM_BASE__INST6_SEG3                       0
0991 #define THM_BASE__INST6_SEG4                       0
0992 
0993 #define UMC_BASE__INST0_SEG0                       0x00014000
0994 #define UMC_BASE__INST0_SEG1                       0x02425800
0995 #define UMC_BASE__INST0_SEG2                       0
0996 #define UMC_BASE__INST0_SEG3                       0
0997 #define UMC_BASE__INST0_SEG4                       0
0998 
0999 #define UMC_BASE__INST1_SEG0                       0x00054000
1000 #define UMC_BASE__INST1_SEG1                       0x02425C00
1001 #define UMC_BASE__INST1_SEG2                       0
1002 #define UMC_BASE__INST1_SEG3                       0
1003 #define UMC_BASE__INST1_SEG4                       0
1004 
1005 #define UMC_BASE__INST2_SEG0                       0x00094000
1006 #define UMC_BASE__INST2_SEG1                       0x02426000
1007 #define UMC_BASE__INST2_SEG2                       0
1008 #define UMC_BASE__INST2_SEG3                       0
1009 #define UMC_BASE__INST2_SEG4                       0
1010 
1011 #define UMC_BASE__INST3_SEG0                       0x000D4000
1012 #define UMC_BASE__INST3_SEG1                       0x02426400
1013 #define UMC_BASE__INST3_SEG2                       0
1014 #define UMC_BASE__INST3_SEG3                       0
1015 #define UMC_BASE__INST3_SEG4                       0
1016 
1017 #define UMC_BASE__INST4_SEG0                       0
1018 #define UMC_BASE__INST4_SEG1                       0
1019 #define UMC_BASE__INST4_SEG2                       0
1020 #define UMC_BASE__INST4_SEG3                       0
1021 #define UMC_BASE__INST4_SEG4                       0
1022 
1023 #define UMC_BASE__INST5_SEG0                       0
1024 #define UMC_BASE__INST5_SEG1                       0
1025 #define UMC_BASE__INST5_SEG2                       0
1026 #define UMC_BASE__INST5_SEG3                       0
1027 #define UMC_BASE__INST5_SEG4                       0
1028 
1029 #define UMC_BASE__INST6_SEG0                       0
1030 #define UMC_BASE__INST6_SEG1                       0
1031 #define UMC_BASE__INST6_SEG2                       0
1032 #define UMC_BASE__INST6_SEG3                       0
1033 #define UMC_BASE__INST6_SEG4                       0
1034 
1035 #define USB0_BASE__INST0_SEG0                      0x0242A800
1036 #define USB0_BASE__INST0_SEG1                      0x05B00000
1037 #define USB0_BASE__INST0_SEG2                      0
1038 #define USB0_BASE__INST0_SEG3                      0
1039 #define USB0_BASE__INST0_SEG4                      0
1040 
1041 #define USB0_BASE__INST1_SEG0                      0
1042 #define USB0_BASE__INST1_SEG1                      0
1043 #define USB0_BASE__INST1_SEG2                      0
1044 #define USB0_BASE__INST1_SEG3                      0
1045 #define USB0_BASE__INST1_SEG4                      0
1046 
1047 #define USB0_BASE__INST2_SEG0                      0
1048 #define USB0_BASE__INST2_SEG1                      0
1049 #define USB0_BASE__INST2_SEG2                      0
1050 #define USB0_BASE__INST2_SEG3                      0
1051 #define USB0_BASE__INST2_SEG4                      0
1052 
1053 #define USB0_BASE__INST3_SEG0                      0
1054 #define USB0_BASE__INST3_SEG1                      0
1055 #define USB0_BASE__INST3_SEG2                      0
1056 #define USB0_BASE__INST3_SEG3                      0
1057 #define USB0_BASE__INST3_SEG4                      0
1058 
1059 #define USB0_BASE__INST4_SEG0                      0
1060 #define USB0_BASE__INST4_SEG1                      0
1061 #define USB0_BASE__INST4_SEG2                      0
1062 #define USB0_BASE__INST4_SEG3                      0
1063 #define USB0_BASE__INST4_SEG4                      0
1064 
1065 #define USB0_BASE__INST5_SEG0                      0
1066 #define USB0_BASE__INST5_SEG1                      0
1067 #define USB0_BASE__INST5_SEG2                      0
1068 #define USB0_BASE__INST5_SEG3                      0
1069 #define USB0_BASE__INST5_SEG4                      0
1070 
1071 #define USB0_BASE__INST6_SEG0                      0
1072 #define USB0_BASE__INST6_SEG1                      0
1073 #define USB0_BASE__INST6_SEG2                      0
1074 #define USB0_BASE__INST6_SEG3                      0
1075 #define USB0_BASE__INST6_SEG4                      0
1076 
1077 #define UVD0_BASE__INST0_SEG0                      0x00007800
1078 #define UVD0_BASE__INST0_SEG1                      0x00007E00
1079 #define UVD0_BASE__INST0_SEG2                      0x02403000
1080 #define UVD0_BASE__INST0_SEG3                      0
1081 #define UVD0_BASE__INST0_SEG4                      0
1082 
1083 #define UVD0_BASE__INST1_SEG0                      0
1084 #define UVD0_BASE__INST1_SEG1                      0
1085 #define UVD0_BASE__INST1_SEG2                      0
1086 #define UVD0_BASE__INST1_SEG3                      0
1087 #define UVD0_BASE__INST1_SEG4                      0
1088 
1089 #define UVD0_BASE__INST2_SEG0                      0
1090 #define UVD0_BASE__INST2_SEG1                      0
1091 #define UVD0_BASE__INST2_SEG2                      0
1092 #define UVD0_BASE__INST2_SEG3                      0
1093 #define UVD0_BASE__INST2_SEG4                      0
1094 
1095 #define UVD0_BASE__INST3_SEG0                      0
1096 #define UVD0_BASE__INST3_SEG1                      0
1097 #define UVD0_BASE__INST3_SEG2                      0
1098 #define UVD0_BASE__INST3_SEG3                      0
1099 #define UVD0_BASE__INST3_SEG4                      0
1100 
1101 #define UVD0_BASE__INST4_SEG0                      0
1102 #define UVD0_BASE__INST4_SEG1                      0
1103 #define UVD0_BASE__INST4_SEG2                      0
1104 #define UVD0_BASE__INST4_SEG3                      0
1105 #define UVD0_BASE__INST4_SEG4                      0
1106 
1107 #define UVD0_BASE__INST5_SEG0                      0
1108 #define UVD0_BASE__INST5_SEG1                      0
1109 #define UVD0_BASE__INST5_SEG2                      0
1110 #define UVD0_BASE__INST5_SEG3                      0
1111 #define UVD0_BASE__INST5_SEG4                      0
1112 
1113 #define UVD0_BASE__INST6_SEG0                      0
1114 #define UVD0_BASE__INST6_SEG1                      0
1115 #define UVD0_BASE__INST6_SEG2                      0
1116 #define UVD0_BASE__INST6_SEG3                      0
1117 #define UVD0_BASE__INST6_SEG4                      0
1118 
1119 #endif