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0001 /*
0002  * Copyright (C) 2019  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _navi10_ip_offset_HEADER
0022 #define _navi10_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                       6
0025 #define MAX_SEGMENT                                        6
0026 
0027 
0028 struct IP_BASE_INSTANCE {
0029     unsigned int segment[MAX_SEGMENT];
0030 };
0031  
0032 struct IP_BASE {
0033     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0034 } __maybe_unused;
0035 
0036 
0037 static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C00, 0, 0, 0, 0, 0 } },
0038                                         { { 0, 0, 0, 0, 0, 0 } },
0039                                         { { 0, 0, 0, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0, 0 } } } };
0043 static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } },
0044                                         { { 0, 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0, 0 } },
0046                                         { { 0, 0, 0, 0, 0, 0 } },
0047                                         { { 0, 0, 0, 0, 0, 0 } },
0048                                         { { 0, 0, 0, 0, 0, 0 } } } };
0049 static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
0050                                         { { 0, 0, 0, 0, 0, 0 } },
0051                                         { { 0, 0, 0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0, 0 } },
0053                                         { { 0, 0, 0, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0, 0 } } } };
0055 static const struct IP_BASE DCN_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0, 0 } } } };
0061 static const struct IP_BASE FUSE_BASE            ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } } } };
0067 static const struct IP_BASE GC_BASE            ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } } } };
0073 static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0, 0 } },
0075                                         { { 0, 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } } } };
0079 static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } },
0081                                         { { 0, 0, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0, 0 } } } };
0085 static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } } } };
0091 static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0, 0 } } } };
0097 static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0, 0 } } } };
0103 static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } } } };
0109 static const struct IP_BASE RSMU_BASE           = { { { { 0x00012000, 0, 0, 0, 0, 0 } },
0110                     { { 0, 0, 0, 0, 0, 0 } },
0111                     { { 0, 0, 0, 0, 0, 0 } },
0112                     { { 0, 0, 0, 0, 0, 0 } },
0113                     { { 0, 0, 0, 0, 0, 0 } },
0114                     { { 0, 0, 0, 0, 0, 0 } } } };
0115 static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0, 0 } },
0117                                         { { 0, 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } } } };
0121 static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } },
0123                                         { { 0, 0, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0, 0 } } } };
0127 static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } } } };
0133 static const struct IP_BASE VCN_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0, 0 } } } };
0139 
0140 
0141 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0142 #define ATHUB_BASE__INST0_SEG1                     0
0143 #define ATHUB_BASE__INST0_SEG2                     0
0144 #define ATHUB_BASE__INST0_SEG3                     0
0145 #define ATHUB_BASE__INST0_SEG4                     0
0146 #define ATHUB_BASE__INST0_SEG5                     0
0147 
0148 #define ATHUB_BASE__INST1_SEG0                     0
0149 #define ATHUB_BASE__INST1_SEG1                     0
0150 #define ATHUB_BASE__INST1_SEG2                     0
0151 #define ATHUB_BASE__INST1_SEG3                     0
0152 #define ATHUB_BASE__INST1_SEG4                     0
0153 #define ATHUB_BASE__INST1_SEG5                     0
0154 
0155 #define ATHUB_BASE__INST2_SEG0                     0
0156 #define ATHUB_BASE__INST2_SEG1                     0
0157 #define ATHUB_BASE__INST2_SEG2                     0
0158 #define ATHUB_BASE__INST2_SEG3                     0
0159 #define ATHUB_BASE__INST2_SEG4                     0
0160 #define ATHUB_BASE__INST2_SEG5                     0
0161 
0162 #define ATHUB_BASE__INST3_SEG0                     0
0163 #define ATHUB_BASE__INST3_SEG1                     0
0164 #define ATHUB_BASE__INST3_SEG2                     0
0165 #define ATHUB_BASE__INST3_SEG3                     0
0166 #define ATHUB_BASE__INST3_SEG4                     0
0167 #define ATHUB_BASE__INST3_SEG5                     0
0168 
0169 #define ATHUB_BASE__INST4_SEG0                     0
0170 #define ATHUB_BASE__INST4_SEG1                     0
0171 #define ATHUB_BASE__INST4_SEG2                     0
0172 #define ATHUB_BASE__INST4_SEG3                     0
0173 #define ATHUB_BASE__INST4_SEG4                     0
0174 #define ATHUB_BASE__INST4_SEG5                     0
0175 
0176 #define ATHUB_BASE__INST5_SEG0                     0
0177 #define ATHUB_BASE__INST5_SEG1                     0
0178 #define ATHUB_BASE__INST5_SEG2                     0
0179 #define ATHUB_BASE__INST5_SEG3                     0
0180 #define ATHUB_BASE__INST5_SEG4                     0
0181 #define ATHUB_BASE__INST5_SEG5                     0
0182 
0183 #define CLK_BASE__INST0_SEG0                       0x00016C00
0184 #define CLK_BASE__INST0_SEG1                       0x00016E00
0185 #define CLK_BASE__INST0_SEG2                       0x00017000
0186 #define CLK_BASE__INST0_SEG3                       0x00017200
0187 #define CLK_BASE__INST0_SEG4                       0x00017E00
0188 #define CLK_BASE__INST0_SEG5                       0x0001B000
0189 
0190 #define CLK_BASE__INST1_SEG0                       0
0191 #define CLK_BASE__INST1_SEG1                       0
0192 #define CLK_BASE__INST1_SEG2                       0
0193 #define CLK_BASE__INST1_SEG3                       0
0194 #define CLK_BASE__INST1_SEG4                       0
0195 #define CLK_BASE__INST1_SEG5                       0
0196 
0197 #define CLK_BASE__INST2_SEG0                       0
0198 #define CLK_BASE__INST2_SEG1                       0
0199 #define CLK_BASE__INST2_SEG2                       0
0200 #define CLK_BASE__INST2_SEG3                       0
0201 #define CLK_BASE__INST2_SEG4                       0
0202 #define CLK_BASE__INST2_SEG5                       0
0203 
0204 #define CLK_BASE__INST3_SEG0                       0
0205 #define CLK_BASE__INST3_SEG1                       0
0206 #define CLK_BASE__INST3_SEG2                       0
0207 #define CLK_BASE__INST3_SEG3                       0
0208 #define CLK_BASE__INST3_SEG4                       0
0209 #define CLK_BASE__INST3_SEG5                       0
0210 
0211 #define CLK_BASE__INST4_SEG0                       0
0212 #define CLK_BASE__INST4_SEG1                       0
0213 #define CLK_BASE__INST4_SEG2                       0
0214 #define CLK_BASE__INST4_SEG3                       0
0215 #define CLK_BASE__INST4_SEG4                       0
0216 #define CLK_BASE__INST4_SEG5                       0
0217 
0218 #define CLK_BASE__INST5_SEG0                       0
0219 #define CLK_BASE__INST5_SEG1                       0
0220 #define CLK_BASE__INST5_SEG2                       0
0221 #define CLK_BASE__INST5_SEG3                       0
0222 #define CLK_BASE__INST5_SEG4                       0
0223 #define CLK_BASE__INST5_SEG5                       0
0224 
0225 #define DF_BASE__INST0_SEG0                        0x00007000
0226 #define DF_BASE__INST0_SEG1                        0
0227 #define DF_BASE__INST0_SEG2                        0
0228 #define DF_BASE__INST0_SEG3                        0
0229 #define DF_BASE__INST0_SEG4                        0
0230 #define DF_BASE__INST0_SEG5                        0
0231 
0232 #define DF_BASE__INST1_SEG0                        0
0233 #define DF_BASE__INST1_SEG1                        0
0234 #define DF_BASE__INST1_SEG2                        0
0235 #define DF_BASE__INST1_SEG3                        0
0236 #define DF_BASE__INST1_SEG4                        0
0237 #define DF_BASE__INST1_SEG5                        0
0238 
0239 #define DF_BASE__INST2_SEG0                        0
0240 #define DF_BASE__INST2_SEG1                        0
0241 #define DF_BASE__INST2_SEG2                        0
0242 #define DF_BASE__INST2_SEG3                        0
0243 #define DF_BASE__INST2_SEG4                        0
0244 #define DF_BASE__INST2_SEG5                        0
0245 
0246 #define DF_BASE__INST3_SEG0                        0
0247 #define DF_BASE__INST3_SEG1                        0
0248 #define DF_BASE__INST3_SEG2                        0
0249 #define DF_BASE__INST3_SEG3                        0
0250 #define DF_BASE__INST3_SEG4                        0
0251 #define DF_BASE__INST3_SEG5                        0
0252 
0253 #define DF_BASE__INST4_SEG0                        0
0254 #define DF_BASE__INST4_SEG1                        0
0255 #define DF_BASE__INST4_SEG2                        0
0256 #define DF_BASE__INST4_SEG3                        0
0257 #define DF_BASE__INST4_SEG4                        0
0258 #define DF_BASE__INST4_SEG5                        0
0259 
0260 #define DF_BASE__INST5_SEG0                        0
0261 #define DF_BASE__INST5_SEG1                        0
0262 #define DF_BASE__INST5_SEG2                        0
0263 #define DF_BASE__INST5_SEG3                        0
0264 #define DF_BASE__INST5_SEG4                        0
0265 #define DF_BASE__INST5_SEG5                        0
0266 
0267 #define DCN_BASE__INST0_SEG0                       0x00000012
0268 #define DCN_BASE__INST0_SEG1                       0x000000C0
0269 #define DCN_BASE__INST0_SEG2                       0x000034C0
0270 #define DCN_BASE__INST0_SEG3                       0x00009000
0271 #define DCN_BASE__INST0_SEG4                       0
0272 #define DCN_BASE__INST0_SEG5                       0
0273 
0274 #define DCN_BASE__INST1_SEG0                       0
0275 #define DCN_BASE__INST1_SEG1                       0
0276 #define DCN_BASE__INST1_SEG2                       0
0277 #define DCN_BASE__INST1_SEG3                       0
0278 #define DCN_BASE__INST1_SEG4                       0
0279 #define DCN_BASE__INST1_SEG5                       0
0280 
0281 #define DCN_BASE__INST2_SEG0                       0
0282 #define DCN_BASE__INST2_SEG1                       0
0283 #define DCN_BASE__INST2_SEG2                       0
0284 #define DCN_BASE__INST2_SEG3                       0
0285 #define DCN_BASE__INST2_SEG4                       0
0286 #define DCN_BASE__INST2_SEG5                       0
0287 
0288 #define DCN_BASE__INST3_SEG0                       0
0289 #define DCN_BASE__INST3_SEG1                       0
0290 #define DCN_BASE__INST3_SEG2                       0
0291 #define DCN_BASE__INST3_SEG3                       0
0292 #define DCN_BASE__INST3_SEG4                       0
0293 #define DCN_BASE__INST3_SEG5                       0
0294 
0295 #define DCN_BASE__INST4_SEG0                       0
0296 #define DCN_BASE__INST4_SEG1                       0
0297 #define DCN_BASE__INST4_SEG2                       0
0298 #define DCN_BASE__INST4_SEG3                       0
0299 #define DCN_BASE__INST4_SEG4                       0
0300 #define DCN_BASE__INST4_SEG5                       0
0301 
0302 #define DCN_BASE__INST5_SEG0                       0
0303 #define DCN_BASE__INST5_SEG1                       0
0304 #define DCN_BASE__INST5_SEG2                       0
0305 #define DCN_BASE__INST5_SEG3                       0
0306 #define DCN_BASE__INST5_SEG4                       0
0307 #define DCN_BASE__INST5_SEG5                       0
0308 
0309 #define FUSE_BASE__INST0_SEG0                      0x00017400
0310 #define FUSE_BASE__INST0_SEG1                      0
0311 #define FUSE_BASE__INST0_SEG2                      0
0312 #define FUSE_BASE__INST0_SEG3                      0
0313 #define FUSE_BASE__INST0_SEG4                      0
0314 #define FUSE_BASE__INST0_SEG5                      0
0315 
0316 #define FUSE_BASE__INST1_SEG0                      0
0317 #define FUSE_BASE__INST1_SEG1                      0
0318 #define FUSE_BASE__INST1_SEG2                      0
0319 #define FUSE_BASE__INST1_SEG3                      0
0320 #define FUSE_BASE__INST1_SEG4                      0
0321 #define FUSE_BASE__INST1_SEG5                      0
0322 
0323 #define FUSE_BASE__INST2_SEG0                      0
0324 #define FUSE_BASE__INST2_SEG1                      0
0325 #define FUSE_BASE__INST2_SEG2                      0
0326 #define FUSE_BASE__INST2_SEG3                      0
0327 #define FUSE_BASE__INST2_SEG4                      0
0328 #define FUSE_BASE__INST2_SEG5                      0
0329 
0330 #define FUSE_BASE__INST3_SEG0                      0
0331 #define FUSE_BASE__INST3_SEG1                      0
0332 #define FUSE_BASE__INST3_SEG2                      0
0333 #define FUSE_BASE__INST3_SEG3                      0
0334 #define FUSE_BASE__INST3_SEG4                      0
0335 #define FUSE_BASE__INST3_SEG5                      0
0336 
0337 #define FUSE_BASE__INST4_SEG0                      0
0338 #define FUSE_BASE__INST4_SEG1                      0
0339 #define FUSE_BASE__INST4_SEG2                      0
0340 #define FUSE_BASE__INST4_SEG3                      0
0341 #define FUSE_BASE__INST4_SEG4                      0
0342 #define FUSE_BASE__INST4_SEG5                      0
0343 
0344 #define FUSE_BASE__INST5_SEG0                      0
0345 #define FUSE_BASE__INST5_SEG1                      0
0346 #define FUSE_BASE__INST5_SEG2                      0
0347 #define FUSE_BASE__INST5_SEG3                      0
0348 #define FUSE_BASE__INST5_SEG4                      0
0349 #define FUSE_BASE__INST5_SEG5                      0
0350 
0351 #define GC_BASE__INST0_SEG0                        0x00001260
0352 #define GC_BASE__INST0_SEG1                        0x0000A000
0353 #define GC_BASE__INST0_SEG2                        0
0354 #define GC_BASE__INST0_SEG3                        0
0355 #define GC_BASE__INST0_SEG4                        0
0356 #define GC_BASE__INST0_SEG5                        0
0357 
0358 #define GC_BASE__INST1_SEG0                        0
0359 #define GC_BASE__INST1_SEG1                        0
0360 #define GC_BASE__INST1_SEG2                        0
0361 #define GC_BASE__INST1_SEG3                        0
0362 #define GC_BASE__INST1_SEG4                        0
0363 #define GC_BASE__INST1_SEG5                        0
0364 
0365 #define GC_BASE__INST2_SEG0                        0
0366 #define GC_BASE__INST2_SEG1                        0
0367 #define GC_BASE__INST2_SEG2                        0
0368 #define GC_BASE__INST2_SEG3                        0
0369 #define GC_BASE__INST2_SEG4                        0
0370 #define GC_BASE__INST2_SEG5                        0
0371 
0372 #define GC_BASE__INST3_SEG0                        0
0373 #define GC_BASE__INST3_SEG1                        0
0374 #define GC_BASE__INST3_SEG2                        0
0375 #define GC_BASE__INST3_SEG3                        0
0376 #define GC_BASE__INST3_SEG4                        0
0377 #define GC_BASE__INST3_SEG5                        0
0378 
0379 #define GC_BASE__INST4_SEG0                        0
0380 #define GC_BASE__INST4_SEG1                        0
0381 #define GC_BASE__INST4_SEG2                        0
0382 #define GC_BASE__INST4_SEG3                        0
0383 #define GC_BASE__INST4_SEG4                        0
0384 #define GC_BASE__INST4_SEG5                        0
0385 
0386 #define GC_BASE__INST5_SEG0                        0
0387 #define GC_BASE__INST5_SEG1                        0
0388 #define GC_BASE__INST5_SEG2                        0
0389 #define GC_BASE__INST5_SEG3                        0
0390 #define GC_BASE__INST5_SEG4                        0
0391 #define GC_BASE__INST5_SEG5                        0
0392 
0393 #define HDP_BASE__INST0_SEG0                       0x00000F20
0394 #define HDP_BASE__INST0_SEG1                       0
0395 #define HDP_BASE__INST0_SEG2                       0
0396 #define HDP_BASE__INST0_SEG3                       0
0397 #define HDP_BASE__INST0_SEG4                       0
0398 #define HDP_BASE__INST0_SEG5                       0
0399 
0400 #define HDP_BASE__INST1_SEG0                       0
0401 #define HDP_BASE__INST1_SEG1                       0
0402 #define HDP_BASE__INST1_SEG2                       0
0403 #define HDP_BASE__INST1_SEG3                       0
0404 #define HDP_BASE__INST1_SEG4                       0
0405 #define HDP_BASE__INST1_SEG5                       0
0406 
0407 #define HDP_BASE__INST2_SEG0                       0
0408 #define HDP_BASE__INST2_SEG1                       0
0409 #define HDP_BASE__INST2_SEG2                       0
0410 #define HDP_BASE__INST2_SEG3                       0
0411 #define HDP_BASE__INST2_SEG4                       0
0412 #define HDP_BASE__INST2_SEG5                       0
0413 
0414 #define HDP_BASE__INST3_SEG0                       0
0415 #define HDP_BASE__INST3_SEG1                       0
0416 #define HDP_BASE__INST3_SEG2                       0
0417 #define HDP_BASE__INST3_SEG3                       0
0418 #define HDP_BASE__INST3_SEG4                       0
0419 #define HDP_BASE__INST3_SEG5                       0
0420 
0421 #define HDP_BASE__INST4_SEG0                       0
0422 #define HDP_BASE__INST4_SEG1                       0
0423 #define HDP_BASE__INST4_SEG2                       0
0424 #define HDP_BASE__INST4_SEG3                       0
0425 #define HDP_BASE__INST4_SEG4                       0
0426 #define HDP_BASE__INST4_SEG5                       0
0427 
0428 #define HDP_BASE__INST5_SEG0                       0
0429 #define HDP_BASE__INST5_SEG1                       0
0430 #define HDP_BASE__INST5_SEG2                       0
0431 #define HDP_BASE__INST5_SEG3                       0
0432 #define HDP_BASE__INST5_SEG4                       0
0433 #define HDP_BASE__INST5_SEG5                       0
0434 
0435 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0436 #define MMHUB_BASE__INST0_SEG1                     0
0437 #define MMHUB_BASE__INST0_SEG2                     0
0438 #define MMHUB_BASE__INST0_SEG3                     0
0439 #define MMHUB_BASE__INST0_SEG4                     0
0440 #define MMHUB_BASE__INST0_SEG5                     0
0441 
0442 #define MMHUB_BASE__INST1_SEG0                     0
0443 #define MMHUB_BASE__INST1_SEG1                     0
0444 #define MMHUB_BASE__INST1_SEG2                     0
0445 #define MMHUB_BASE__INST1_SEG3                     0
0446 #define MMHUB_BASE__INST1_SEG4                     0
0447 #define MMHUB_BASE__INST1_SEG5                     0
0448 
0449 #define MMHUB_BASE__INST2_SEG0                     0
0450 #define MMHUB_BASE__INST2_SEG1                     0
0451 #define MMHUB_BASE__INST2_SEG2                     0
0452 #define MMHUB_BASE__INST2_SEG3                     0
0453 #define MMHUB_BASE__INST2_SEG4                     0
0454 #define MMHUB_BASE__INST2_SEG5                     0
0455 
0456 #define MMHUB_BASE__INST3_SEG0                     0
0457 #define MMHUB_BASE__INST3_SEG1                     0
0458 #define MMHUB_BASE__INST3_SEG2                     0
0459 #define MMHUB_BASE__INST3_SEG3                     0
0460 #define MMHUB_BASE__INST3_SEG4                     0
0461 #define MMHUB_BASE__INST3_SEG5                     0
0462 
0463 #define MMHUB_BASE__INST4_SEG0                     0
0464 #define MMHUB_BASE__INST4_SEG1                     0
0465 #define MMHUB_BASE__INST4_SEG2                     0
0466 #define MMHUB_BASE__INST4_SEG3                     0
0467 #define MMHUB_BASE__INST4_SEG4                     0
0468 #define MMHUB_BASE__INST4_SEG5                     0
0469 
0470 #define MMHUB_BASE__INST5_SEG0                     0
0471 #define MMHUB_BASE__INST5_SEG1                     0
0472 #define MMHUB_BASE__INST5_SEG2                     0
0473 #define MMHUB_BASE__INST5_SEG3                     0
0474 #define MMHUB_BASE__INST5_SEG4                     0
0475 #define MMHUB_BASE__INST5_SEG5                     0
0476 
0477 #define MP0_BASE__INST0_SEG0                       0x00016000
0478 #define MP0_BASE__INST0_SEG1                       0
0479 #define MP0_BASE__INST0_SEG2                       0
0480 #define MP0_BASE__INST0_SEG3                       0
0481 #define MP0_BASE__INST0_SEG4                       0
0482 #define MP0_BASE__INST0_SEG5                       0
0483 
0484 #define MP0_BASE__INST1_SEG0                       0
0485 #define MP0_BASE__INST1_SEG1                       0
0486 #define MP0_BASE__INST1_SEG2                       0
0487 #define MP0_BASE__INST1_SEG3                       0
0488 #define MP0_BASE__INST1_SEG4                       0
0489 #define MP0_BASE__INST1_SEG5                       0
0490 
0491 #define MP0_BASE__INST2_SEG0                       0
0492 #define MP0_BASE__INST2_SEG1                       0
0493 #define MP0_BASE__INST2_SEG2                       0
0494 #define MP0_BASE__INST2_SEG3                       0
0495 #define MP0_BASE__INST2_SEG4                       0
0496 #define MP0_BASE__INST2_SEG5                       0
0497 
0498 #define MP0_BASE__INST3_SEG0                       0
0499 #define MP0_BASE__INST3_SEG1                       0
0500 #define MP0_BASE__INST3_SEG2                       0
0501 #define MP0_BASE__INST3_SEG3                       0
0502 #define MP0_BASE__INST3_SEG4                       0
0503 #define MP0_BASE__INST3_SEG5                       0
0504 
0505 #define MP0_BASE__INST4_SEG0                       0
0506 #define MP0_BASE__INST4_SEG1                       0
0507 #define MP0_BASE__INST4_SEG2                       0
0508 #define MP0_BASE__INST4_SEG3                       0
0509 #define MP0_BASE__INST4_SEG4                       0
0510 #define MP0_BASE__INST4_SEG5                       0
0511 
0512 #define MP0_BASE__INST5_SEG0                       0
0513 #define MP0_BASE__INST5_SEG1                       0
0514 #define MP0_BASE__INST5_SEG2                       0
0515 #define MP0_BASE__INST5_SEG3                       0
0516 #define MP0_BASE__INST5_SEG4                       0
0517 #define MP0_BASE__INST5_SEG5                       0
0518 
0519 #define MP1_BASE__INST0_SEG0                       0x00016000
0520 #define MP1_BASE__INST0_SEG1                       0
0521 #define MP1_BASE__INST0_SEG2                       0
0522 #define MP1_BASE__INST0_SEG3                       0
0523 #define MP1_BASE__INST0_SEG4                       0
0524 #define MP1_BASE__INST0_SEG5                       0
0525 
0526 #define MP1_BASE__INST1_SEG0                       0
0527 #define MP1_BASE__INST1_SEG1                       0
0528 #define MP1_BASE__INST1_SEG2                       0
0529 #define MP1_BASE__INST1_SEG3                       0
0530 #define MP1_BASE__INST1_SEG4                       0
0531 #define MP1_BASE__INST1_SEG5                       0
0532 
0533 #define MP1_BASE__INST2_SEG0                       0
0534 #define MP1_BASE__INST2_SEG1                       0
0535 #define MP1_BASE__INST2_SEG2                       0
0536 #define MP1_BASE__INST2_SEG3                       0
0537 #define MP1_BASE__INST2_SEG4                       0
0538 #define MP1_BASE__INST2_SEG5                       0
0539 
0540 #define MP1_BASE__INST3_SEG0                       0
0541 #define MP1_BASE__INST3_SEG1                       0
0542 #define MP1_BASE__INST3_SEG2                       0
0543 #define MP1_BASE__INST3_SEG3                       0
0544 #define MP1_BASE__INST3_SEG4                       0
0545 #define MP1_BASE__INST3_SEG5                       0
0546 
0547 #define MP1_BASE__INST4_SEG0                       0
0548 #define MP1_BASE__INST4_SEG1                       0
0549 #define MP1_BASE__INST4_SEG2                       0
0550 #define MP1_BASE__INST4_SEG3                       0
0551 #define MP1_BASE__INST4_SEG4                       0
0552 #define MP1_BASE__INST4_SEG5                       0
0553 
0554 #define MP1_BASE__INST5_SEG0                       0
0555 #define MP1_BASE__INST5_SEG1                       0
0556 #define MP1_BASE__INST5_SEG2                       0
0557 #define MP1_BASE__INST5_SEG3                       0
0558 #define MP1_BASE__INST5_SEG4                       0
0559 #define MP1_BASE__INST5_SEG5                       0
0560 
0561 #define NBIO_BASE__INST0_SEG0                      0x00000000
0562 #define NBIO_BASE__INST0_SEG1                      0x00000014
0563 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0564 #define NBIO_BASE__INST0_SEG3                      0x00010400
0565 #define NBIO_BASE__INST0_SEG4                      0
0566 #define NBIO_BASE__INST0_SEG5                      0
0567 
0568 #define NBIO_BASE__INST1_SEG0                      0
0569 #define NBIO_BASE__INST1_SEG1                      0
0570 #define NBIO_BASE__INST1_SEG2                      0
0571 #define NBIO_BASE__INST1_SEG3                      0
0572 #define NBIO_BASE__INST1_SEG4                      0
0573 #define NBIO_BASE__INST1_SEG5                      0
0574 
0575 #define NBIO_BASE__INST2_SEG0                      0
0576 #define NBIO_BASE__INST2_SEG1                      0
0577 #define NBIO_BASE__INST2_SEG2                      0
0578 #define NBIO_BASE__INST2_SEG3                      0
0579 #define NBIO_BASE__INST2_SEG4                      0
0580 #define NBIO_BASE__INST2_SEG5                      0
0581 
0582 #define NBIO_BASE__INST3_SEG0                      0
0583 #define NBIO_BASE__INST3_SEG1                      0
0584 #define NBIO_BASE__INST3_SEG2                      0
0585 #define NBIO_BASE__INST3_SEG3                      0
0586 #define NBIO_BASE__INST3_SEG4                      0
0587 #define NBIO_BASE__INST3_SEG5                      0
0588 
0589 #define NBIO_BASE__INST4_SEG0                      0
0590 #define NBIO_BASE__INST4_SEG1                      0
0591 #define NBIO_BASE__INST4_SEG2                      0
0592 #define NBIO_BASE__INST4_SEG3                      0
0593 #define NBIO_BASE__INST4_SEG4                      0
0594 #define NBIO_BASE__INST4_SEG5                      0
0595 
0596 #define NBIO_BASE__INST5_SEG0                      0
0597 #define NBIO_BASE__INST5_SEG1                      0
0598 #define NBIO_BASE__INST5_SEG2                      0
0599 #define NBIO_BASE__INST5_SEG3                      0
0600 #define NBIO_BASE__INST5_SEG4                      0
0601 #define NBIO_BASE__INST5_SEG5                      0
0602 
0603 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0604 #define OSSSYS_BASE__INST0_SEG1                    0
0605 #define OSSSYS_BASE__INST0_SEG2                    0
0606 #define OSSSYS_BASE__INST0_SEG3                    0
0607 #define OSSSYS_BASE__INST0_SEG4                    0
0608 #define OSSSYS_BASE__INST0_SEG5                    0
0609 
0610 #define OSSSYS_BASE__INST1_SEG0                    0
0611 #define OSSSYS_BASE__INST1_SEG1                    0
0612 #define OSSSYS_BASE__INST1_SEG2                    0
0613 #define OSSSYS_BASE__INST1_SEG3                    0
0614 #define OSSSYS_BASE__INST1_SEG4                    0
0615 #define OSSSYS_BASE__INST1_SEG5                    0
0616 
0617 #define OSSSYS_BASE__INST2_SEG0                    0
0618 #define OSSSYS_BASE__INST2_SEG1                    0
0619 #define OSSSYS_BASE__INST2_SEG2                    0
0620 #define OSSSYS_BASE__INST2_SEG3                    0
0621 #define OSSSYS_BASE__INST2_SEG4                    0
0622 #define OSSSYS_BASE__INST2_SEG5                    0
0623 
0624 #define OSSSYS_BASE__INST3_SEG0                    0
0625 #define OSSSYS_BASE__INST3_SEG1                    0
0626 #define OSSSYS_BASE__INST3_SEG2                    0
0627 #define OSSSYS_BASE__INST3_SEG3                    0
0628 #define OSSSYS_BASE__INST3_SEG4                    0
0629 #define OSSSYS_BASE__INST3_SEG5                    0
0630 
0631 #define OSSSYS_BASE__INST4_SEG0                    0
0632 #define OSSSYS_BASE__INST4_SEG1                    0
0633 #define OSSSYS_BASE__INST4_SEG2                    0
0634 #define OSSSYS_BASE__INST4_SEG3                    0
0635 #define OSSSYS_BASE__INST4_SEG4                    0
0636 #define OSSSYS_BASE__INST4_SEG5                    0
0637 
0638 #define OSSSYS_BASE__INST5_SEG0                    0
0639 #define OSSSYS_BASE__INST5_SEG1                    0
0640 #define OSSSYS_BASE__INST5_SEG2                    0
0641 #define OSSSYS_BASE__INST5_SEG3                    0
0642 #define OSSSYS_BASE__INST5_SEG4                    0
0643 #define OSSSYS_BASE__INST5_SEG5                    0
0644 
0645 #define RSMU_BASE__INST0_SEG0                      0x00012000
0646 #define RSMU_BASE__INST0_SEG1                      0
0647 #define RSMU_BASE__INST0_SEG2                      0
0648 #define RSMU_BASE__INST0_SEG3                      0
0649 #define RSMU_BASE__INST0_SEG4                      0
0650 #define RSMU_BASE__INST0_SEG5                      0
0651 
0652 #define RSMU_BASE__INST1_SEG0                      0
0653 #define RSMU_BASE__INST1_SEG1                      0
0654 #define RSMU_BASE__INST1_SEG2                      0
0655 #define RSMU_BASE__INST1_SEG3                      0
0656 #define RSMU_BASE__INST1_SEG4                      0
0657 #define RSMU_BASE__INST1_SEG5                      0
0658 
0659 #define RSMU_BASE__INST2_SEG0                      0
0660 #define RSMU_BASE__INST2_SEG1                      0
0661 #define RSMU_BASE__INST2_SEG2                      0
0662 #define RSMU_BASE__INST2_SEG3                      0
0663 #define RSMU_BASE__INST2_SEG4                      0
0664 #define RSMU_BASE__INST2_SEG5                      0
0665 
0666 #define RSMU_BASE__INST3_SEG0                      0
0667 #define RSMU_BASE__INST3_SEG1                      0
0668 #define RSMU_BASE__INST3_SEG2                      0
0669 #define RSMU_BASE__INST3_SEG3                      0
0670 #define RSMU_BASE__INST3_SEG4                      0
0671 #define RSMU_BASE__INST3_SEG5                      0
0672 
0673 #define RSMU_BASE__INST4_SEG0                      0
0674 #define RSMU_BASE__INST4_SEG1                      0
0675 #define RSMU_BASE__INST4_SEG2                      0
0676 #define RSMU_BASE__INST4_SEG3                      0
0677 #define RSMU_BASE__INST4_SEG4                      0
0678 #define RSMU_BASE__INST4_SEG5                      0
0679 
0680 #define RSMU_BASE__INST5_SEG0                      0
0681 #define RSMU_BASE__INST5_SEG1                      0
0682 #define RSMU_BASE__INST5_SEG2                      0
0683 #define RSMU_BASE__INST5_SEG3                      0
0684 #define RSMU_BASE__INST5_SEG4                      0
0685 #define RSMU_BASE__INST5_SEG5                      0
0686 
0687 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0688 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0689 #define SMUIO_BASE__INST0_SEG2                     0
0690 #define SMUIO_BASE__INST0_SEG3                     0
0691 #define SMUIO_BASE__INST0_SEG4                     0
0692 #define SMUIO_BASE__INST0_SEG5                     0
0693 
0694 #define SMUIO_BASE__INST1_SEG0                     0
0695 #define SMUIO_BASE__INST1_SEG1                     0
0696 #define SMUIO_BASE__INST1_SEG2                     0
0697 #define SMUIO_BASE__INST1_SEG3                     0
0698 #define SMUIO_BASE__INST1_SEG4                     0
0699 #define SMUIO_BASE__INST1_SEG5                     0
0700 
0701 #define SMUIO_BASE__INST2_SEG0                     0
0702 #define SMUIO_BASE__INST2_SEG1                     0
0703 #define SMUIO_BASE__INST2_SEG2                     0
0704 #define SMUIO_BASE__INST2_SEG3                     0
0705 #define SMUIO_BASE__INST2_SEG4                     0
0706 #define SMUIO_BASE__INST2_SEG5                     0
0707 
0708 #define SMUIO_BASE__INST3_SEG0                     0
0709 #define SMUIO_BASE__INST3_SEG1                     0
0710 #define SMUIO_BASE__INST3_SEG2                     0
0711 #define SMUIO_BASE__INST3_SEG3                     0
0712 #define SMUIO_BASE__INST3_SEG4                     0
0713 #define SMUIO_BASE__INST3_SEG5                     0
0714 
0715 #define SMUIO_BASE__INST4_SEG0                     0
0716 #define SMUIO_BASE__INST4_SEG1                     0
0717 #define SMUIO_BASE__INST4_SEG2                     0
0718 #define SMUIO_BASE__INST4_SEG3                     0
0719 #define SMUIO_BASE__INST4_SEG4                     0
0720 #define SMUIO_BASE__INST4_SEG5                     0
0721 
0722 #define SMUIO_BASE__INST5_SEG0                     0
0723 #define SMUIO_BASE__INST5_SEG1                     0
0724 #define SMUIO_BASE__INST5_SEG2                     0
0725 #define SMUIO_BASE__INST5_SEG3                     0
0726 #define SMUIO_BASE__INST5_SEG4                     0
0727 #define SMUIO_BASE__INST5_SEG5                     0
0728 
0729 #define THM_BASE__INST0_SEG0                       0x00016600
0730 #define THM_BASE__INST0_SEG1                       0
0731 #define THM_BASE__INST0_SEG2                       0
0732 #define THM_BASE__INST0_SEG3                       0
0733 #define THM_BASE__INST0_SEG4                       0
0734 #define THM_BASE__INST0_SEG5                       0
0735 
0736 #define THM_BASE__INST1_SEG0                       0
0737 #define THM_BASE__INST1_SEG1                       0
0738 #define THM_BASE__INST1_SEG2                       0
0739 #define THM_BASE__INST1_SEG3                       0
0740 #define THM_BASE__INST1_SEG4                       0
0741 #define THM_BASE__INST1_SEG5                       0
0742 
0743 #define THM_BASE__INST2_SEG0                       0
0744 #define THM_BASE__INST2_SEG1                       0
0745 #define THM_BASE__INST2_SEG2                       0
0746 #define THM_BASE__INST2_SEG3                       0
0747 #define THM_BASE__INST2_SEG4                       0
0748 #define THM_BASE__INST2_SEG5                       0
0749 
0750 #define THM_BASE__INST3_SEG0                       0
0751 #define THM_BASE__INST3_SEG1                       0
0752 #define THM_BASE__INST3_SEG2                       0
0753 #define THM_BASE__INST3_SEG3                       0
0754 #define THM_BASE__INST3_SEG4                       0
0755 #define THM_BASE__INST3_SEG5                       0
0756 
0757 #define THM_BASE__INST4_SEG0                       0
0758 #define THM_BASE__INST4_SEG1                       0
0759 #define THM_BASE__INST4_SEG2                       0
0760 #define THM_BASE__INST4_SEG3                       0
0761 #define THM_BASE__INST4_SEG4                       0
0762 #define THM_BASE__INST4_SEG5                       0
0763 
0764 #define THM_BASE__INST5_SEG0                       0
0765 #define THM_BASE__INST5_SEG1                       0
0766 #define THM_BASE__INST5_SEG2                       0
0767 #define THM_BASE__INST5_SEG3                       0
0768 #define THM_BASE__INST5_SEG4                       0
0769 #define THM_BASE__INST5_SEG5                       0
0770 
0771 #define UMC_BASE__INST0_SEG0                       0x00014000
0772 #define UMC_BASE__INST0_SEG1                       0
0773 #define UMC_BASE__INST0_SEG2                       0
0774 #define UMC_BASE__INST0_SEG3                       0
0775 #define UMC_BASE__INST0_SEG4                       0
0776 #define UMC_BASE__INST0_SEG5                       0
0777 
0778 #define UMC_BASE__INST1_SEG0                       0
0779 #define UMC_BASE__INST1_SEG1                       0
0780 #define UMC_BASE__INST1_SEG2                       0
0781 #define UMC_BASE__INST1_SEG3                       0
0782 #define UMC_BASE__INST1_SEG4                       0
0783 #define UMC_BASE__INST1_SEG5                       0
0784 
0785 #define UMC_BASE__INST2_SEG0                       0
0786 #define UMC_BASE__INST2_SEG1                       0
0787 #define UMC_BASE__INST2_SEG2                       0
0788 #define UMC_BASE__INST2_SEG3                       0
0789 #define UMC_BASE__INST2_SEG4                       0
0790 #define UMC_BASE__INST2_SEG5                       0
0791 
0792 #define UMC_BASE__INST3_SEG0                       0
0793 #define UMC_BASE__INST3_SEG1                       0
0794 #define UMC_BASE__INST3_SEG2                       0
0795 #define UMC_BASE__INST3_SEG3                       0
0796 #define UMC_BASE__INST3_SEG4                       0
0797 #define UMC_BASE__INST3_SEG5                       0
0798 
0799 #define UMC_BASE__INST4_SEG0                       0
0800 #define UMC_BASE__INST4_SEG1                       0
0801 #define UMC_BASE__INST4_SEG2                       0
0802 #define UMC_BASE__INST4_SEG3                       0
0803 #define UMC_BASE__INST4_SEG4                       0
0804 #define UMC_BASE__INST4_SEG5                       0
0805 
0806 #define UMC_BASE__INST5_SEG0                       0
0807 #define UMC_BASE__INST5_SEG1                       0
0808 #define UMC_BASE__INST5_SEG2                       0
0809 #define UMC_BASE__INST5_SEG3                       0
0810 #define UMC_BASE__INST5_SEG4                       0
0811 #define UMC_BASE__INST5_SEG5                       0
0812 
0813 #define VCN_BASE__INST0_SEG0                       0x00007800
0814 #define VCN_BASE__INST0_SEG1                       0x00007E00
0815 #define VCN_BASE__INST0_SEG2                       0
0816 #define VCN_BASE__INST0_SEG3                       0
0817 #define VCN_BASE__INST0_SEG4                       0
0818 #define VCN_BASE__INST0_SEG5                       0
0819 
0820 #define VCN_BASE__INST1_SEG0                       0
0821 #define VCN_BASE__INST1_SEG1                       0
0822 #define VCN_BASE__INST1_SEG2                       0
0823 #define VCN_BASE__INST1_SEG3                       0
0824 #define VCN_BASE__INST1_SEG4                       0
0825 #define VCN_BASE__INST1_SEG5                       0
0826 
0827 #define VCN_BASE__INST2_SEG0                       0
0828 #define VCN_BASE__INST2_SEG1                       0
0829 #define VCN_BASE__INST2_SEG2                       0
0830 #define VCN_BASE__INST2_SEG3                       0
0831 #define VCN_BASE__INST2_SEG4                       0
0832 #define VCN_BASE__INST2_SEG5                       0
0833 
0834 #define VCN_BASE__INST3_SEG0                       0
0835 #define VCN_BASE__INST3_SEG1                       0
0836 #define VCN_BASE__INST3_SEG2                       0
0837 #define VCN_BASE__INST3_SEG3                       0
0838 #define VCN_BASE__INST3_SEG4                       0
0839 #define VCN_BASE__INST3_SEG5                       0
0840 
0841 #define VCN_BASE__INST4_SEG0                       0
0842 #define VCN_BASE__INST4_SEG1                       0
0843 #define VCN_BASE__INST4_SEG2                       0
0844 #define VCN_BASE__INST4_SEG3                       0
0845 #define VCN_BASE__INST4_SEG4                       0
0846 #define VCN_BASE__INST4_SEG5                       0
0847 
0848 #define VCN_BASE__INST5_SEG0                       0
0849 #define VCN_BASE__INST5_SEG1                       0
0850 #define VCN_BASE__INST5_SEG2                       0
0851 #define VCN_BASE__INST5_SEG3                       0
0852 #define VCN_BASE__INST5_SEG4                       0
0853 #define VCN_BASE__INST5_SEG5                       0
0854 
0855 #endif
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