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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef __MES_API_DEF_H__
0025 #define __MES_API_DEF_H__
0026 
0027 #pragma pack(push, 4)
0028 
0029 #define MES_API_VERSION 1
0030 
0031 /* Driver submits one API(cmd) as a single Frame and this command size is same
0032  * for all API to ease the debugging and parsing of ring buffer.
0033  */
0034 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
0035 
0036 /* To avoid command in scheduler context to be overwritten whenever multiple
0037  * interrupts come in, this creates another queue.
0038  */
0039 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
0040 
0041 enum MES_API_TYPE {
0042     MES_API_TYPE_SCHEDULER = 1,
0043     MES_API_TYPE_MAX
0044 };
0045 
0046 enum MES_SCH_API_OPCODE {
0047     MES_SCH_API_SET_HW_RSRC         = 0,
0048     MES_SCH_API_SET_SCHEDULING_CONFIG   = 1, /* agreegated db, quantums, etc */
0049     MES_SCH_API_ADD_QUEUE           = 2,
0050     MES_SCH_API_REMOVE_QUEUE        = 3,
0051     MES_SCH_API_PERFORM_YIELD       = 4,
0052     MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
0053     MES_SCH_API_SUSPEND         = 6,
0054     MES_SCH_API_RESUME          = 7,
0055     MES_SCH_API_RESET           = 8,
0056     MES_SCH_API_SET_LOG_BUFFER      = 9,
0057     MES_SCH_API_CHANGE_GANG_PRORITY     = 10,
0058     MES_SCH_API_QUERY_SCHEDULER_STATUS  = 11,
0059     MES_SCH_API_PROGRAM_GDS         = 12,
0060     MES_SCH_API_SET_DEBUG_VMID      = 13,
0061     MES_SCH_API_MISC            = 14,
0062     MES_SCH_API_UPDATE_ROOT_PAGE_TABLE      = 15,
0063     MES_SCH_API_AMD_LOG                     = 16,
0064     MES_SCH_API_MAX             = 0xFF
0065 };
0066 
0067 union MES_API_HEADER {
0068     struct {
0069         uint32_t type       : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
0070         uint32_t opcode     : 8;
0071         uint32_t dwsize     : 8; /* including header */
0072         uint32_t reserved   : 12;
0073     };
0074 
0075     uint32_t    u32All;
0076 };
0077 
0078 enum MES_AMD_PRIORITY_LEVEL {
0079     AMD_PRIORITY_LEVEL_LOW      = 0,
0080     AMD_PRIORITY_LEVEL_NORMAL   = 1,
0081     AMD_PRIORITY_LEVEL_MEDIUM   = 2,
0082     AMD_PRIORITY_LEVEL_HIGH     = 3,
0083     AMD_PRIORITY_LEVEL_REALTIME = 4,
0084     AMD_PRIORITY_NUM_LEVELS
0085 };
0086 
0087 enum MES_QUEUE_TYPE {
0088     MES_QUEUE_TYPE_GFX,
0089     MES_QUEUE_TYPE_COMPUTE,
0090     MES_QUEUE_TYPE_SDMA,
0091     MES_QUEUE_TYPE_MAX,
0092 };
0093 
0094 struct MES_API_STATUS {
0095     uint64_t    api_completion_fence_addr;
0096     uint64_t    api_completion_fence_value;
0097 };
0098 
0099 enum { MAX_COMPUTE_PIPES = 8 };
0100 enum { MAX_GFX_PIPES = 2 };
0101 enum { MAX_SDMA_PIPES = 2 };
0102 
0103 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
0104 enum { MAX_GFX_HQD_PER_PIPE = 8 };
0105 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
0106 
0107 enum { MAX_QUEUES_IN_A_GANG = 8 };
0108 
0109 enum VM_HUB_TYPE {
0110     VM_HUB_TYPE_GC = 0,
0111     VM_HUB_TYPE_MM = 1,
0112     VM_HUB_TYPE_MAX,
0113 };
0114 
0115 enum { VMID_INVALID = 0xffff };
0116 
0117 enum { MAX_VMID_GCHUB = 16 };
0118 enum { MAX_VMID_MMHUB = 16 };
0119 
0120 enum MES_LOG_OPERATION {
0121     MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
0122     MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
0123     MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
0124     MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
0125     MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
0126     MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
0127 };
0128 
0129 enum MES_LOG_CONTEXT_STATE {
0130     MES_LOG_CONTEXT_STATE_IDLE      = 0,
0131     MES_LOG_CONTEXT_STATE_RUNNING       = 1,
0132     MES_LOG_CONTEXT_STATE_READY     = 2,
0133     MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
0134     MES_LOG_CONTEXT_STATE_INVALID           = 0xF,
0135 };
0136 
0137 struct MES_LOG_CONTEXT_STATE_CHANGE {
0138     void                *h_context;
0139     enum MES_LOG_CONTEXT_STATE  new_context_state;
0140 };
0141 
0142 struct MES_LOG_QUEUE_NEW_WORK {
0143     uint64_t                   h_queue;
0144     uint64_t                   reserved;
0145 };
0146 
0147 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
0148     uint64_t                   h_queue;
0149     uint64_t                   h_sync_object;
0150 };
0151 
0152 struct MES_LOG_QUEUE_NO_MORE_WORK {
0153     uint64_t                   h_queue;
0154     uint64_t                   reserved;
0155 };
0156 
0157 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
0158     uint64_t                   h_queue;
0159     uint64_t                   h_sync_object;
0160 };
0161 
0162 struct MES_LOG_ENTRY_HEADER {
0163     uint32_t    first_free_entry_index;
0164     uint32_t    wraparound_count;
0165     uint64_t    number_of_entries;
0166     uint64_t    reserved[2];
0167 };
0168 
0169 struct MES_LOG_ENTRY_DATA {
0170     uint64_t    gpu_time_stamp;
0171     uint32_t    operation_type; /* operation_type is of MES_LOG_OPERATION type */
0172     uint32_t    reserved_operation_type_bits;
0173     union {
0174         struct MES_LOG_CONTEXT_STATE_CHANGE     context_state_change;
0175         struct MES_LOG_QUEUE_NEW_WORK           queue_new_work;
0176         struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
0177         struct MES_LOG_QUEUE_NO_MORE_WORK       queue_no_more_work;
0178         struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT   queue_wait_sync_object;
0179         uint64_t                                all[2];
0180     };
0181 };
0182 
0183 struct MES_LOG_BUFFER {
0184     struct MES_LOG_ENTRY_HEADER header;
0185     struct MES_LOG_ENTRY_DATA   entries[1];
0186 };
0187 
0188 enum MES_SWIP_TO_HWIP_DEF {
0189     MES_MAX_HWIP_SEGMENT = 6,
0190 };
0191 
0192 union MESAPI_SET_HW_RESOURCES {
0193     struct {
0194         union MES_API_HEADER    header;
0195         uint32_t        vmid_mask_mmhub;
0196         uint32_t        vmid_mask_gfxhub;
0197         uint32_t        gds_size;
0198         uint32_t        paging_vmid;
0199         uint32_t        compute_hqd_mask[MAX_COMPUTE_PIPES];
0200         uint32_t        gfx_hqd_mask[MAX_GFX_PIPES];
0201         uint32_t        sdma_hqd_mask[MAX_SDMA_PIPES];
0202         uint32_t        aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
0203         uint64_t        g_sch_ctx_gpu_mc_ptr;
0204         uint64_t        query_status_fence_gpu_mc_ptr;
0205         uint32_t        gc_base[MES_MAX_HWIP_SEGMENT];
0206         uint32_t        mmhub_base[MES_MAX_HWIP_SEGMENT];
0207         uint32_t        osssys_base[MES_MAX_HWIP_SEGMENT];
0208         struct MES_API_STATUS   api_status;
0209         union {
0210             struct {
0211                 uint32_t disable_reset  : 1;
0212                 uint32_t use_different_vmid_compute : 1;
0213                 uint32_t disable_mes_log   : 1;
0214                 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
0215                 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
0216                 uint32_t second_gfx_pipe_enabled : 1;
0217                 uint32_t enable_level_process_quantum_check : 1;
0218                 uint32_t apply_cwsr_program_all_vmid_sq_shader_tba_registers_wa : 1;
0219                 uint32_t enable_mqd_active_poll : 1;
0220                 uint32_t disable_timer_int : 1;
0221                 uint32_t reserved   : 22;
0222             };
0223             uint32_t    uint32_t_all;
0224         };
0225     };
0226 
0227     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0228 };
0229 
0230 union MESAPI__ADD_QUEUE {
0231     struct {
0232         union MES_API_HEADER        header;
0233         uint32_t            process_id;
0234         uint64_t            page_table_base_addr;
0235         uint64_t            process_va_start;
0236         uint64_t            process_va_end;
0237         uint64_t            process_quantum;
0238         uint64_t            process_context_addr;
0239         uint64_t            gang_quantum;
0240         uint64_t            gang_context_addr;
0241         uint32_t            inprocess_gang_priority;
0242         enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
0243         uint32_t            doorbell_offset;
0244         uint64_t            mqd_addr;
0245         uint64_t            wptr_addr;
0246         uint64_t                        h_context;
0247         uint64_t                        h_queue;
0248         enum MES_QUEUE_TYPE     queue_type;
0249         uint32_t            gds_base;
0250         uint32_t            gds_size;
0251         uint32_t            gws_base;
0252         uint32_t            gws_size;
0253         uint32_t            oa_mask;
0254         uint64_t                        trap_handler_addr;
0255         uint32_t                        vm_context_cntl;
0256 
0257         struct {
0258             uint32_t paging         : 1;
0259             uint32_t debug_vmid     : 4;
0260             uint32_t program_gds        : 1;
0261             uint32_t is_gang_suspended  : 1;
0262             uint32_t is_tmz_queue       : 1;
0263             uint32_t map_kiq_utility_queue  : 1;
0264             uint32_t reserved       : 23;
0265         };
0266         struct MES_API_STATUS       api_status;
0267     };
0268 
0269     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0270 };
0271 
0272 union MESAPI__REMOVE_QUEUE {
0273     struct {
0274         union MES_API_HEADER    header;
0275         uint32_t        doorbell_offset;
0276         uint64_t        gang_context_addr;
0277 
0278         struct {
0279             uint32_t unmap_legacy_gfx_queue   : 1;
0280             uint32_t unmap_kiq_utility_queue  : 1;
0281             uint32_t preempt_legacy_gfx_queue : 1;
0282             uint32_t reserved                 : 29;
0283         };
0284         struct MES_API_STATUS       api_status;
0285 
0286         uint32_t                    pipe_id;
0287         uint32_t                    queue_id;
0288 
0289         uint64_t                    tf_addr;
0290         uint32_t                    tf_data;
0291     };
0292 
0293     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0294 };
0295 
0296 union MESAPI__SET_SCHEDULING_CONFIG {
0297     struct {
0298         union MES_API_HEADER    header;
0299         /* Grace period when preempting another priority band for this
0300          * priority band. The value for idle priority band is ignored,
0301          * as it never preempts other bands.
0302          */
0303         uint64_t        grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
0304         /* Default quantum for scheduling across processes within
0305          * a priority band.
0306          */
0307         uint64_t        process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
0308         /* Default grace period for processes that preempt each other
0309          * within a priority band.
0310          */
0311         uint64_t        process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
0312         /* For normal level this field specifies the target GPU
0313          * percentage in situations when it's starved by the high level.
0314          * Valid values are between 0 and 50, with the default being 10.
0315          */
0316         uint32_t        normal_yield_percent;
0317         struct MES_API_STATUS   api_status;
0318     };
0319 
0320     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0321 };
0322 
0323 union MESAPI__PERFORM_YIELD {
0324     struct {
0325         union MES_API_HEADER    header;
0326         uint32_t        dummy;
0327         struct MES_API_STATUS   api_status;
0328     };
0329 
0330     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0331 };
0332 
0333 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
0334     struct {
0335         union MES_API_HEADER        header;
0336         uint32_t            inprocess_gang_priority;
0337         enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
0338         uint64_t            gang_quantum;
0339         uint64_t            gang_context_addr;
0340         struct MES_API_STATUS       api_status;
0341     };
0342 
0343     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0344 };
0345 
0346 union MESAPI__SUSPEND {
0347     struct {
0348         union MES_API_HEADER    header;
0349         /* false - suspend all gangs; true - specific gang */
0350         struct {
0351             uint32_t suspend_all_gangs  : 1;
0352             uint32_t reserved       : 31;
0353         };
0354         /* gang_context_addr is valid only if suspend_all = false */
0355         uint64_t        gang_context_addr;
0356 
0357         uint64_t        suspend_fence_addr;
0358         uint32_t        suspend_fence_value;
0359 
0360         struct MES_API_STATUS   api_status;
0361     };
0362 
0363     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0364 };
0365 
0366 union MESAPI__RESUME {
0367     struct {
0368         union MES_API_HEADER    header;
0369         /* false - resume all gangs; true - specified gang */
0370         struct {
0371             uint32_t resume_all_gangs   : 1;
0372             uint32_t reserved       : 31;
0373         };
0374         /* valid only if resume_all_gangs = false */
0375         uint64_t        gang_context_addr;
0376 
0377         struct MES_API_STATUS   api_status;
0378     };
0379 
0380     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0381 };
0382 
0383 union MESAPI__RESET {
0384     struct {
0385         union MES_API_HEADER        header;
0386 
0387         struct {
0388             /* Only reset the queue given by doorbell_offset (not entire gang) */
0389             uint32_t                reset_queue_only : 1;
0390             /* Hang detection first then reset any queues that are hung */
0391             uint32_t                hang_detect_then_reset : 1;
0392             /* Only do hang detection (no reset) */
0393             uint32_t                hang_detect_only : 1;
0394             /* Rest HP and LP kernel queues not managed by MES */
0395             uint32_t                reset_legacy_gfx : 1;
0396             uint32_t                reserved : 28;
0397         };
0398 
0399         uint64_t            gang_context_addr;
0400 
0401         /* valid only if reset_queue_only = true */
0402         uint32_t            doorbell_offset;
0403 
0404         /* valid only if hang_detect_then_reset = true */
0405         uint64_t            doorbell_offset_addr;
0406         enum MES_QUEUE_TYPE     queue_type;
0407 
0408         /* valid only if reset_legacy_gfx = true */
0409         uint32_t            pipe_id_lp;
0410         uint32_t            queue_id_lp;
0411         uint32_t            vmid_id_lp;
0412         uint64_t            mqd_mc_addr_lp;
0413         uint32_t            doorbell_offset_lp;
0414         uint64_t            wptr_addr_lp;
0415 
0416         uint32_t            pipe_id_hp;
0417         uint32_t            queue_id_hp;
0418         uint32_t            vmid_id_hp;
0419         uint64_t            mqd_mc_addr_hp;
0420         uint32_t            doorbell_offset_hp;
0421         uint64_t            wptr_addr_hp;
0422 
0423         struct MES_API_STATUS       api_status;
0424     };
0425 
0426     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0427 };
0428 
0429 union MESAPI__SET_LOGGING_BUFFER {
0430     struct {
0431         union MES_API_HEADER    header;
0432         /* There are separate log buffers for each queue type */
0433         enum MES_QUEUE_TYPE log_type;
0434         /* Log buffer GPU Address */
0435         uint64_t        logging_buffer_addr;
0436         /* number of entries in the log buffer */
0437         uint32_t        number_of_entries;
0438         /* Entry index at which CPU interrupt needs to be signalled */
0439         uint32_t        interrupt_entry;
0440 
0441         struct MES_API_STATUS   api_status;
0442     };
0443 
0444     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0445 };
0446 
0447 union MESAPI__QUERY_MES_STATUS {
0448     struct {
0449         union MES_API_HEADER    header;
0450         bool            mes_healthy; /* 0 - not healthy, 1 - healthy */
0451         struct MES_API_STATUS   api_status;
0452     };
0453 
0454     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0455 };
0456 
0457 union MESAPI__PROGRAM_GDS {
0458     struct {
0459         union MES_API_HEADER    header;
0460         uint64_t        process_context_addr;
0461         uint32_t        gds_base;
0462         uint32_t        gds_size;
0463         uint32_t        gws_base;
0464         uint32_t        gws_size;
0465         uint32_t        oa_mask;
0466         struct MES_API_STATUS   api_status;
0467     };
0468 
0469     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0470 };
0471 
0472 union MESAPI__SET_DEBUG_VMID {
0473     struct {
0474         union MES_API_HEADER    header;
0475         struct MES_API_STATUS   api_status;
0476         union {
0477             struct {
0478                 uint32_t use_gds    : 1;
0479                 uint32_t reserved   : 31;
0480             } flags;
0481             uint32_t    u32All;
0482         };
0483         uint32_t        reserved;
0484         uint32_t        debug_vmid;
0485         uint64_t        process_context_addr;
0486         uint64_t        page_table_base_addr;
0487         uint64_t        process_va_start;
0488         uint64_t        process_va_end;
0489         uint32_t        gds_base;
0490         uint32_t        gds_size;
0491         uint32_t        gws_base;
0492         uint32_t        gws_size;
0493         uint32_t        oa_mask;
0494     };
0495 
0496     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0497 };
0498 
0499 enum MESAPI_MISC_OPCODE {
0500     MESAPI_MISC__MODIFY_REG,
0501     MESAPI_MISC__INV_GART,
0502     MESAPI_MISC__QUERY_STATUS,
0503     MESAPI_MISC__MAX,
0504 };
0505 
0506 enum MODIFY_REG_SUBCODE {
0507     MODIFY_REG__OVERWRITE,
0508     MODIFY_REG__RMW_OR,
0509     MODIFY_REG__RMW_AND,
0510     MODIFY_REG__MAX,
0511 };
0512 
0513 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
0514 
0515 struct MODIFY_REG {
0516     enum MODIFY_REG_SUBCODE   subcode;
0517     uint32_t                  reg_offset;
0518     uint32_t                  reg_value;
0519 };
0520 
0521 struct INV_GART {
0522     uint64_t                  inv_range_va_start;
0523     uint64_t                  inv_range_size;
0524 };
0525 
0526 struct QUERY_STATUS {
0527     uint32_t context_id;
0528 };
0529 
0530 union MESAPI__MISC {
0531     struct {
0532         union MES_API_HEADER    header;
0533         enum MESAPI_MISC_OPCODE opcode;
0534         struct MES_API_STATUS   api_status;
0535 
0536         union {
0537             struct      MODIFY_REG modify_reg;
0538             struct      INV_GART inv_gart;
0539             struct      QUERY_STATUS query_status;
0540             uint32_t    data[MISC_DATA_MAX_SIZE_IN_DWORDS];
0541         };
0542     };
0543 
0544     uint32_t    max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0545 };
0546 
0547 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
0548     struct {
0549         union MES_API_HEADER        header;
0550         uint64_t                    page_table_base_addr;
0551         uint64_t                    process_context_addr;
0552         struct MES_API_STATUS       api_status;
0553     };
0554 
0555     uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0556 };
0557 
0558 union MESAPI_AMD_LOG {
0559     struct {
0560         union MES_API_HEADER        header;
0561         uint64_t                    p_buffer_memory;
0562         uint64_t                    p_buffer_size_used;
0563         struct MES_API_STATUS       api_status;
0564     };
0565 
0566     uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
0567 };
0568 
0569 #pragma pack(pop)
0570 #endif