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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef __KGD_PP_INTERFACE_H__
0025 #define __KGD_PP_INTERFACE_H__
0026 
0027 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
0028 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
0029 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
0030 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
0031 
0032 enum smu_event_type {
0033     SMU_EVENT_RESET_COMPLETE = 0,
0034 };
0035 
0036 struct amd_vce_state {
0037     /* vce clocks */
0038     u32 evclk;
0039     u32 ecclk;
0040     /* gpu clocks */
0041     u32 sclk;
0042     u32 mclk;
0043     u8 clk_idx;
0044     u8 pstate;
0045 };
0046 
0047 
0048 enum amd_dpm_forced_level {
0049     AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
0050     AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
0051     AMD_DPM_FORCED_LEVEL_LOW = 0x4,
0052     AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
0053     AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
0054     AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
0055     AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
0056     AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
0057     AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
0058     AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
0059 };
0060 
0061 enum amd_pm_state_type {
0062     /* not used for dpm */
0063     POWER_STATE_TYPE_DEFAULT,
0064     POWER_STATE_TYPE_POWERSAVE,
0065     /* user selectable states */
0066     POWER_STATE_TYPE_BATTERY,
0067     POWER_STATE_TYPE_BALANCED,
0068     POWER_STATE_TYPE_PERFORMANCE,
0069     /* internal states */
0070     POWER_STATE_TYPE_INTERNAL_UVD,
0071     POWER_STATE_TYPE_INTERNAL_UVD_SD,
0072     POWER_STATE_TYPE_INTERNAL_UVD_HD,
0073     POWER_STATE_TYPE_INTERNAL_UVD_HD2,
0074     POWER_STATE_TYPE_INTERNAL_UVD_MVC,
0075     POWER_STATE_TYPE_INTERNAL_BOOT,
0076     POWER_STATE_TYPE_INTERNAL_THERMAL,
0077     POWER_STATE_TYPE_INTERNAL_ACPI,
0078     POWER_STATE_TYPE_INTERNAL_ULV,
0079     POWER_STATE_TYPE_INTERNAL_3DPERF,
0080 };
0081 
0082 #define AMD_MAX_VCE_LEVELS 6
0083 
0084 enum amd_vce_level {
0085     AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
0086     AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
0087     AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
0088     AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
0089     AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
0090     AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
0091 };
0092 
0093 enum amd_fan_ctrl_mode {
0094     AMD_FAN_CTRL_NONE = 0,
0095     AMD_FAN_CTRL_MANUAL = 1,
0096     AMD_FAN_CTRL_AUTO = 2,
0097 };
0098 
0099 enum pp_clock_type {
0100     PP_SCLK,
0101     PP_MCLK,
0102     PP_PCIE,
0103     PP_SOCCLK,
0104     PP_FCLK,
0105     PP_DCEFCLK,
0106     PP_VCLK,
0107     PP_DCLK,
0108     OD_SCLK,
0109     OD_MCLK,
0110     OD_VDDC_CURVE,
0111     OD_RANGE,
0112     OD_VDDGFX_OFFSET,
0113     OD_CCLK,
0114 };
0115 
0116 enum amd_pp_sensors {
0117     AMDGPU_PP_SENSOR_GFX_SCLK = 0,
0118     AMDGPU_PP_SENSOR_CPU_CLK,
0119     AMDGPU_PP_SENSOR_VDDNB,
0120     AMDGPU_PP_SENSOR_VDDGFX,
0121     AMDGPU_PP_SENSOR_UVD_VCLK,
0122     AMDGPU_PP_SENSOR_UVD_DCLK,
0123     AMDGPU_PP_SENSOR_VCE_ECCLK,
0124     AMDGPU_PP_SENSOR_GPU_LOAD,
0125     AMDGPU_PP_SENSOR_MEM_LOAD,
0126     AMDGPU_PP_SENSOR_GFX_MCLK,
0127     AMDGPU_PP_SENSOR_GPU_TEMP,
0128     AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
0129     AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
0130     AMDGPU_PP_SENSOR_MEM_TEMP,
0131     AMDGPU_PP_SENSOR_VCE_POWER,
0132     AMDGPU_PP_SENSOR_UVD_POWER,
0133     AMDGPU_PP_SENSOR_GPU_POWER,
0134     AMDGPU_PP_SENSOR_SS_APU_SHARE,
0135     AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
0136     AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
0137     AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
0138     AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
0139     AMDGPU_PP_SENSOR_MIN_FAN_RPM,
0140     AMDGPU_PP_SENSOR_MAX_FAN_RPM,
0141     AMDGPU_PP_SENSOR_VCN_POWER_STATE,
0142 };
0143 
0144 enum amd_pp_task {
0145     AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
0146     AMD_PP_TASK_ENABLE_USER_STATE,
0147     AMD_PP_TASK_READJUST_POWER_STATE,
0148     AMD_PP_TASK_COMPLETE_INIT,
0149     AMD_PP_TASK_MAX
0150 };
0151 
0152 enum PP_SMC_POWER_PROFILE {
0153     PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
0154     PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
0155     PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
0156     PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
0157     PP_SMC_POWER_PROFILE_VR           = 0x4,
0158     PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
0159     PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
0160     PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
0161     PP_SMC_POWER_PROFILE_COUNT,
0162 };
0163 
0164 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
0165 
0166 
0167 
0168 enum {
0169     PP_GROUP_UNKNOWN = 0,
0170     PP_GROUP_GFX = 1,
0171     PP_GROUP_SYS,
0172     PP_GROUP_MAX
0173 };
0174 
0175 enum PP_OD_DPM_TABLE_COMMAND {
0176     PP_OD_EDIT_SCLK_VDDC_TABLE,
0177     PP_OD_EDIT_MCLK_VDDC_TABLE,
0178     PP_OD_EDIT_CCLK_VDDC_TABLE,
0179     PP_OD_EDIT_VDDC_CURVE,
0180     PP_OD_RESTORE_DEFAULT_TABLE,
0181     PP_OD_COMMIT_DPM_TABLE,
0182     PP_OD_EDIT_VDDGFX_OFFSET
0183 };
0184 
0185 struct pp_states_info {
0186     uint32_t nums;
0187     uint32_t states[16];
0188 };
0189 
0190 enum PP_HWMON_TEMP {
0191     PP_TEMP_EDGE = 0,
0192     PP_TEMP_JUNCTION,
0193     PP_TEMP_MEM,
0194     PP_TEMP_MAX
0195 };
0196 
0197 enum pp_mp1_state {
0198     PP_MP1_STATE_NONE,
0199     PP_MP1_STATE_SHUTDOWN,
0200     PP_MP1_STATE_UNLOAD,
0201     PP_MP1_STATE_RESET,
0202 };
0203 
0204 enum pp_df_cstate {
0205     DF_CSTATE_DISALLOW = 0,
0206     DF_CSTATE_ALLOW,
0207 };
0208 
0209 /**
0210  * DOC: amdgpu_pp_power
0211  *
0212  * APU power is managed to system-level requirements through the PPT
0213  * (package power tracking) feature. PPT is intended to limit power to the
0214  * requirements of the power source and could be dynamically updated to
0215  * maximize APU performance within the system power budget.
0216  *
0217  * Two types of power measurement can be requested, where supported, with
0218  * :c:type:`enum pp_power_type <pp_power_type>`.
0219  */
0220 
0221 /**
0222  * enum pp_power_limit_level - Used to query the power limits
0223  *
0224  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
0225  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
0226  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
0227  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
0228  */
0229 enum pp_power_limit_level
0230 {
0231     PP_PWR_LIMIT_MIN = -1,
0232     PP_PWR_LIMIT_CURRENT,
0233     PP_PWR_LIMIT_DEFAULT,
0234     PP_PWR_LIMIT_MAX,
0235 };
0236 
0237 /**
0238  * enum pp_power_type - Used to specify the type of the requested power
0239  *
0240  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
0241  * moving average of APU power (default ~5000 ms).
0242  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
0243  * where supported.
0244  */
0245 enum pp_power_type
0246 {
0247     PP_PWR_TYPE_SUSTAINED,
0248     PP_PWR_TYPE_FAST,
0249 };
0250 
0251 #define PP_GROUP_MASK        0xF0000000
0252 #define PP_GROUP_SHIFT       28
0253 
0254 #define PP_BLOCK_MASK        0x0FFFFF00
0255 #define PP_BLOCK_SHIFT       8
0256 
0257 #define PP_BLOCK_GFX_CG         0x01
0258 #define PP_BLOCK_GFX_MG         0x02
0259 #define PP_BLOCK_GFX_3D         0x04
0260 #define PP_BLOCK_GFX_RLC        0x08
0261 #define PP_BLOCK_GFX_CP         0x10
0262 #define PP_BLOCK_SYS_BIF        0x01
0263 #define PP_BLOCK_SYS_MC         0x02
0264 #define PP_BLOCK_SYS_ROM        0x04
0265 #define PP_BLOCK_SYS_DRM        0x08
0266 #define PP_BLOCK_SYS_HDP        0x10
0267 #define PP_BLOCK_SYS_SDMA       0x20
0268 
0269 #define PP_STATE_MASK           0x0000000F
0270 #define PP_STATE_SHIFT          0
0271 #define PP_STATE_SUPPORT_MASK   0x000000F0
0272 #define PP_STATE_SUPPORT_SHIFT  0
0273 
0274 #define PP_STATE_CG             0x01
0275 #define PP_STATE_LS             0x02
0276 #define PP_STATE_DS             0x04
0277 #define PP_STATE_SD             0x08
0278 #define PP_STATE_SUPPORT_CG     0x10
0279 #define PP_STATE_SUPPORT_LS     0x20
0280 #define PP_STATE_SUPPORT_DS     0x40
0281 #define PP_STATE_SUPPORT_SD     0x80
0282 
0283 #define PP_CG_MSG_ID(group, block, support, state) \
0284         ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
0285         (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
0286 
0287 #define XGMI_MODE_PSTATE_D3 0
0288 #define XGMI_MODE_PSTATE_D0 1
0289 
0290 #define NUM_HBM_INSTANCES 4
0291 
0292 struct seq_file;
0293 enum amd_pp_clock_type;
0294 struct amd_pp_simple_clock_info;
0295 struct amd_pp_display_configuration;
0296 struct amd_pp_clock_info;
0297 struct pp_display_clock_request;
0298 struct pp_clock_levels_with_voltage;
0299 struct pp_clock_levels_with_latency;
0300 struct amd_pp_clocks;
0301 struct pp_smu_wm_range_sets;
0302 struct pp_smu_nv_clock_table;
0303 struct dpm_clocks;
0304 
0305 struct amd_pm_funcs {
0306 /* export for dpm on ci and si */
0307     int (*pre_set_power_state)(void *handle);
0308     int (*set_power_state)(void *handle);
0309     void (*post_set_power_state)(void *handle);
0310     void (*display_configuration_changed)(void *handle);
0311     void (*print_power_state)(void *handle, void *ps);
0312     bool (*vblank_too_short)(void *handle);
0313     void (*enable_bapm)(void *handle, bool enable);
0314     int (*check_state_equal)(void *handle,
0315                 void  *cps,
0316                 void  *rps,
0317                 bool  *equal);
0318 /* export for sysfs */
0319     int (*set_fan_control_mode)(void *handle, u32 mode);
0320     int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
0321     int (*set_fan_speed_pwm)(void *handle, u32 speed);
0322     int (*get_fan_speed_pwm)(void *handle, u32 *speed);
0323     int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
0324     int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
0325     int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
0326     int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
0327     int (*get_sclk_od)(void *handle);
0328     int (*set_sclk_od)(void *handle, uint32_t value);
0329     int (*get_mclk_od)(void *handle);
0330     int (*set_mclk_od)(void *handle, uint32_t value);
0331     int (*read_sensor)(void *handle, int idx, void *value, int *size);
0332     enum amd_dpm_forced_level (*get_performance_level)(void *handle);
0333     enum amd_pm_state_type (*get_current_power_state)(void *handle);
0334     int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
0335     int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
0336     int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
0337     int (*get_pp_table)(void *handle, char **table);
0338     int (*set_pp_table)(void *handle, const char *buf, size_t size);
0339     void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
0340     int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
0341 /* export to amdgpu */
0342     struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
0343     int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
0344             enum amd_pm_state_type *user_state);
0345     int (*load_firmware)(void *handle);
0346     int (*wait_for_fw_loading_complete)(void *handle);
0347     int (*set_powergating_by_smu)(void *handle,
0348                 uint32_t block_type, bool gate);
0349     int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
0350     int (*set_power_limit)(void *handle, uint32_t n);
0351     int (*get_power_limit)(void *handle, uint32_t *limit,
0352             enum pp_power_limit_level pp_limit_level,
0353             enum pp_power_type power_type);
0354     int (*get_power_profile_mode)(void *handle, char *buf);
0355     int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
0356     int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
0357     int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
0358     int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
0359     int (*smu_i2c_bus_access)(void *handle, bool acquire);
0360     int (*gfx_state_change_set)(void *handle, uint32_t state);
0361 /* export to DC */
0362     u32 (*get_sclk)(void *handle, bool low);
0363     u32 (*get_mclk)(void *handle, bool low);
0364     int (*display_configuration_change)(void *handle,
0365         const struct amd_pp_display_configuration *input);
0366     int (*get_display_power_level)(void *handle,
0367         struct amd_pp_simple_clock_info *output);
0368     int (*get_current_clocks)(void *handle,
0369         struct amd_pp_clock_info *clocks);
0370     int (*get_clock_by_type)(void *handle,
0371         enum amd_pp_clock_type type,
0372         struct amd_pp_clocks *clocks);
0373     int (*get_clock_by_type_with_latency)(void *handle,
0374         enum amd_pp_clock_type type,
0375         struct pp_clock_levels_with_latency *clocks);
0376     int (*get_clock_by_type_with_voltage)(void *handle,
0377         enum amd_pp_clock_type type,
0378         struct pp_clock_levels_with_voltage *clocks);
0379     int (*set_watermarks_for_clocks_ranges)(void *handle,
0380                         void *clock_ranges);
0381     int (*display_clock_voltage_request)(void *handle,
0382                 struct pp_display_clock_request *clock);
0383     int (*get_display_mode_validation_clocks)(void *handle,
0384         struct amd_pp_simple_clock_info *clocks);
0385     int (*notify_smu_enable_pwe)(void *handle);
0386     int (*enable_mgpu_fan_boost)(void *handle);
0387     int (*set_active_display_count)(void *handle, uint32_t count);
0388     int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
0389     int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
0390     int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
0391     int (*get_asic_baco_capability)(void *handle, bool *cap);
0392     int (*get_asic_baco_state)(void *handle, int *state);
0393     int (*set_asic_baco_state)(void *handle, int state);
0394     int (*get_ppfeature_status)(void *handle, char *buf);
0395     int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
0396     int (*asic_reset_mode_2)(void *handle);
0397     int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
0398     int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
0399     ssize_t (*get_gpu_metrics)(void *handle, void **table);
0400     int (*set_watermarks_for_clock_ranges)(void *handle,
0401                            struct pp_smu_wm_range_sets *ranges);
0402     int (*display_disable_memory_clock_switch)(void *handle,
0403                            bool disable_memory_clock_switch);
0404     int (*get_max_sustainable_clocks_by_dc)(void *handle,
0405                         struct pp_smu_nv_clock_table *max_clocks);
0406     int (*get_uclk_dpm_states)(void *handle,
0407                    unsigned int *clock_values_in_khz,
0408                    unsigned int *num_states);
0409     int (*get_dpm_clock_table)(void *handle,
0410                    struct dpm_clocks *clock_table);
0411     int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
0412     void (*pm_compute_clocks)(void *handle);
0413 };
0414 
0415 struct metrics_table_header {
0416     uint16_t            structure_size;
0417     uint8_t             format_revision;
0418     uint8_t             content_revision;
0419 };
0420 
0421 /*
0422  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
0423  * Use gpu_metrics_v1_1 or later instead.
0424  */
0425 struct gpu_metrics_v1_0 {
0426     struct metrics_table_header common_header;
0427 
0428     /* Driver attached timestamp (in ns) */
0429     uint64_t            system_clock_counter;
0430 
0431     /* Temperature */
0432     uint16_t            temperature_edge;
0433     uint16_t            temperature_hotspot;
0434     uint16_t            temperature_mem;
0435     uint16_t            temperature_vrgfx;
0436     uint16_t            temperature_vrsoc;
0437     uint16_t            temperature_vrmem;
0438 
0439     /* Utilization */
0440     uint16_t            average_gfx_activity;
0441     uint16_t            average_umc_activity; // memory controller
0442     uint16_t            average_mm_activity; // UVD or VCN
0443 
0444     /* Power/Energy */
0445     uint16_t            average_socket_power;
0446     uint32_t            energy_accumulator;
0447 
0448     /* Average clocks */
0449     uint16_t            average_gfxclk_frequency;
0450     uint16_t            average_socclk_frequency;
0451     uint16_t            average_uclk_frequency;
0452     uint16_t            average_vclk0_frequency;
0453     uint16_t            average_dclk0_frequency;
0454     uint16_t            average_vclk1_frequency;
0455     uint16_t            average_dclk1_frequency;
0456 
0457     /* Current clocks */
0458     uint16_t            current_gfxclk;
0459     uint16_t            current_socclk;
0460     uint16_t            current_uclk;
0461     uint16_t            current_vclk0;
0462     uint16_t            current_dclk0;
0463     uint16_t            current_vclk1;
0464     uint16_t            current_dclk1;
0465 
0466     /* Throttle status */
0467     uint32_t            throttle_status;
0468 
0469     /* Fans */
0470     uint16_t            current_fan_speed;
0471 
0472     /* Link width/speed */
0473     uint8_t             pcie_link_width;
0474     uint8_t             pcie_link_speed; // in 0.1 GT/s
0475 };
0476 
0477 struct gpu_metrics_v1_1 {
0478     struct metrics_table_header common_header;
0479 
0480     /* Temperature */
0481     uint16_t            temperature_edge;
0482     uint16_t            temperature_hotspot;
0483     uint16_t            temperature_mem;
0484     uint16_t            temperature_vrgfx;
0485     uint16_t            temperature_vrsoc;
0486     uint16_t            temperature_vrmem;
0487 
0488     /* Utilization */
0489     uint16_t            average_gfx_activity;
0490     uint16_t            average_umc_activity; // memory controller
0491     uint16_t            average_mm_activity; // UVD or VCN
0492 
0493     /* Power/Energy */
0494     uint16_t            average_socket_power;
0495     uint64_t            energy_accumulator;
0496 
0497     /* Driver attached timestamp (in ns) */
0498     uint64_t            system_clock_counter;
0499 
0500     /* Average clocks */
0501     uint16_t            average_gfxclk_frequency;
0502     uint16_t            average_socclk_frequency;
0503     uint16_t            average_uclk_frequency;
0504     uint16_t            average_vclk0_frequency;
0505     uint16_t            average_dclk0_frequency;
0506     uint16_t            average_vclk1_frequency;
0507     uint16_t            average_dclk1_frequency;
0508 
0509     /* Current clocks */
0510     uint16_t            current_gfxclk;
0511     uint16_t            current_socclk;
0512     uint16_t            current_uclk;
0513     uint16_t            current_vclk0;
0514     uint16_t            current_dclk0;
0515     uint16_t            current_vclk1;
0516     uint16_t            current_dclk1;
0517 
0518     /* Throttle status */
0519     uint32_t            throttle_status;
0520 
0521     /* Fans */
0522     uint16_t            current_fan_speed;
0523 
0524     /* Link width/speed */
0525     uint16_t            pcie_link_width;
0526     uint16_t            pcie_link_speed; // in 0.1 GT/s
0527 
0528     uint16_t            padding;
0529 
0530     uint32_t            gfx_activity_acc;
0531     uint32_t            mem_activity_acc;
0532 
0533     uint16_t            temperature_hbm[NUM_HBM_INSTANCES];
0534 };
0535 
0536 struct gpu_metrics_v1_2 {
0537     struct metrics_table_header common_header;
0538 
0539     /* Temperature */
0540     uint16_t            temperature_edge;
0541     uint16_t            temperature_hotspot;
0542     uint16_t            temperature_mem;
0543     uint16_t            temperature_vrgfx;
0544     uint16_t            temperature_vrsoc;
0545     uint16_t            temperature_vrmem;
0546 
0547     /* Utilization */
0548     uint16_t            average_gfx_activity;
0549     uint16_t            average_umc_activity; // memory controller
0550     uint16_t            average_mm_activity; // UVD or VCN
0551 
0552     /* Power/Energy */
0553     uint16_t            average_socket_power;
0554     uint64_t            energy_accumulator;
0555 
0556     /* Driver attached timestamp (in ns) */
0557     uint64_t            system_clock_counter;
0558 
0559     /* Average clocks */
0560     uint16_t            average_gfxclk_frequency;
0561     uint16_t            average_socclk_frequency;
0562     uint16_t            average_uclk_frequency;
0563     uint16_t            average_vclk0_frequency;
0564     uint16_t            average_dclk0_frequency;
0565     uint16_t            average_vclk1_frequency;
0566     uint16_t            average_dclk1_frequency;
0567 
0568     /* Current clocks */
0569     uint16_t            current_gfxclk;
0570     uint16_t            current_socclk;
0571     uint16_t            current_uclk;
0572     uint16_t            current_vclk0;
0573     uint16_t            current_dclk0;
0574     uint16_t            current_vclk1;
0575     uint16_t            current_dclk1;
0576 
0577     /* Throttle status (ASIC dependent) */
0578     uint32_t            throttle_status;
0579 
0580     /* Fans */
0581     uint16_t            current_fan_speed;
0582 
0583     /* Link width/speed */
0584     uint16_t            pcie_link_width;
0585     uint16_t            pcie_link_speed; // in 0.1 GT/s
0586 
0587     uint16_t            padding;
0588 
0589     uint32_t            gfx_activity_acc;
0590     uint32_t            mem_activity_acc;
0591 
0592     uint16_t            temperature_hbm[NUM_HBM_INSTANCES];
0593 
0594     /* PMFW attached timestamp (10ns resolution) */
0595     uint64_t            firmware_timestamp;
0596 };
0597 
0598 struct gpu_metrics_v1_3 {
0599     struct metrics_table_header common_header;
0600 
0601     /* Temperature */
0602     uint16_t            temperature_edge;
0603     uint16_t            temperature_hotspot;
0604     uint16_t            temperature_mem;
0605     uint16_t            temperature_vrgfx;
0606     uint16_t            temperature_vrsoc;
0607     uint16_t            temperature_vrmem;
0608 
0609     /* Utilization */
0610     uint16_t            average_gfx_activity;
0611     uint16_t            average_umc_activity; // memory controller
0612     uint16_t            average_mm_activity; // UVD or VCN
0613 
0614     /* Power/Energy */
0615     uint16_t            average_socket_power;
0616     uint64_t            energy_accumulator;
0617 
0618     /* Driver attached timestamp (in ns) */
0619     uint64_t            system_clock_counter;
0620 
0621     /* Average clocks */
0622     uint16_t            average_gfxclk_frequency;
0623     uint16_t            average_socclk_frequency;
0624     uint16_t            average_uclk_frequency;
0625     uint16_t            average_vclk0_frequency;
0626     uint16_t            average_dclk0_frequency;
0627     uint16_t            average_vclk1_frequency;
0628     uint16_t            average_dclk1_frequency;
0629 
0630     /* Current clocks */
0631     uint16_t            current_gfxclk;
0632     uint16_t            current_socclk;
0633     uint16_t            current_uclk;
0634     uint16_t            current_vclk0;
0635     uint16_t            current_dclk0;
0636     uint16_t            current_vclk1;
0637     uint16_t            current_dclk1;
0638 
0639     /* Throttle status */
0640     uint32_t            throttle_status;
0641 
0642     /* Fans */
0643     uint16_t            current_fan_speed;
0644 
0645     /* Link width/speed */
0646     uint16_t            pcie_link_width;
0647     uint16_t            pcie_link_speed; // in 0.1 GT/s
0648 
0649     uint16_t            padding;
0650 
0651     uint32_t            gfx_activity_acc;
0652     uint32_t            mem_activity_acc;
0653 
0654     uint16_t            temperature_hbm[NUM_HBM_INSTANCES];
0655 
0656     /* PMFW attached timestamp (10ns resolution) */
0657     uint64_t            firmware_timestamp;
0658 
0659     /* Voltage (mV) */
0660     uint16_t            voltage_soc;
0661     uint16_t            voltage_gfx;
0662     uint16_t            voltage_mem;
0663 
0664     uint16_t            padding1;
0665 
0666     /* Throttle status (ASIC independent) */
0667     uint64_t            indep_throttle_status;
0668 };
0669 
0670 /*
0671  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
0672  * Use gpu_metrics_v2_1 or later instead.
0673  */
0674 struct gpu_metrics_v2_0 {
0675     struct metrics_table_header common_header;
0676 
0677     /* Driver attached timestamp (in ns) */
0678     uint64_t            system_clock_counter;
0679 
0680     /* Temperature */
0681     uint16_t            temperature_gfx; // gfx temperature on APUs
0682     uint16_t            temperature_soc; // soc temperature on APUs
0683     uint16_t            temperature_core[8]; // CPU core temperature on APUs
0684     uint16_t            temperature_l3[2];
0685 
0686     /* Utilization */
0687     uint16_t            average_gfx_activity;
0688     uint16_t            average_mm_activity; // UVD or VCN
0689 
0690     /* Power/Energy */
0691     uint16_t            average_socket_power; // dGPU + APU power on A + A platform
0692     uint16_t            average_cpu_power;
0693     uint16_t            average_soc_power;
0694     uint16_t            average_gfx_power;
0695     uint16_t            average_core_power[8]; // CPU core power on APUs
0696 
0697     /* Average clocks */
0698     uint16_t            average_gfxclk_frequency;
0699     uint16_t            average_socclk_frequency;
0700     uint16_t            average_uclk_frequency;
0701     uint16_t            average_fclk_frequency;
0702     uint16_t            average_vclk_frequency;
0703     uint16_t            average_dclk_frequency;
0704 
0705     /* Current clocks */
0706     uint16_t            current_gfxclk;
0707     uint16_t            current_socclk;
0708     uint16_t            current_uclk;
0709     uint16_t            current_fclk;
0710     uint16_t            current_vclk;
0711     uint16_t            current_dclk;
0712     uint16_t            current_coreclk[8]; // CPU core clocks
0713     uint16_t            current_l3clk[2];
0714 
0715     /* Throttle status */
0716     uint32_t            throttle_status;
0717 
0718     /* Fans */
0719     uint16_t            fan_pwm;
0720 
0721     uint16_t            padding;
0722 };
0723 
0724 struct gpu_metrics_v2_1 {
0725     struct metrics_table_header common_header;
0726 
0727     /* Temperature */
0728     uint16_t            temperature_gfx; // gfx temperature on APUs
0729     uint16_t            temperature_soc; // soc temperature on APUs
0730     uint16_t            temperature_core[8]; // CPU core temperature on APUs
0731     uint16_t            temperature_l3[2];
0732 
0733     /* Utilization */
0734     uint16_t            average_gfx_activity;
0735     uint16_t            average_mm_activity; // UVD or VCN
0736 
0737     /* Driver attached timestamp (in ns) */
0738     uint64_t            system_clock_counter;
0739 
0740     /* Power/Energy */
0741     uint16_t            average_socket_power; // dGPU + APU power on A + A platform
0742     uint16_t            average_cpu_power;
0743     uint16_t            average_soc_power;
0744     uint16_t            average_gfx_power;
0745     uint16_t            average_core_power[8]; // CPU core power on APUs
0746 
0747     /* Average clocks */
0748     uint16_t            average_gfxclk_frequency;
0749     uint16_t            average_socclk_frequency;
0750     uint16_t            average_uclk_frequency;
0751     uint16_t            average_fclk_frequency;
0752     uint16_t            average_vclk_frequency;
0753     uint16_t            average_dclk_frequency;
0754 
0755     /* Current clocks */
0756     uint16_t            current_gfxclk;
0757     uint16_t            current_socclk;
0758     uint16_t            current_uclk;
0759     uint16_t            current_fclk;
0760     uint16_t            current_vclk;
0761     uint16_t            current_dclk;
0762     uint16_t            current_coreclk[8]; // CPU core clocks
0763     uint16_t            current_l3clk[2];
0764 
0765     /* Throttle status */
0766     uint32_t            throttle_status;
0767 
0768     /* Fans */
0769     uint16_t            fan_pwm;
0770 
0771     uint16_t            padding[3];
0772 };
0773 
0774 struct gpu_metrics_v2_2 {
0775     struct metrics_table_header common_header;
0776 
0777     /* Temperature */
0778     uint16_t            temperature_gfx; // gfx temperature on APUs
0779     uint16_t            temperature_soc; // soc temperature on APUs
0780     uint16_t            temperature_core[8]; // CPU core temperature on APUs
0781     uint16_t            temperature_l3[2];
0782 
0783     /* Utilization */
0784     uint16_t            average_gfx_activity;
0785     uint16_t            average_mm_activity; // UVD or VCN
0786 
0787     /* Driver attached timestamp (in ns) */
0788     uint64_t            system_clock_counter;
0789 
0790     /* Power/Energy */
0791     uint16_t            average_socket_power; // dGPU + APU power on A + A platform
0792     uint16_t            average_cpu_power;
0793     uint16_t            average_soc_power;
0794     uint16_t            average_gfx_power;
0795     uint16_t            average_core_power[8]; // CPU core power on APUs
0796 
0797     /* Average clocks */
0798     uint16_t            average_gfxclk_frequency;
0799     uint16_t            average_socclk_frequency;
0800     uint16_t            average_uclk_frequency;
0801     uint16_t            average_fclk_frequency;
0802     uint16_t            average_vclk_frequency;
0803     uint16_t            average_dclk_frequency;
0804 
0805     /* Current clocks */
0806     uint16_t            current_gfxclk;
0807     uint16_t            current_socclk;
0808     uint16_t            current_uclk;
0809     uint16_t            current_fclk;
0810     uint16_t            current_vclk;
0811     uint16_t            current_dclk;
0812     uint16_t            current_coreclk[8]; // CPU core clocks
0813     uint16_t            current_l3clk[2];
0814 
0815     /* Throttle status (ASIC dependent) */
0816     uint32_t            throttle_status;
0817 
0818     /* Fans */
0819     uint16_t            fan_pwm;
0820 
0821     uint16_t            padding[3];
0822 
0823     /* Throttle status (ASIC independent) */
0824     uint64_t            indep_throttle_status;
0825 };
0826 
0827 #endif
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