amd/include/kgd_kfd_interface.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 /*
0024  * This file defines the private interface between the
0025  * AMD kernel graphics drivers and the AMD KFD.
0026  */
0027
0028 #ifndef KGD_KFD_INTERFACE_H_INCLUDED
0029 #define KGD_KFD_INTERFACE_H_INCLUDED
0030
0031 #include <linux/types.h>
0032 #include <linux/bitmap.h>
0033 #include <linux/dma-fence.h>
0034
0035 struct pci_dev;
0036 struct amdgpu_device;
0037
0038 #define KGD_MAX_QUEUES 128
0039
0040 struct kfd_dev;
0041 struct kgd_mem;
0042
0043 enum kfd_preempt_type {
0044     KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
0045     KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
0046     KFD_PREEMPT_TYPE_WAVEFRONT_SAVE
0047 };
0048
0049 struct kfd_vm_fault_info {
0050     uint64_t    page_addr;
0051     uint32_t    vmid;
0052     uint32_t    mc_id;
0053     uint32_t    status;
0054     bool        prot_valid;
0055     bool        prot_read;
0056     bool        prot_write;
0057     bool        prot_exec;
0058 };
0059
0060 struct kfd_cu_info {
0061     uint32_t num_shader_engines;
0062     uint32_t num_shader_arrays_per_engine;
0063     uint32_t num_cu_per_sh;
0064     uint32_t cu_active_number;
0065     uint32_t cu_ao_mask;
0066     uint32_t simd_per_cu;
0067     uint32_t max_waves_per_simd;
0068     uint32_t wave_front_size;
0069     uint32_t max_scratch_slots_per_cu;
0070     uint32_t lds_size;
0071     uint32_t cu_bitmap[4][4];
0072 };
0073
0074 /* For getting GPU local memory information from KGD */
0075 struct kfd_local_mem_info {
0076     uint64_t local_mem_size_private;
0077     uint64_t local_mem_size_public;
0078     uint32_t vram_width;
0079     uint32_t mem_clk_max;
0080 };
0081
0082 enum kgd_memory_pool {
0083     KGD_POOL_SYSTEM_CACHEABLE = 1,
0084     KGD_POOL_SYSTEM_WRITECOMBINE = 2,
0085     KGD_POOL_FRAMEBUFFER = 3,
0086 };
0087
0088 /**
0089  * enum kfd_sched_policy
0090  *
0091  * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
0092  * scheduling. In this scheduling mode we're using the firmware code to
0093  * schedule the user mode queues and kernel queues such as HIQ and DIQ.
0094  * the HIQ queue is used as a special queue that dispatches the configuration
0095  * to the cp and the user mode queues list that are currently running.
0096  * the DIQ queue is a debugging queue that dispatches debugging commands to the
0097  * firmware.
0098  * in this scheduling mode user mode queues over subscription feature is
0099  * enabled.
0100  *
0101  * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
0102  * subscription feature disabled.
0103  *
0104  * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
0105  * set the command processor registers and sets the queues "manually". This
0106  * mode is used *ONLY* for debugging proposes.
0107  *
0108  */
0109 enum kfd_sched_policy {
0110     KFD_SCHED_POLICY_HWS = 0,
0111     KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
0112     KFD_SCHED_POLICY_NO_HWS
0113 };
0114
0115 struct kgd2kfd_shared_resources {
0116     /* Bit n == 1 means VMID n is available for KFD. */
0117     unsigned int compute_vmid_bitmap;
0118
0119     /* number of pipes per mec */
0120     uint32_t num_pipe_per_mec;
0121
0122     /* number of queues per pipe */
0123     uint32_t num_queue_per_pipe;
0124
0125     /* Bit n == 1 means Queue n is available for KFD */
0126     DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
0127
0128     /* SDMA doorbell assignments (SOC15 and later chips only). Only
0129      * specific doorbells are routed to each SDMA engine. Others
0130      * are routed to IH and VCN. They are not usable by the CP.
0131      */
0132     uint32_t *sdma_doorbell_idx;
0133
0134     /* From SOC15 onward, the doorbell index range not usable for CP
0135      * queues.
0136      */
0137     uint32_t non_cp_doorbells_start;
0138     uint32_t non_cp_doorbells_end;
0139
0140     /* Base address of doorbell aperture. */
0141     phys_addr_t doorbell_physical_address;
0142
0143     /* Size in bytes of doorbell aperture. */
0144     size_t doorbell_aperture_size;
0145
0146     /* Number of bytes at start of aperture reserved for KGD. */
0147     size_t doorbell_start_offset;
0148
0149     /* GPUVM address space size in bytes */
0150     uint64_t gpuvm_size;
0151
0152     /* Minor device number of the render node */
0153     int drm_render_minor;
0154
0155     bool enable_mes;
0156 };
0157
0158 struct tile_config {
0159     uint32_t *tile_config_ptr;
0160     uint32_t *macro_tile_config_ptr;
0161     uint32_t num_tile_configs;
0162     uint32_t num_macro_tile_configs;
0163
0164     uint32_t gb_addr_config;
0165     uint32_t num_banks;
0166     uint32_t num_ranks;
0167 };
0168
0169 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
0170
0171 /**
0172  * struct kfd2kgd_calls
0173  *
0174  * @program_sh_mem_settings: A function that should initiate the memory
0175  * properties such as main aperture memory type (cache / non cached) and
0176  * secondary aperture base address, size and memory type.
0177  * This function is used only for no cp scheduling mode.
0178  *
0179  * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
0180  * scheduling mode. Only used for no cp scheduling mode.
0181  *
0182  * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
0183  * sceduling mode.
0184  *
0185  * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
0186  * used only for no HWS mode.
0187  *
0188  * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
0189  * Array is allocated with kmalloc, needs to be freed with kfree by caller.
0190  *
0191  * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
0192  * Array is allocated with kmalloc, needs to be freed with kfree by caller.
0193  *
0194  * @hqd_is_occupies: Checks if a hqd slot is occupied.
0195  *
0196  * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
0197  *
0198  * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
0199  *
0200  * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
0201  * SDMA hqd slot.
0202  *
0203  * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
0204  * Only used for no cp scheduling mode
0205  *
0206  * @set_vm_context_page_table_base: Program page table base for a VMID
0207  *
0208  * @invalidate_tlbs: Invalidate TLBs for a specific PASID
0209  *
0210  * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
0211  *
0212  * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
0213  * IH ring entry. This function allows the KFD ISR to get the VMID
0214  * from the fault status register as early as possible.
0215  *
0216  * @get_cu_occupancy: Function pointer that returns to caller the number
0217  * of wave fronts that are in flight for all of the queues of a process
0218  * as identified by its pasid. It is important to note that the value
0219  * returned by this function is a snapshot of current moment and cannot
0220  * guarantee any minimum for the number of waves in-flight. This function
0221  * is defined for devices that belong to GFX9 and later GFX families. Care
0222  * must be taken in calling this function as it is not defined for devices
0223  * that belong to GFX8 and below GFX families.
0224  *
0225  * This structure contains function pointers to services that the kgd driver
0226  * provides to amdkfd driver.
0227  *
0228  */
0229 struct kfd2kgd_calls {
0230     /* Register access functions */
0231     void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
0232             uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
0233             uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
0234
0235     int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid,
0236                     unsigned int vmid);
0237
0238     int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id);
0239
0240     int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
0241             uint32_t queue_id, uint32_t __user *wptr,
0242             uint32_t wptr_shift, uint32_t wptr_mask,
0243             struct mm_struct *mm);
0244
0245     int (*hiq_mqd_load)(struct amdgpu_device *adev, void *mqd,
0246                 uint32_t pipe_id, uint32_t queue_id,
0247                 uint32_t doorbell_off);
0248
0249     int (*hqd_sdma_load)(struct amdgpu_device *adev, void *mqd,
0250                  uint32_t __user *wptr, struct mm_struct *mm);
0251
0252     int (*hqd_dump)(struct amdgpu_device *adev,
0253             uint32_t pipe_id, uint32_t queue_id,
0254             uint32_t (**dump)[2], uint32_t *n_regs);
0255
0256     int (*hqd_sdma_dump)(struct amdgpu_device *adev,
0257                  uint32_t engine_id, uint32_t queue_id,
0258                  uint32_t (**dump)[2], uint32_t *n_regs);
0259
0260     bool (*hqd_is_occupied)(struct amdgpu_device *adev,
0261                 uint64_t queue_address, uint32_t pipe_id,
0262                 uint32_t queue_id);
0263
0264     int (*hqd_destroy)(struct amdgpu_device *adev, void *mqd,
0265                 uint32_t reset_type, unsigned int timeout,
0266                 uint32_t pipe_id, uint32_t queue_id);
0267
0268     bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
0269
0270     int (*hqd_sdma_destroy)(struct amdgpu_device *adev, void *mqd,
0271                 unsigned int timeout);
0272
0273     int (*wave_control_execute)(struct amdgpu_device *adev,
0274                     uint32_t gfx_index_val,
0275                     uint32_t sq_cmd);
0276     bool (*get_atc_vmid_pasid_mapping_info)(struct amdgpu_device *adev,
0277                     uint8_t vmid,
0278                     uint16_t *p_pasid);
0279
0280     /* No longer needed from GFXv9 onward. The scratch base address is
0281      * passed to the shader by the CP. It's the user mode driver's
0282      * responsibility.
0283      */
0284     void (*set_scratch_backing_va)(struct amdgpu_device *adev,
0285                 uint64_t va, uint32_t vmid);
0286
0287     void (*set_vm_context_page_table_base)(struct amdgpu_device *adev,
0288             uint32_t vmid, uint64_t page_table_base);
0289     uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
0290
0291     void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
0292             int *wave_cnt, int *max_waves_per_cu);
0293     void (*program_trap_handler_settings)(struct amdgpu_device *adev,
0294             uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);
0295 };
0296
0297 #endif  /* KGD_KFD_INTERFACE_H_INCLUDED */