ivsrcid/sdma2/irqsrcs_sdma2_5_0.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #ifndef __IRQSRCS_SDMA2_5_0_H__
0023 #define __IRQSRCS_SDMA2_5_0_H__
0024
0025
0026 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE              217     // 0xD9 SDMA atomic*_rtn ops complete
0027 #define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT               218     // 0xDA SDMA atomic CMPSWAP loop timeout
0028 #define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT                   219     // 0xDB sdma mid-command buffer preempt interrupt
0029 #define SDMA2_5_0__SRCID__SDMA_ECC                          220     // 0xDC ECC  Error
0030 #define SDMA2_5_0__SRCID__SDMA_PAGE_FAULT                   221     // 0xDD Page Fault Error from UTCL2 when nack=3
0031 #define SDMA2_5_0__SRCID__SDMA_PAGE_NULL                    222     // 0xDE Page Null from UTCL2 when nack=2
0032 #define SDMA2_5_0__SRCID__SDMA_XNACK                        223     // 0xDF Page retry  timeout after UTCL2 return nack=1
0033 #define SDMA2_5_0__SRCID__SDMA_TRAP                         224     // 0xE0 Trap
0034 #define SDMA2_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT       225     // 0xE1 0xDAGPF (Sem incomplete timeout)
0035 #define SDMA2_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT        226     // 0xE2 Semaphore wait fail timeout
0036 #define SDMA2_5_0__SRCID__SDMA_SRAM_ECC                     228     // 0xE4 SRAM ECC Error
0037 #define SDMA2_5_0__SRCID__SDMA_PREEMPT                      240     // 0xF0 SDMA New Run List
0038 #define SDMA2_5_0__SRCID__SDMA_VM_HOLE                      242     // 0xF2 MC or SEM address in VM hole
0039 #define SDMA2_5_0__SRCID__SDMA_CTXEMPTY                     243     // 0xF3 Context Empty
0040 #define SDMA2_5_0__SRCID__SDMA_DOORBELL_INVALID             244     // 0xF4 Doorbell BE invalid
0041 #define SDMA2_5_0__SRCID__SDMA_FROZEN                       245     // 0xF5 SDMA Frozen
0042 #define SDMA2_5_0__SRCID__SDMA_POLL_TIMEOUT                 246     // 0xF6 SRBM read poll timeout
0043 #define SDMA2_5_0__SRCID__SDMA_SRBMWRITE                    247     // 0xF7 SRBM write Protection
0044
0045 #endif // __IRQSRCS_SDMA2_5_0_H__