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0001 /* 0002 * Copyright 2017 Advanced Micro Devices, Inc. 0003 * 0004 * Permission is hereby granted, free of charge, to any person obtaining a 0005 * copy of this software and associated documentation files (the "Software"), 0006 * to deal in the Software without restriction, including without limitation 0007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 0008 * and/or sell copies of the Software, and to permit persons to whom the 0009 * Software is furnished to do so, subject to the following conditions: 0010 * 0011 * The above copyright notice and this permission notice shall be included in 0012 * all copies or substantial portions of the Software. 0013 * 0014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 0015 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 0016 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 0017 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 0018 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 0019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 0020 * OTHER DEALINGS IN THE SOFTWARE. 0021 * 0022 * Authors: AMD 0023 * 0024 */ 0025 0026 #ifndef __IRQSRCS_DCN_1_0_H__ 0027 #define __IRQSRCS_DCN_1_0_H__ 0028 0029 0030 #define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 0031 #define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 0032 0033 #define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0034 #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 0035 0036 #define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0037 #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 0038 0039 #define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0040 #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 0041 0042 #define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0043 #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 0044 0045 #define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0046 #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 0047 0048 #define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0049 #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 0050 0051 #define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0052 #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 0053 0054 #define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0055 #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 0056 0057 #define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0058 #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 0059 0060 #define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0061 #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 0062 0063 #define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0064 #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 0065 0066 #define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0067 #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 0068 0069 #define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0070 #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 0071 0072 #define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0073 #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 0074 0075 #define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0076 #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 0077 0078 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 0079 #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 0080 0081 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 0082 #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 0083 0084 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 0085 #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 0086 0087 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 0088 #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 0089 0090 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 0091 #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 0092 0093 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 0094 #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 0095 0096 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level 0097 #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 0098 0099 #define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level 0100 #define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 0101 0102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level 0103 #define DCN_1_0__CTXID__DMCU_SCP_INT 14 0104 0105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 0106 #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 0107 0108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 0109 #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 0110 0111 #define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 0112 #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 0113 0114 #define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level 0115 #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 0116 0117 #define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level 0118 #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 0119 0120 #define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level 0121 #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 0122 0123 #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 0124 #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 0125 0126 #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 0127 #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 0128 0129 #define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 0130 #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 0131 0132 #define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0133 #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 0134 0135 #define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0136 #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 0137 0138 #define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0139 #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 0140 0141 #define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0142 #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 0143 0144 #define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0145 #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 0146 0147 #define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0148 #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 0149 0150 #define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0151 #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 0152 0153 #define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 0154 #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 0155 0156 #define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level 0157 #define DCN_1_0__CTXID__DC_HPD1_INT 0 0158 0159 #define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0160 #define DCN_1_0__CTXID__DC_HPD2_INT 1 0161 0162 #define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0163 #define DCN_1_0__CTXID__DC_HPD3_INT 2 0164 0165 #define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0166 #define DCN_1_0__CTXID__DC_HPD4_INT 3 0167 0168 #define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0169 #define DCN_1_0__CTXID__DC_HPD5_INT 4 0170 0171 #define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0172 #define DCN_1_0__CTXID__DC_HPD6_INT 5 0173 0174 #define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level 0175 #define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 0176 0177 #define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0178 #define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 0179 0180 #define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0181 #define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 0182 0183 #define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0184 #define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 0185 0186 #define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0187 #define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 0188 0189 #define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0190 #define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 0191 0192 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level 0193 #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 0194 0195 #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0196 #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 0197 0198 #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0199 #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 0200 0201 #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0202 #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 0203 0204 #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0205 #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 0206 0207 #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0208 #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 0209 0210 #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0211 #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 0212 0213 #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0214 #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 0215 0216 #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0217 #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 0218 0219 #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0220 #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 0221 0222 #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0223 #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 0224 0225 #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0226 #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 0227 0228 #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0229 #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 0230 0231 #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0232 #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 0233 0234 #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0235 #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 0236 0237 #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0238 #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 0239 0240 #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0241 #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 0242 0243 #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0244 #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 0245 0246 #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0247 #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 0248 0249 #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0250 #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 0251 0252 #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0253 #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 0254 0255 #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0256 #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 0257 0258 #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0259 #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 0260 0261 #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0262 #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 0263 0264 #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 0265 #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 0266 0267 #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0268 #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 0269 0270 #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0271 #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 0272 0273 #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0274 #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 0275 0276 #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0277 #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 0278 0279 #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0280 #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 0281 0282 #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0283 #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 0284 0285 #define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level 0286 #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 0287 0288 #define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0289 #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 0290 0291 #define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0292 #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 0293 0294 #define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0295 #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 0296 0297 #define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0298 #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 0299 0300 #define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0301 #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 0302 0303 #define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 0304 #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 0305 0306 #define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0307 #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 0308 0309 #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level 0310 #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 0311 0312 #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0313 #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 0314 0315 #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0316 #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 0317 0318 #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0319 #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 0320 0321 #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0322 #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 0323 0324 #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0325 #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 0326 0327 #define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 0328 #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 0329 0330 #define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 0331 #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 0332 0333 #define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 0334 #define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 0335 0336 #define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 0337 #define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 0338 0339 #define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0340 #define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 0341 0342 #define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0343 #define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 0344 0345 #define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0346 #define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 0347 0348 #define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0349 #define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 0350 0351 #define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0352 #define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 0353 0354 #define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0355 #define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 0356 0357 #define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0358 #define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 0359 0360 #define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0361 #define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 0362 0363 #define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0364 #define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 0365 0366 #define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 0367 #define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 0368 0369 #define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0370 #define DCN_1_0__CTXID__VGA_CRT_INT 12 0371 0372 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0373 #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 0374 0375 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0376 #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 0377 0378 #define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0379 #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 0380 0381 #define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0382 #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 0383 0384 #define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0385 #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 0386 0387 #define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0388 #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 0389 0390 #define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0391 #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 0392 0393 #define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0394 #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 0395 0396 #define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 0397 #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 0398 0399 #define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 0400 #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 0401 0402 #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0403 #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 0404 0405 #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0406 #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 0407 0408 #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0409 #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 0410 0411 #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0412 #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 0413 0414 #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0415 #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 0416 0417 #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 0418 #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 0419 0420 #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0421 #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 0422 0423 #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0424 #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 0425 0426 #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0427 #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 0428 0429 #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0430 #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 0431 0432 #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0433 #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 0434 0435 #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0436 #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 0437 0438 #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0439 #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 0440 0441 #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0442 #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 0443 0444 #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0445 #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 0446 0447 #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0448 #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 0449 0450 #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0451 #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 0452 0453 #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0454 #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 0455 0456 #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0457 #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 0458 0459 #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0460 #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 0461 0462 #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0463 #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 0464 0465 #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 0466 #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 0467 0468 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0469 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 0470 0471 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0472 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 0473 0474 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0475 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 0476 0477 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0478 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 0479 0480 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0481 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 0482 0483 #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 0484 #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 0485 0486 #define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level 0487 #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 0488 0489 #define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 0490 #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 0491 0492 #define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 0493 #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 0494 0495 #define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 0496 #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 0497 0498 #define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0499 #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 0500 0501 #define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 0502 #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 0503 0504 #define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0505 #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 0506 0507 #define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0508 #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 0509 0510 #define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0511 #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 0512 0513 #define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0514 #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 0515 0516 #define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0517 #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 0518 0519 #define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0520 #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 0521 0522 #define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0523 #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 0524 0525 #define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0526 #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 0527 0528 #define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0529 #define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 0530 0531 #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0532 #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 0533 0534 #define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0535 #define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 0536 0537 #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0538 #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 0539 0540 #define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0541 #define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 0542 0543 #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0544 #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 0545 0546 #define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0547 #define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 0548 0549 #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0550 #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 0551 0552 #define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0553 #define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 0554 0555 #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0556 #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 0557 0558 #define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0559 #define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 0560 0561 #define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 0562 #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 0563 0564 #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0565 #define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0566 #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0567 #define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0568 #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0569 #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0570 0571 #define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 0572 #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 0573 0574 #define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 0575 #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 0576 0577 #define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 0578 #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 0579 0580 #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 0581 #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 0582 0583 #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 0584 #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 0585 0586 #define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0587 #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 0588 0589 #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0590 #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 0591 0592 #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0593 #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 0594 0595 #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0596 #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 0597 0598 #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0599 #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 0600 0601 #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0602 #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 0603 0604 #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0605 #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 0606 0607 #define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse 0608 #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 0609 0610 #define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0611 #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 0612 0613 #define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0614 #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 0615 0616 #define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0617 #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 0618 0619 #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0620 #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 0621 0622 #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0623 #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 0624 0625 #define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0626 #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 0627 0628 #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0629 #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 0630 0631 #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0632 #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 0633 0634 #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0635 #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 0636 0637 #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0638 #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 0639 0640 #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0641 #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 0642 0643 #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0644 #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 0645 0646 #define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 0647 #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 0648 0649 #define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0650 #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 0651 0652 #define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0653 #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 0654 0655 #define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0656 #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 0657 0658 #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0659 #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 0660 0661 #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0662 #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 0663 0664 #define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0665 #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 0666 0667 #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0668 #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 0669 0670 #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0671 #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 0672 0673 #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0674 #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 0675 0676 #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0677 #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 0678 0679 #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0680 #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 0681 0682 #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0683 #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 0684 0685 #define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 0686 #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 0687 0688 #define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0689 #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 0690 0691 #define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0692 #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 0693 0694 #define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0695 #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 0696 0697 #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0698 #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 0699 0700 #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0701 #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 0702 0703 #define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0704 #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 0705 0706 #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0707 #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 0708 0709 #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0710 #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 0711 0712 #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0713 #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 0714 0715 #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0716 #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 0717 0718 #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0719 #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 0720 0721 #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0722 #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 0723 0724 #define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 0725 #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 0726 0727 #define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0728 #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 0729 0730 #define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0731 #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 0732 0733 #define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0734 #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 0735 0736 #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0737 #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 0738 0739 #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0740 #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 0741 0742 #define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0743 #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 0744 0745 #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0746 #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 0747 0748 #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0749 #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 0750 0751 #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0752 #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 0753 0754 #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0755 #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 0756 0757 #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0758 #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 0759 0760 #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0761 #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 0762 0763 #define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 0764 #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 0765 0766 #define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 0767 #define DCN_1_0__CTXID__DC_D1_VBLANK 0 0768 0769 #define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 0770 #define DCN_1_0__CTXID__DC_D1_VLINE1 1 0771 0772 #define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 0773 #define DCN_1_0__CTXID__DC_D1_VLINE2 2 0774 0775 #define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0776 #define DCN_1_0__CTXID__DC_D2_VBLANK 3 0777 0778 #define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0779 #define DCN_1_0__CTXID__DC_D2_VLINE1 4 0780 0781 #define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0782 #define DCN_1_0__CTXID__DC_D2_VLINE2 5 0783 0784 #define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0785 #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 0786 0787 #define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 0788 #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 0789 0790 #define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 0791 #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 0792 0793 #define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0794 #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 0795 0796 #define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0797 #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 0798 0799 #define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0800 #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 0801 0802 #define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0803 #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 0804 0805 #define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0806 #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 0807 0808 #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 0809 #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 0810 0811 #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 0812 #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 0813 0814 #define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0815 #define DCN_1_0__CTXID__DC_D3_VBLANK 9 0816 0817 #define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0818 #define DCN_1_0__CTXID__DC_D3_VLINE1 10 0819 0820 #define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0821 #define DCN_1_0__CTXID__DC_D3_VLINE2 11 0822 0823 #define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0824 #define DCN_1_0__CTXID__DC_D4_VBLANK 12 0825 0826 #define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0827 #define DCN_1_0__CTXID__DC_D4_VLINE1 13 0828 0829 #define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0830 #define DCN_1_0__CTXID__DC_D4_VLINE2 14 0831 0832 #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 0833 #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 0834 0835 #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 0836 #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 0837 0838 #define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0839 #define DCN_1_0__CTXID__DC_D5_VBLANK 9 0840 0841 #define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0842 #define DCN_1_0__CTXID__DC_D5_VLINE1 10 0843 0844 #define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0845 #define DCN_1_0__CTXID__DC_D5_VLINE2 11 0846 0847 #define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0848 #define DCN_1_0__CTXID__DC_D6_VBLANK 12 0849 0850 #define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0851 #define DCN_1_0__CTXID__DC_D6_VLINE1 13 0852 0853 #define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0854 #define DCN_1_0__CTXID__DC_D6_VLINE2 14 0855 0856 #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 0857 #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 0858 0859 #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 0860 #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 0861 0862 #define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0863 #define DCN_1_0__CTXID__DC_D7_VBLANK 9 0864 0865 #define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0866 #define DCN_1_0__CTXID__DC_D7_VLINE1 10 0867 0868 #define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0869 #define DCN_1_0__CTXID__DC_D7_VLINE2 11 0870 0871 #define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0872 #define DCN_1_0__CTXID__DC_D8_VBLANK 12 0873 0874 #define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0875 #define DCN_1_0__CTXID__DC_D8_VLINE1 13 0876 0877 #define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0878 #define DCN_1_0__CTXID__DC_D8_VLINE2 14 0879 0880 #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 0881 #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 0882 0883 #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 0884 #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 0885 0886 #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 0887 #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 0888 0889 #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 0890 #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 0891 0892 #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 0893 #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 0894 0895 #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 0896 #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 0897 0898 #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 0899 #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 0900 0901 #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 0902 #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 0903 0904 #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 0905 #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 0906 0907 #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 0908 #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 0909 0910 #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 0911 #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 0912 0913 #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0914 #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 0915 0916 #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0917 #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 0918 0919 #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 0920 #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 0921 0922 #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0923 #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 0924 0925 #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 0926 #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 0927 0928 #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 0929 #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 0930 0931 #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 0932 #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 0933 0934 #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0935 #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 0936 0937 #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 0938 #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 0939 0940 #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0941 #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 0942 0943 #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 0944 #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 0945 0946 #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 0947 #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 0948 0949 #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 0950 #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 0951 0952 #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 0953 #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 0954 0955 #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 0956 #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 0957 0958 #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse 0959 #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 0960 0961 #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 0962 #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 0963 0964 #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 0965 #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 0966 0967 #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 0968 #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 0969 0970 #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 0971 #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 0972 0973 #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 0974 #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 0975 0976 #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 0977 #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 0978 0979 #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 0980 #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 0981 0982 #define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0983 #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 0984 0985 #define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0986 #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 0987 0988 #define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0989 #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 0990 0991 #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0992 #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 0993 0994 #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 0995 #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 0996 0997 #define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 0998 #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 0999 1000 #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1001 #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 1002 1003 #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1004 #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 1005 1006 #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1007 #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 1008 1009 #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1010 #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 1011 1012 #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1013 #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 1014 1015 #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1016 #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 1017 1018 #define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1019 #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 1020 1021 #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1022 #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 1023 1024 #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1025 #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 1026 1027 #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1028 #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 1029 1030 #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1031 #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 1032 1033 #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1034 #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 1035 1036 #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 1037 #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 1038 1039 #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1040 #define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1041 #define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1042 #define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1043 #define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1044 #define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1045 1046 #define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1047 #define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1048 #define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1049 #define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1050 #define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1051 #define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1052 1053 #define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 1054 #define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 1055 #define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 1056 #define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 1057 #define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 1058 #define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1059 1060 #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1061 #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 1062 1063 #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1064 #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 1065 1066 #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1067 #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 1068 1069 #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1070 #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 1071 1072 #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1073 #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 1074 1075 #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1076 #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 1077 1078 #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1079 #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 1080 1081 #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1082 #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 1083 1084 #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1085 #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 1086 1087 #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1088 #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 1089 1090 #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1091 #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 1092 1093 #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1094 #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 1095 1096 #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1097 #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 1098 1099 #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1100 #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 1101 1102 #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1103 #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 1104 1105 #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1106 #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 1107 1108 #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1109 #define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1110 #define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1111 #define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1112 #define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1113 #define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1114 #define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1115 #define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1116 1117 #define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1118 #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1119 #define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1120 #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1121 #define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1122 #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1123 1124 #define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1125 #define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1126 #define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1127 #define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1128 #define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1129 #define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1130 #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1131 #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1132 1133 #define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 0x68 1134 #define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT 6 1135 #define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 0x68 // DMCUB_IHC_outbox1_ready_int IHC_DMCUB_outbox1_ready_int_ack DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE24 Level/Pulse 1136 #define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT 8 1137 1138 #endif // __IRQSRCS_DCN_1_0_H__
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