amd/include/dm_pp_interface.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _DM_PP_INTERFACE_
0024 #define _DM_PP_INTERFACE_
0025
0026 #include "dm_services_types.h"
0027
0028 #define PP_MAX_CLOCK_LEVELS 16
0029
0030 enum amd_pp_display_config_type{
0031     AMD_PP_DisplayConfigType_None = 0,
0032     AMD_PP_DisplayConfigType_DP54 ,
0033     AMD_PP_DisplayConfigType_DP432 ,
0034     AMD_PP_DisplayConfigType_DP324 ,
0035     AMD_PP_DisplayConfigType_DP27,
0036     AMD_PP_DisplayConfigType_DP243,
0037     AMD_PP_DisplayConfigType_DP216,
0038     AMD_PP_DisplayConfigType_DP162,
0039     AMD_PP_DisplayConfigType_HDMI6G ,
0040     AMD_PP_DisplayConfigType_HDMI297 ,
0041     AMD_PP_DisplayConfigType_HDMI162,
0042     AMD_PP_DisplayConfigType_LVDS,
0043     AMD_PP_DisplayConfigType_DVI,
0044     AMD_PP_DisplayConfigType_WIRELESS,
0045     AMD_PP_DisplayConfigType_VGA
0046 };
0047
0048 struct single_display_configuration
0049 {
0050     uint32_t controller_index;
0051     uint32_t controller_id;
0052     uint32_t signal_type;
0053     uint32_t display_state;
0054     /* phy id for the primary internal transmitter */
0055     uint8_t primary_transmitter_phyi_d;
0056     /* bitmap with the active lanes */
0057     uint8_t primary_transmitter_active_lanemap;
0058     /* phy id for the secondary internal transmitter (for dual-link dvi) */
0059     uint8_t secondary_transmitter_phy_id;
0060     /* bitmap with the active lanes */
0061     uint8_t secondary_transmitter_active_lanemap;
0062     /* misc phy settings for SMU. */
0063     uint32_t config_flags;
0064     uint32_t display_type;
0065     uint32_t view_resolution_cx;
0066     uint32_t view_resolution_cy;
0067     enum amd_pp_display_config_type displayconfigtype;
0068     uint32_t vertical_refresh; /* for active display */
0069 };
0070
0071 #define MAX_NUM_DISPLAY 32
0072
0073 struct amd_pp_display_configuration {
0074     bool nb_pstate_switch_disable;/* controls NB PState switch */
0075     bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
0076     bool cpu_pstate_disable;
0077     uint32_t cpu_pstate_separation_time;
0078
0079     uint32_t num_display;  /* total number of display*/
0080     uint32_t num_path_including_non_display;
0081     uint32_t crossfire_display_index;
0082     uint32_t min_mem_set_clock;
0083     uint32_t min_core_set_clock;
0084     /* unit 10KHz x bit*/
0085     uint32_t min_bus_bandwidth;
0086     /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
0087     uint32_t min_core_set_clock_in_sr;
0088
0089     struct single_display_configuration displays[MAX_NUM_DISPLAY];
0090
0091     uint32_t vrefresh; /* for active display*/
0092
0093     uint32_t min_vblank_time; /* for active display*/
0094     bool multi_monitor_in_sync;
0095     /* Controller Index of primary display - used in MCLK SMC switching hang
0096      * SW Workaround*/
0097     uint32_t crtc_index;
0098     /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
0099     uint32_t line_time_in_us;
0100     bool invalid_vblank_time;
0101
0102     uint32_t display_clk;
0103     /*
0104      * for given display configuration if multimonitormnsync == false then
0105      * Memory clock DPMS with this latency or below is allowed, DPMS with
0106      * higher latency not allowed.
0107      */
0108     uint32_t dce_tolerable_mclk_in_active_latency;
0109     uint32_t min_dcef_set_clk;
0110     uint32_t min_dcef_deep_sleep_set_clk;
0111 };
0112
0113 struct amd_pp_simple_clock_info {
0114     uint32_t    engine_max_clock;
0115     uint32_t    memory_max_clock;
0116     uint32_t    level;
0117 };
0118
0119 enum PP_DAL_POWERLEVEL {
0120     PP_DAL_POWERLEVEL_INVALID = 0,
0121     PP_DAL_POWERLEVEL_ULTRALOW,
0122     PP_DAL_POWERLEVEL_LOW,
0123     PP_DAL_POWERLEVEL_NOMINAL,
0124     PP_DAL_POWERLEVEL_PERFORMANCE,
0125
0126     PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
0127     PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
0128     PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
0129     PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
0130     PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
0131     PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
0132     PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
0133     PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
0134 };
0135
0136 struct amd_pp_clock_info {
0137     uint32_t min_engine_clock;
0138     uint32_t max_engine_clock;
0139     uint32_t min_memory_clock;
0140     uint32_t max_memory_clock;
0141     uint32_t min_bus_bandwidth;
0142     uint32_t max_bus_bandwidth;
0143     uint32_t max_engine_clock_in_sr;
0144     uint32_t min_engine_clock_in_sr;
0145     enum PP_DAL_POWERLEVEL max_clocks_state;
0146 };
0147
0148 enum amd_pp_clock_type {
0149     amd_pp_disp_clock = 1,
0150     amd_pp_sys_clock,
0151     amd_pp_mem_clock,
0152     amd_pp_dcef_clock,
0153     amd_pp_soc_clock,
0154     amd_pp_pixel_clock,
0155     amd_pp_phy_clock,
0156     amd_pp_dcf_clock,
0157     amd_pp_dpp_clock,
0158     amd_pp_f_clock = amd_pp_dcef_clock,
0159 };
0160
0161 #define MAX_NUM_CLOCKS 16
0162
0163 struct amd_pp_clocks {
0164     uint32_t count;
0165     uint32_t clock[MAX_NUM_CLOCKS];
0166     uint32_t latency[MAX_NUM_CLOCKS];
0167 };
0168
0169 struct pp_clock_with_latency {
0170     uint32_t clocks_in_khz;
0171     uint32_t latency_in_us;
0172 };
0173
0174 struct pp_clock_levels_with_latency {
0175     uint32_t num_levels;
0176     struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS];
0177 };
0178
0179 struct pp_clock_with_voltage {
0180     uint32_t clocks_in_khz;
0181     uint32_t voltage_in_mv;
0182 };
0183
0184 struct pp_clock_levels_with_voltage {
0185     uint32_t num_levels;
0186     struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
0187 };
0188
0189 struct pp_display_clock_request {
0190     enum amd_pp_clock_type clock_type;
0191     uint32_t clock_freq_in_khz;
0192 };
0193
0194 #endif /* _DM_PP_INTERFACE_ */