amd/include/discovery.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _DISCOVERY_H_
0025 #define _DISCOVERY_H_
0026
0027 #define PSP_HEADER_SIZE                 256
0028 #define BINARY_SIGNATURE                0x28211407
0029 #define DISCOVERY_TABLE_SIGNATURE       0x53445049
0030 #define GC_TABLE_ID                     0x4347
0031 #define HARVEST_TABLE_SIGNATURE         0x56524148
0032 #define VCN_INFO_TABLE_ID               0x004E4356
0033 #define MALL_INFO_TABLE_ID              0x4D414C4C
0034
0035 typedef enum
0036 {
0037     IP_DISCOVERY = 0,
0038     GC,
0039     HARVEST_INFO,
0040     VCN_INFO,
0041     MALL_INFO,
0042     RESERVED_1,
0043     TOTAL_TABLES = 6
0044 } table;
0045
0046 #pragma pack(1)
0047
0048 typedef struct table_info
0049 {
0050     uint16_t offset;   /* Byte offset */
0051     uint16_t checksum; /* Byte sum of the table */
0052     uint16_t size;     /* Table size */
0053     uint16_t padding;
0054 } table_info;
0055
0056 typedef struct binary_header
0057 {
0058     /* psp structure should go at the top of this structure */
0059     uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
0060     uint16_t version_major;
0061     uint16_t version_minor;
0062     uint16_t binary_checksum;  /* Byte sum of the binary after this field */
0063     uint16_t binary_size;      /* Binary Size*/
0064     table_info table_list[TOTAL_TABLES];
0065 } binary_header;
0066
0067 typedef struct die_info
0068 {
0069     uint16_t die_id;
0070     uint16_t die_offset; /* Points to the corresponding die_header structure */
0071 } die_info;
0072
0073
0074 typedef struct ip_discovery_header
0075 {
0076     uint32_t signature;    /* Table Signature */
0077     uint16_t version;      /* Table Version */
0078     uint16_t size;         /* Table Size */
0079     uint32_t id;           /* Table ID */
0080     uint16_t num_dies;     /* Number of Dies */
0081     die_info die_info[16]; /* list die information for up to 16 dies */
0082     uint16_t padding[1];   /* padding */
0083 } ip_discovery_header;
0084
0085 typedef struct ip
0086 {
0087     uint16_t hw_id;           /* Hardware ID */
0088     uint8_t number_instance;  /* instance of the IP */
0089     uint8_t num_base_address; /* Number of Base Addresses */
0090     uint8_t major;            /* HCID Major */
0091     uint8_t minor;            /* HCID Minor */
0092     uint8_t revision;         /* HCID Revision */
0093 #if defined(__BIG_ENDIAN)
0094     uint8_t reserved : 4;     /* Placeholder field */
0095     uint8_t harvest : 4;      /* Harvest */
0096 #else
0097     uint8_t harvest : 4;      /* Harvest */
0098     uint8_t reserved : 4;     /* Placeholder field */
0099 #endif
0100     uint32_t base_address[]; /* variable number of Addresses */
0101 } ip;
0102
0103 typedef struct ip_v3
0104 {
0105     uint16_t hw_id;                         /* Hardware ID */
0106     uint8_t instance_number;                /* Instance number for the IP */
0107     uint8_t num_base_address;               /* Number of base addresses*/
0108     uint8_t major;                          /* Hardware ID.major version */
0109     uint8_t minor;                          /* Hardware ID.minor version */
0110     uint8_t revision;                       /* Hardware ID.revision version */
0111 #if defined(__BIG_ENDIAN)
0112     uint8_t variant : 4;                    /* HW variant */
0113     uint8_t sub_revision : 4;               /* HCID Sub-Revision */
0114 #else
0115     uint8_t sub_revision : 4;               /* HCID Sub-Revision */
0116     uint8_t variant : 4;                    /* HW variant */
0117 #endif
0118     uint32_t base_address[1];               /* Base Address list. Corresponds to the num_base_address field*/
0119 } ip_v3;
0120
0121 typedef struct die_header
0122 {
0123     uint16_t die_id;
0124     uint16_t num_ips;
0125 } die_header;
0126
0127 typedef struct ip_structure
0128 {
0129     ip_discovery_header* header;
0130     struct die
0131     {
0132         die_header *die_header;
0133         union
0134         {
0135             ip *ip_list;
0136             ip_v3 *ip_v3_list;
0137         };                                  /* IP list. Variable size*/
0138     } die;
0139 } ip_structure;
0140
0141 struct gpu_info_header {
0142     uint32_t table_id;      /* table ID */
0143     uint16_t version_major; /* table version */
0144     uint16_t version_minor; /* table version */
0145     uint32_t size;          /* size of the entire header+data in bytes */
0146 };
0147
0148 struct gc_info_v1_0 {
0149     struct gpu_info_header header;
0150
0151     uint32_t gc_num_se;
0152     uint32_t gc_num_wgp0_per_sa;
0153     uint32_t gc_num_wgp1_per_sa;
0154     uint32_t gc_num_rb_per_se;
0155     uint32_t gc_num_gl2c;
0156     uint32_t gc_num_gprs;
0157     uint32_t gc_num_max_gs_thds;
0158     uint32_t gc_gs_table_depth;
0159     uint32_t gc_gsprim_buff_depth;
0160     uint32_t gc_parameter_cache_depth;
0161     uint32_t gc_double_offchip_lds_buffer;
0162     uint32_t gc_wave_size;
0163     uint32_t gc_max_waves_per_simd;
0164     uint32_t gc_max_scratch_slots_per_cu;
0165     uint32_t gc_lds_size;
0166     uint32_t gc_num_sc_per_se;
0167     uint32_t gc_num_sa_per_se;
0168     uint32_t gc_num_packer_per_sc;
0169     uint32_t gc_num_gl2a;
0170 };
0171
0172 struct gc_info_v1_1 {
0173     struct gpu_info_header header;
0174
0175     uint32_t gc_num_se;
0176     uint32_t gc_num_wgp0_per_sa;
0177     uint32_t gc_num_wgp1_per_sa;
0178     uint32_t gc_num_rb_per_se;
0179     uint32_t gc_num_gl2c;
0180     uint32_t gc_num_gprs;
0181     uint32_t gc_num_max_gs_thds;
0182     uint32_t gc_gs_table_depth;
0183     uint32_t gc_gsprim_buff_depth;
0184     uint32_t gc_parameter_cache_depth;
0185     uint32_t gc_double_offchip_lds_buffer;
0186     uint32_t gc_wave_size;
0187     uint32_t gc_max_waves_per_simd;
0188     uint32_t gc_max_scratch_slots_per_cu;
0189     uint32_t gc_lds_size;
0190     uint32_t gc_num_sc_per_se;
0191     uint32_t gc_num_sa_per_se;
0192     uint32_t gc_num_packer_per_sc;
0193     uint32_t gc_num_gl2a;
0194     uint32_t gc_num_tcp_per_sa;
0195     uint32_t gc_num_sdp_interface;
0196     uint32_t gc_num_tcps;
0197 };
0198
0199 struct gc_info_v1_2 {
0200     struct gpu_info_header header;
0201     uint32_t gc_num_se;
0202     uint32_t gc_num_wgp0_per_sa;
0203     uint32_t gc_num_wgp1_per_sa;
0204     uint32_t gc_num_rb_per_se;
0205     uint32_t gc_num_gl2c;
0206     uint32_t gc_num_gprs;
0207     uint32_t gc_num_max_gs_thds;
0208     uint32_t gc_gs_table_depth;
0209     uint32_t gc_gsprim_buff_depth;
0210     uint32_t gc_parameter_cache_depth;
0211     uint32_t gc_double_offchip_lds_buffer;
0212     uint32_t gc_wave_size;
0213     uint32_t gc_max_waves_per_simd;
0214     uint32_t gc_max_scratch_slots_per_cu;
0215     uint32_t gc_lds_size;
0216     uint32_t gc_num_sc_per_se;
0217     uint32_t gc_num_sa_per_se;
0218     uint32_t gc_num_packer_per_sc;
0219     uint32_t gc_num_gl2a;
0220     uint32_t gc_num_tcp_per_sa;
0221     uint32_t gc_num_sdp_interface;
0222     uint32_t gc_num_tcps;
0223     uint32_t gc_num_tcp_per_wpg;
0224     uint32_t gc_tcp_l1_size;
0225     uint32_t gc_num_sqc_per_wgp;
0226     uint32_t gc_l1_instruction_cache_size_per_sqc;
0227     uint32_t gc_l1_data_cache_size_per_sqc;
0228     uint32_t gc_gl1c_per_sa;
0229     uint32_t gc_gl1c_size_per_instance;
0230     uint32_t gc_gl2c_per_gpu;
0231 };
0232
0233 struct gc_info_v2_0 {
0234     struct gpu_info_header header;
0235
0236     uint32_t gc_num_se;
0237     uint32_t gc_num_cu_per_sh;
0238     uint32_t gc_num_sh_per_se;
0239     uint32_t gc_num_rb_per_se;
0240     uint32_t gc_num_tccs;
0241     uint32_t gc_num_gprs;
0242     uint32_t gc_num_max_gs_thds;
0243     uint32_t gc_gs_table_depth;
0244     uint32_t gc_gsprim_buff_depth;
0245     uint32_t gc_parameter_cache_depth;
0246     uint32_t gc_double_offchip_lds_buffer;
0247     uint32_t gc_wave_size;
0248     uint32_t gc_max_waves_per_simd;
0249     uint32_t gc_max_scratch_slots_per_cu;
0250     uint32_t gc_lds_size;
0251     uint32_t gc_num_sc_per_se;
0252     uint32_t gc_num_packer_per_sc;
0253 };
0254
0255 typedef struct harvest_info_header {
0256     uint32_t signature; /* Table Signature */
0257     uint32_t version;   /* Table Version */
0258 } harvest_info_header;
0259
0260 typedef struct harvest_info {
0261     uint16_t hw_id;          /* Hardware ID */
0262     uint8_t number_instance; /* Instance of the IP */
0263     uint8_t reserved;        /* Reserved for alignment */
0264 } harvest_info;
0265
0266 typedef struct harvest_table {
0267     harvest_info_header header;
0268     harvest_info list[32];
0269 } harvest_table;
0270
0271 struct mall_info_header {
0272     uint32_t table_id; /* table ID */
0273     uint16_t version_major; /* table version */
0274     uint16_t version_minor; /* table version */
0275     uint32_t size_bytes; /* size of the entire header+data in bytes */
0276 };
0277
0278 struct mall_info_v1_0 {
0279     struct mall_info_header header;
0280     uint32_t mall_size_per_m;
0281     uint32_t m_s_present;
0282     uint32_t m_half_use;
0283     uint32_t m_mall_config;
0284     uint32_t reserved[5];
0285 };
0286
0287 #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
0288
0289 struct vcn_info_header {
0290     uint32_t table_id; /* table ID */
0291     uint16_t version_major; /* table version */
0292     uint16_t version_minor; /* table version */
0293     uint32_t size_bytes; /* size of the entire header+data in bytes */
0294 };
0295
0296 struct vcn_instance_info_v1_0
0297 {
0298     uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
0299     union _fuse_data {
0300         struct {
0301             uint32_t av1_disabled : 1;
0302             uint32_t vp9_disabled : 1;
0303             uint32_t hevc_disabled : 1;
0304             uint32_t h264_disabled : 1;
0305             uint32_t reserved : 28;
0306         } bits;
0307         uint32_t all_bits;
0308     } fuse_data;
0309     uint32_t reserved[2];
0310 };
0311
0312 struct vcn_info_v1_0 {
0313     struct vcn_info_header header;
0314     uint32_t num_of_instances; /* number of entries used in instance_info below*/
0315     struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
0316     uint32_t reserved[4];
0317 };
0318
0319 #pragma pack()
0320
0321 #endif