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0001 /*
0002  * Copyright (C) 2020  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _dimgrey_cavefish_ip_offset_HEADER
0022 #define _dimgrey_cavefish_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                        7
0025 #define MAX_SEGMENT                                         6
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 };
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0, 0 } } } };
0046 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
0047                                         { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
0048                                         { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
0049                                         { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
0050                                         { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
0051                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
0052                                         { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
0053 static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
0054                                         { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } } } };
0060 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } } } };
0067 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
0068                                         { { 0, 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0, 0 } } } };
0074 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
0075                                         { { 0, 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0, 0 } } } };
0088 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } } } };
0095 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } } } };
0102 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } } } };
0109 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
0110                                         { { 0, 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0, 0 } } } };
0116 static const struct IP_BASE MP1_BASE = { { { { 0x00016200, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400, 0 } },
0117                                         { { 0, 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
0124                                         { { 0, 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0, 0 } } } };
0130 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } } } };
0137 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0, 0 } } } };
0144 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0, 0 } } } };
0151 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
0152                                         { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
0153                                         { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
0154                                         { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0, 0 } } } };
0158 static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
0159                                         { { 0, 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0, 0 } } } };
0165 
0166 
0167 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0168 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0169 #define ATHUB_BASE__INST0_SEG2                     0
0170 #define ATHUB_BASE__INST0_SEG3                     0
0171 #define ATHUB_BASE__INST0_SEG4                     0
0172 #define ATHUB_BASE__INST0_SEG5                     0
0173 
0174 #define ATHUB_BASE__INST1_SEG0                     0
0175 #define ATHUB_BASE__INST1_SEG1                     0
0176 #define ATHUB_BASE__INST1_SEG2                     0
0177 #define ATHUB_BASE__INST1_SEG3                     0
0178 #define ATHUB_BASE__INST1_SEG4                     0
0179 #define ATHUB_BASE__INST1_SEG5                     0
0180 
0181 #define ATHUB_BASE__INST2_SEG0                     0
0182 #define ATHUB_BASE__INST2_SEG1                     0
0183 #define ATHUB_BASE__INST2_SEG2                     0
0184 #define ATHUB_BASE__INST2_SEG3                     0
0185 #define ATHUB_BASE__INST2_SEG4                     0
0186 #define ATHUB_BASE__INST2_SEG5                     0
0187 
0188 #define ATHUB_BASE__INST3_SEG0                     0
0189 #define ATHUB_BASE__INST3_SEG1                     0
0190 #define ATHUB_BASE__INST3_SEG2                     0
0191 #define ATHUB_BASE__INST3_SEG3                     0
0192 #define ATHUB_BASE__INST3_SEG4                     0
0193 #define ATHUB_BASE__INST3_SEG5                     0
0194 
0195 #define ATHUB_BASE__INST4_SEG0                     0
0196 #define ATHUB_BASE__INST4_SEG1                     0
0197 #define ATHUB_BASE__INST4_SEG2                     0
0198 #define ATHUB_BASE__INST4_SEG3                     0
0199 #define ATHUB_BASE__INST4_SEG4                     0
0200 #define ATHUB_BASE__INST4_SEG5                     0
0201 
0202 #define ATHUB_BASE__INST5_SEG0                     0
0203 #define ATHUB_BASE__INST5_SEG1                     0
0204 #define ATHUB_BASE__INST5_SEG2                     0
0205 #define ATHUB_BASE__INST5_SEG3                     0
0206 #define ATHUB_BASE__INST5_SEG4                     0
0207 #define ATHUB_BASE__INST5_SEG5                     0
0208 
0209 #define ATHUB_BASE__INST6_SEG0                     0
0210 #define ATHUB_BASE__INST6_SEG1                     0
0211 #define ATHUB_BASE__INST6_SEG2                     0
0212 #define ATHUB_BASE__INST6_SEG3                     0
0213 #define ATHUB_BASE__INST6_SEG4                     0
0214 #define ATHUB_BASE__INST6_SEG5                     0
0215 
0216 #define CLK_BASE__INST0_SEG0                       0x00016C00
0217 #define CLK_BASE__INST0_SEG1                       0x02401800
0218 #define CLK_BASE__INST0_SEG2                       0
0219 #define CLK_BASE__INST0_SEG3                       0
0220 #define CLK_BASE__INST0_SEG4                       0
0221 #define CLK_BASE__INST0_SEG5                       0
0222 
0223 #define CLK_BASE__INST1_SEG0                       0x00016E00
0224 #define CLK_BASE__INST1_SEG1                       0x02401C00
0225 #define CLK_BASE__INST1_SEG2                       0
0226 #define CLK_BASE__INST1_SEG3                       0
0227 #define CLK_BASE__INST1_SEG4                       0
0228 #define CLK_BASE__INST1_SEG5                       0
0229 
0230 #define CLK_BASE__INST2_SEG0                       0x00017000
0231 #define CLK_BASE__INST2_SEG1                       0x02402000
0232 #define CLK_BASE__INST2_SEG2                       0
0233 #define CLK_BASE__INST2_SEG3                       0
0234 #define CLK_BASE__INST2_SEG4                       0
0235 #define CLK_BASE__INST2_SEG5                       0
0236 
0237 #define CLK_BASE__INST3_SEG0                       0x00017200
0238 #define CLK_BASE__INST3_SEG1                       0x02402400
0239 #define CLK_BASE__INST3_SEG2                       0
0240 #define CLK_BASE__INST3_SEG3                       0
0241 #define CLK_BASE__INST3_SEG4                       0
0242 #define CLK_BASE__INST3_SEG5                       0
0243 
0244 #define CLK_BASE__INST4_SEG0                       0x0001B000
0245 #define CLK_BASE__INST4_SEG1                       0x0242D800
0246 #define CLK_BASE__INST4_SEG2                       0
0247 #define CLK_BASE__INST4_SEG3                       0
0248 #define CLK_BASE__INST4_SEG4                       0
0249 #define CLK_BASE__INST4_SEG5                       0
0250 
0251 #define CLK_BASE__INST5_SEG0                       0x0001B200
0252 #define CLK_BASE__INST5_SEG1                       0x0242DC00
0253 #define CLK_BASE__INST5_SEG2                       0
0254 #define CLK_BASE__INST5_SEG3                       0
0255 #define CLK_BASE__INST5_SEG4                       0
0256 #define CLK_BASE__INST5_SEG5                       0
0257 
0258 #define CLK_BASE__INST6_SEG0                       0x0001B400
0259 #define CLK_BASE__INST6_SEG1                       0x0242E000
0260 #define CLK_BASE__INST6_SEG2                       0
0261 #define CLK_BASE__INST6_SEG3                       0
0262 #define CLK_BASE__INST6_SEG4                       0
0263 #define CLK_BASE__INST6_SEG5                       0
0264 
0265 #define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
0266 #define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
0267 #define DBGU_IO0_BASE__INST0_SEG2                  0
0268 #define DBGU_IO0_BASE__INST0_SEG3                  0
0269 #define DBGU_IO0_BASE__INST0_SEG4                  0
0270 #define DBGU_IO0_BASE__INST0_SEG5                  0
0271 
0272 #define DBGU_IO0_BASE__INST1_SEG0                  0x00000260
0273 #define DBGU_IO0_BASE__INST1_SEG1                  0x02413C00
0274 #define DBGU_IO0_BASE__INST1_SEG2                  0
0275 #define DBGU_IO0_BASE__INST1_SEG3                  0
0276 #define DBGU_IO0_BASE__INST1_SEG4                  0
0277 #define DBGU_IO0_BASE__INST1_SEG5                  0
0278 
0279 #define DBGU_IO0_BASE__INST2_SEG0                  0
0280 #define DBGU_IO0_BASE__INST2_SEG1                  0
0281 #define DBGU_IO0_BASE__INST2_SEG2                  0
0282 #define DBGU_IO0_BASE__INST2_SEG3                  0
0283 #define DBGU_IO0_BASE__INST2_SEG4                  0
0284 #define DBGU_IO0_BASE__INST2_SEG5                  0
0285 
0286 #define DBGU_IO0_BASE__INST3_SEG0                  0
0287 #define DBGU_IO0_BASE__INST3_SEG1                  0
0288 #define DBGU_IO0_BASE__INST3_SEG2                  0
0289 #define DBGU_IO0_BASE__INST3_SEG3                  0
0290 #define DBGU_IO0_BASE__INST3_SEG4                  0
0291 #define DBGU_IO0_BASE__INST3_SEG5                  0
0292 
0293 #define DBGU_IO0_BASE__INST4_SEG0                  0
0294 #define DBGU_IO0_BASE__INST4_SEG1                  0
0295 #define DBGU_IO0_BASE__INST4_SEG2                  0
0296 #define DBGU_IO0_BASE__INST4_SEG3                  0
0297 #define DBGU_IO0_BASE__INST4_SEG4                  0
0298 #define DBGU_IO0_BASE__INST4_SEG5                  0
0299 
0300 #define DBGU_IO0_BASE__INST5_SEG0                  0
0301 #define DBGU_IO0_BASE__INST5_SEG1                  0
0302 #define DBGU_IO0_BASE__INST5_SEG2                  0
0303 #define DBGU_IO0_BASE__INST5_SEG3                  0
0304 #define DBGU_IO0_BASE__INST5_SEG4                  0
0305 #define DBGU_IO0_BASE__INST5_SEG5                  0
0306 
0307 #define DBGU_IO0_BASE__INST6_SEG0                  0
0308 #define DBGU_IO0_BASE__INST6_SEG1                  0
0309 #define DBGU_IO0_BASE__INST6_SEG2                  0
0310 #define DBGU_IO0_BASE__INST6_SEG3                  0
0311 #define DBGU_IO0_BASE__INST6_SEG4                  0
0312 #define DBGU_IO0_BASE__INST6_SEG5                  0
0313 
0314 #define DF_BASE__INST0_SEG0                        0x00007000
0315 #define DF_BASE__INST0_SEG1                        0x0240B800
0316 #define DF_BASE__INST0_SEG2                        0
0317 #define DF_BASE__INST0_SEG3                        0
0318 #define DF_BASE__INST0_SEG4                        0
0319 #define DF_BASE__INST0_SEG5                        0
0320 
0321 #define DF_BASE__INST1_SEG0                        0
0322 #define DF_BASE__INST1_SEG1                        0
0323 #define DF_BASE__INST1_SEG2                        0
0324 #define DF_BASE__INST1_SEG3                        0
0325 #define DF_BASE__INST1_SEG4                        0
0326 #define DF_BASE__INST1_SEG5                        0
0327 
0328 #define DF_BASE__INST2_SEG0                        0
0329 #define DF_BASE__INST2_SEG1                        0
0330 #define DF_BASE__INST2_SEG2                        0
0331 #define DF_BASE__INST2_SEG3                        0
0332 #define DF_BASE__INST2_SEG4                        0
0333 #define DF_BASE__INST2_SEG5                        0
0334 
0335 #define DF_BASE__INST3_SEG0                        0
0336 #define DF_BASE__INST3_SEG1                        0
0337 #define DF_BASE__INST3_SEG2                        0
0338 #define DF_BASE__INST3_SEG3                        0
0339 #define DF_BASE__INST3_SEG4                        0
0340 #define DF_BASE__INST3_SEG5                        0
0341 
0342 #define DF_BASE__INST4_SEG0                        0
0343 #define DF_BASE__INST4_SEG1                        0
0344 #define DF_BASE__INST4_SEG2                        0
0345 #define DF_BASE__INST4_SEG3                        0
0346 #define DF_BASE__INST4_SEG4                        0
0347 #define DF_BASE__INST4_SEG5                        0
0348 
0349 #define DF_BASE__INST5_SEG0                        0
0350 #define DF_BASE__INST5_SEG1                        0
0351 #define DF_BASE__INST5_SEG2                        0
0352 #define DF_BASE__INST5_SEG3                        0
0353 #define DF_BASE__INST5_SEG4                        0
0354 #define DF_BASE__INST5_SEG5                        0
0355 
0356 #define DF_BASE__INST6_SEG0                        0
0357 #define DF_BASE__INST6_SEG1                        0
0358 #define DF_BASE__INST6_SEG2                        0
0359 #define DF_BASE__INST6_SEG3                        0
0360 #define DF_BASE__INST6_SEG4                        0
0361 #define DF_BASE__INST6_SEG5                        0
0362 
0363 #define DCN_BASE__INST0_SEG0                       0x00000012
0364 #define DCN_BASE__INST0_SEG1                       0x000000C0
0365 #define DCN_BASE__INST0_SEG2                       0x000034C0
0366 #define DCN_BASE__INST0_SEG3                       0x00009000
0367 #define DCN_BASE__INST0_SEG4                       0x02403C00
0368 #define DCN_BASE__INST0_SEG5                       0
0369 
0370 #define DCN_BASE__INST1_SEG0                       0
0371 #define DCN_BASE__INST1_SEG1                       0
0372 #define DCN_BASE__INST1_SEG2                       0
0373 #define DCN_BASE__INST1_SEG3                       0
0374 #define DCN_BASE__INST1_SEG4                       0
0375 #define DCN_BASE__INST1_SEG5                       0
0376 
0377 #define DCN_BASE__INST2_SEG0                       0
0378 #define DCN_BASE__INST2_SEG1                       0
0379 #define DCN_BASE__INST2_SEG2                       0
0380 #define DCN_BASE__INST2_SEG3                       0
0381 #define DCN_BASE__INST2_SEG4                       0
0382 #define DCN_BASE__INST2_SEG5                       0
0383 
0384 #define DCN_BASE__INST3_SEG0                       0
0385 #define DCN_BASE__INST3_SEG1                       0
0386 #define DCN_BASE__INST3_SEG2                       0
0387 #define DCN_BASE__INST3_SEG3                       0
0388 #define DCN_BASE__INST3_SEG4                       0
0389 #define DCN_BASE__INST3_SEG5                       0
0390 
0391 #define DCN_BASE__INST4_SEG0                       0
0392 #define DCN_BASE__INST4_SEG1                       0
0393 #define DCN_BASE__INST4_SEG2                       0
0394 #define DCN_BASE__INST4_SEG3                       0
0395 #define DCN_BASE__INST4_SEG4                       0
0396 #define DCN_BASE__INST4_SEG5                       0
0397 
0398 #define DCN_BASE__INST5_SEG0                       0
0399 #define DCN_BASE__INST5_SEG1                       0
0400 #define DCN_BASE__INST5_SEG2                       0
0401 #define DCN_BASE__INST5_SEG3                       0
0402 #define DCN_BASE__INST5_SEG4                       0
0403 #define DCN_BASE__INST5_SEG5                       0
0404 
0405 #define DCN_BASE__INST6_SEG0                       0
0406 #define DCN_BASE__INST6_SEG1                       0
0407 #define DCN_BASE__INST6_SEG2                       0
0408 #define DCN_BASE__INST6_SEG3                       0
0409 #define DCN_BASE__INST6_SEG4                       0
0410 #define DCN_BASE__INST6_SEG5                       0
0411 
0412 #define DPCS_BASE__INST0_SEG0                      0x00000012
0413 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0414 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0415 #define DPCS_BASE__INST0_SEG3                      0x00009000
0416 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0417 #define DPCS_BASE__INST0_SEG5                      0
0418 
0419 #define DPCS_BASE__INST1_SEG0                      0
0420 #define DPCS_BASE__INST1_SEG1                      0
0421 #define DPCS_BASE__INST1_SEG2                      0
0422 #define DPCS_BASE__INST1_SEG3                      0
0423 #define DPCS_BASE__INST1_SEG4                      0
0424 #define DPCS_BASE__INST1_SEG5                      0
0425 
0426 #define DPCS_BASE__INST2_SEG0                      0
0427 #define DPCS_BASE__INST2_SEG1                      0
0428 #define DPCS_BASE__INST2_SEG2                      0
0429 #define DPCS_BASE__INST2_SEG3                      0
0430 #define DPCS_BASE__INST2_SEG4                      0
0431 #define DPCS_BASE__INST2_SEG5                      0
0432 
0433 #define DPCS_BASE__INST3_SEG0                      0
0434 #define DPCS_BASE__INST3_SEG1                      0
0435 #define DPCS_BASE__INST3_SEG2                      0
0436 #define DPCS_BASE__INST3_SEG3                      0
0437 #define DPCS_BASE__INST3_SEG4                      0
0438 #define DPCS_BASE__INST3_SEG5                      0
0439 
0440 #define DPCS_BASE__INST4_SEG0                      0
0441 #define DPCS_BASE__INST4_SEG1                      0
0442 #define DPCS_BASE__INST4_SEG2                      0
0443 #define DPCS_BASE__INST4_SEG3                      0
0444 #define DPCS_BASE__INST4_SEG4                      0
0445 #define DPCS_BASE__INST4_SEG5                      0
0446 
0447 #define DPCS_BASE__INST5_SEG0                      0
0448 #define DPCS_BASE__INST5_SEG1                      0
0449 #define DPCS_BASE__INST5_SEG2                      0
0450 #define DPCS_BASE__INST5_SEG3                      0
0451 #define DPCS_BASE__INST5_SEG4                      0
0452 #define DPCS_BASE__INST5_SEG5                      0
0453 
0454 #define DPCS_BASE__INST6_SEG0                      0
0455 #define DPCS_BASE__INST6_SEG1                      0
0456 #define DPCS_BASE__INST6_SEG2                      0
0457 #define DPCS_BASE__INST6_SEG3                      0
0458 #define DPCS_BASE__INST6_SEG4                      0
0459 #define DPCS_BASE__INST6_SEG5                      0
0460 
0461 #define FUSE_BASE__INST0_SEG0                      0x00017400
0462 #define FUSE_BASE__INST0_SEG1                      0x02401400
0463 #define FUSE_BASE__INST0_SEG2                      0
0464 #define FUSE_BASE__INST0_SEG3                      0
0465 #define FUSE_BASE__INST0_SEG4                      0
0466 #define FUSE_BASE__INST0_SEG5                      0
0467 
0468 #define FUSE_BASE__INST1_SEG0                      0
0469 #define FUSE_BASE__INST1_SEG1                      0
0470 #define FUSE_BASE__INST1_SEG2                      0
0471 #define FUSE_BASE__INST1_SEG3                      0
0472 #define FUSE_BASE__INST1_SEG4                      0
0473 #define FUSE_BASE__INST1_SEG5                      0
0474 
0475 #define FUSE_BASE__INST2_SEG0                      0
0476 #define FUSE_BASE__INST2_SEG1                      0
0477 #define FUSE_BASE__INST2_SEG2                      0
0478 #define FUSE_BASE__INST2_SEG3                      0
0479 #define FUSE_BASE__INST2_SEG4                      0
0480 #define FUSE_BASE__INST2_SEG5                      0
0481 
0482 #define FUSE_BASE__INST3_SEG0                      0
0483 #define FUSE_BASE__INST3_SEG1                      0
0484 #define FUSE_BASE__INST3_SEG2                      0
0485 #define FUSE_BASE__INST3_SEG3                      0
0486 #define FUSE_BASE__INST3_SEG4                      0
0487 #define FUSE_BASE__INST3_SEG5                      0
0488 
0489 #define FUSE_BASE__INST4_SEG0                      0
0490 #define FUSE_BASE__INST4_SEG1                      0
0491 #define FUSE_BASE__INST4_SEG2                      0
0492 #define FUSE_BASE__INST4_SEG3                      0
0493 #define FUSE_BASE__INST4_SEG4                      0
0494 #define FUSE_BASE__INST4_SEG5                      0
0495 
0496 #define FUSE_BASE__INST5_SEG0                      0
0497 #define FUSE_BASE__INST5_SEG1                      0
0498 #define FUSE_BASE__INST5_SEG2                      0
0499 #define FUSE_BASE__INST5_SEG3                      0
0500 #define FUSE_BASE__INST5_SEG4                      0
0501 #define FUSE_BASE__INST5_SEG5                      0
0502 
0503 #define FUSE_BASE__INST6_SEG0                      0
0504 #define FUSE_BASE__INST6_SEG1                      0
0505 #define FUSE_BASE__INST6_SEG2                      0
0506 #define FUSE_BASE__INST6_SEG3                      0
0507 #define FUSE_BASE__INST6_SEG4                      0
0508 #define FUSE_BASE__INST6_SEG5                      0
0509 
0510 #define GC_BASE__INST0_SEG0                        0x00001260
0511 #define GC_BASE__INST0_SEG1                        0x0000A000
0512 #define GC_BASE__INST0_SEG2                        0x0001C000
0513 #define GC_BASE__INST0_SEG3                        0x02402C00
0514 #define GC_BASE__INST0_SEG4                        0
0515 #define GC_BASE__INST0_SEG5                        0
0516 
0517 #define GC_BASE__INST1_SEG0                        0
0518 #define GC_BASE__INST1_SEG1                        0
0519 #define GC_BASE__INST1_SEG2                        0
0520 #define GC_BASE__INST1_SEG3                        0
0521 #define GC_BASE__INST1_SEG4                        0
0522 #define GC_BASE__INST1_SEG5                        0
0523 
0524 #define GC_BASE__INST2_SEG0                        0
0525 #define GC_BASE__INST2_SEG1                        0
0526 #define GC_BASE__INST2_SEG2                        0
0527 #define GC_BASE__INST2_SEG3                        0
0528 #define GC_BASE__INST2_SEG4                        0
0529 #define GC_BASE__INST2_SEG5                        0
0530 
0531 #define GC_BASE__INST3_SEG0                        0
0532 #define GC_BASE__INST3_SEG1                        0
0533 #define GC_BASE__INST3_SEG2                        0
0534 #define GC_BASE__INST3_SEG3                        0
0535 #define GC_BASE__INST3_SEG4                        0
0536 #define GC_BASE__INST3_SEG5                        0
0537 
0538 #define GC_BASE__INST4_SEG0                        0
0539 #define GC_BASE__INST4_SEG1                        0
0540 #define GC_BASE__INST4_SEG2                        0
0541 #define GC_BASE__INST4_SEG3                        0
0542 #define GC_BASE__INST4_SEG4                        0
0543 #define GC_BASE__INST4_SEG5                        0
0544 
0545 #define GC_BASE__INST5_SEG0                        0
0546 #define GC_BASE__INST5_SEG1                        0
0547 #define GC_BASE__INST5_SEG2                        0
0548 #define GC_BASE__INST5_SEG3                        0
0549 #define GC_BASE__INST5_SEG4                        0
0550 #define GC_BASE__INST5_SEG5                        0
0551 
0552 #define GC_BASE__INST6_SEG0                        0
0553 #define GC_BASE__INST6_SEG1                        0
0554 #define GC_BASE__INST6_SEG2                        0
0555 #define GC_BASE__INST6_SEG3                        0
0556 #define GC_BASE__INST6_SEG4                        0
0557 #define GC_BASE__INST6_SEG5                        0
0558 
0559 #define HDP_BASE__INST0_SEG0                       0x00000F20
0560 #define HDP_BASE__INST0_SEG1                       0x0240A400
0561 #define HDP_BASE__INST0_SEG2                       0
0562 #define HDP_BASE__INST0_SEG3                       0
0563 #define HDP_BASE__INST0_SEG4                       0
0564 #define HDP_BASE__INST0_SEG5                       0
0565 
0566 #define HDP_BASE__INST1_SEG0                       0
0567 #define HDP_BASE__INST1_SEG1                       0
0568 #define HDP_BASE__INST1_SEG2                       0
0569 #define HDP_BASE__INST1_SEG3                       0
0570 #define HDP_BASE__INST1_SEG4                       0
0571 #define HDP_BASE__INST1_SEG5                       0
0572 
0573 #define HDP_BASE__INST2_SEG0                       0
0574 #define HDP_BASE__INST2_SEG1                       0
0575 #define HDP_BASE__INST2_SEG2                       0
0576 #define HDP_BASE__INST2_SEG3                       0
0577 #define HDP_BASE__INST2_SEG4                       0
0578 #define HDP_BASE__INST2_SEG5                       0
0579 
0580 #define HDP_BASE__INST3_SEG0                       0
0581 #define HDP_BASE__INST3_SEG1                       0
0582 #define HDP_BASE__INST3_SEG2                       0
0583 #define HDP_BASE__INST3_SEG3                       0
0584 #define HDP_BASE__INST3_SEG4                       0
0585 #define HDP_BASE__INST3_SEG5                       0
0586 
0587 #define HDP_BASE__INST4_SEG0                       0
0588 #define HDP_BASE__INST4_SEG1                       0
0589 #define HDP_BASE__INST4_SEG2                       0
0590 #define HDP_BASE__INST4_SEG3                       0
0591 #define HDP_BASE__INST4_SEG4                       0
0592 #define HDP_BASE__INST4_SEG5                       0
0593 
0594 #define HDP_BASE__INST5_SEG0                       0
0595 #define HDP_BASE__INST5_SEG1                       0
0596 #define HDP_BASE__INST5_SEG2                       0
0597 #define HDP_BASE__INST5_SEG3                       0
0598 #define HDP_BASE__INST5_SEG4                       0
0599 #define HDP_BASE__INST5_SEG5                       0
0600 
0601 #define HDP_BASE__INST6_SEG0                       0
0602 #define HDP_BASE__INST6_SEG1                       0
0603 #define HDP_BASE__INST6_SEG2                       0
0604 #define HDP_BASE__INST6_SEG3                       0
0605 #define HDP_BASE__INST6_SEG4                       0
0606 #define HDP_BASE__INST6_SEG5                       0
0607 
0608 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0609 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0610 #define MMHUB_BASE__INST0_SEG2                     0
0611 #define MMHUB_BASE__INST0_SEG3                     0
0612 #define MMHUB_BASE__INST0_SEG4                     0
0613 #define MMHUB_BASE__INST0_SEG5                     0
0614 
0615 #define MMHUB_BASE__INST1_SEG0                     0
0616 #define MMHUB_BASE__INST1_SEG1                     0
0617 #define MMHUB_BASE__INST1_SEG2                     0
0618 #define MMHUB_BASE__INST1_SEG3                     0
0619 #define MMHUB_BASE__INST1_SEG4                     0
0620 #define MMHUB_BASE__INST1_SEG5                     0
0621 
0622 #define MMHUB_BASE__INST2_SEG0                     0
0623 #define MMHUB_BASE__INST2_SEG1                     0
0624 #define MMHUB_BASE__INST2_SEG2                     0
0625 #define MMHUB_BASE__INST2_SEG3                     0
0626 #define MMHUB_BASE__INST2_SEG4                     0
0627 #define MMHUB_BASE__INST2_SEG5                     0
0628 
0629 #define MMHUB_BASE__INST3_SEG0                     0
0630 #define MMHUB_BASE__INST3_SEG1                     0
0631 #define MMHUB_BASE__INST3_SEG2                     0
0632 #define MMHUB_BASE__INST3_SEG3                     0
0633 #define MMHUB_BASE__INST3_SEG4                     0
0634 #define MMHUB_BASE__INST3_SEG5                     0
0635 
0636 #define MMHUB_BASE__INST4_SEG0                     0
0637 #define MMHUB_BASE__INST4_SEG1                     0
0638 #define MMHUB_BASE__INST4_SEG2                     0
0639 #define MMHUB_BASE__INST4_SEG3                     0
0640 #define MMHUB_BASE__INST4_SEG4                     0
0641 #define MMHUB_BASE__INST4_SEG5                     0
0642 
0643 #define MMHUB_BASE__INST5_SEG0                     0
0644 #define MMHUB_BASE__INST5_SEG1                     0
0645 #define MMHUB_BASE__INST5_SEG2                     0
0646 #define MMHUB_BASE__INST5_SEG3                     0
0647 #define MMHUB_BASE__INST5_SEG4                     0
0648 #define MMHUB_BASE__INST5_SEG5                     0
0649 
0650 #define MMHUB_BASE__INST6_SEG0                     0
0651 #define MMHUB_BASE__INST6_SEG1                     0
0652 #define MMHUB_BASE__INST6_SEG2                     0
0653 #define MMHUB_BASE__INST6_SEG3                     0
0654 #define MMHUB_BASE__INST6_SEG4                     0
0655 #define MMHUB_BASE__INST6_SEG5                     0
0656 
0657 #define MP0_BASE__INST0_SEG0                       0x00016000
0658 #define MP0_BASE__INST0_SEG1                       0x00DC0000
0659 #define MP0_BASE__INST0_SEG2                       0x00E00000
0660 #define MP0_BASE__INST0_SEG3                       0x00E40000
0661 #define MP0_BASE__INST0_SEG4                       0x0243FC00
0662 #define MP0_BASE__INST0_SEG5                       0
0663 
0664 #define MP0_BASE__INST1_SEG0                       0
0665 #define MP0_BASE__INST1_SEG1                       0
0666 #define MP0_BASE__INST1_SEG2                       0
0667 #define MP0_BASE__INST1_SEG3                       0
0668 #define MP0_BASE__INST1_SEG4                       0
0669 #define MP0_BASE__INST1_SEG5                       0
0670 
0671 #define MP0_BASE__INST2_SEG0                       0
0672 #define MP0_BASE__INST2_SEG1                       0
0673 #define MP0_BASE__INST2_SEG2                       0
0674 #define MP0_BASE__INST2_SEG3                       0
0675 #define MP0_BASE__INST2_SEG4                       0
0676 #define MP0_BASE__INST2_SEG5                       0
0677 
0678 #define MP0_BASE__INST3_SEG0                       0
0679 #define MP0_BASE__INST3_SEG1                       0
0680 #define MP0_BASE__INST3_SEG2                       0
0681 #define MP0_BASE__INST3_SEG3                       0
0682 #define MP0_BASE__INST3_SEG4                       0
0683 #define MP0_BASE__INST3_SEG5                       0
0684 
0685 #define MP0_BASE__INST4_SEG0                       0
0686 #define MP0_BASE__INST4_SEG1                       0
0687 #define MP0_BASE__INST4_SEG2                       0
0688 #define MP0_BASE__INST4_SEG3                       0
0689 #define MP0_BASE__INST4_SEG4                       0
0690 #define MP0_BASE__INST4_SEG5                       0
0691 
0692 #define MP0_BASE__INST5_SEG0                       0
0693 #define MP0_BASE__INST5_SEG1                       0
0694 #define MP0_BASE__INST5_SEG2                       0
0695 #define MP0_BASE__INST5_SEG3                       0
0696 #define MP0_BASE__INST5_SEG4                       0
0697 #define MP0_BASE__INST5_SEG5                       0
0698 
0699 #define MP0_BASE__INST6_SEG0                       0
0700 #define MP0_BASE__INST6_SEG1                       0
0701 #define MP0_BASE__INST6_SEG2                       0
0702 #define MP0_BASE__INST6_SEG3                       0
0703 #define MP0_BASE__INST6_SEG4                       0
0704 #define MP0_BASE__INST6_SEG5                       0
0705 
0706 #define MP1_BASE__INST0_SEG0                       0x00016200
0707 #define MP1_BASE__INST0_SEG1                       0x00E80000
0708 #define MP1_BASE__INST0_SEG2                       0x00EC0000
0709 #define MP1_BASE__INST0_SEG3                       0x00F00000
0710 #define MP1_BASE__INST0_SEG4                       0x02400400
0711 #define MP1_BASE__INST0_SEG5                       0
0712 
0713 #define MP1_BASE__INST1_SEG0                       0
0714 #define MP1_BASE__INST1_SEG1                       0
0715 #define MP1_BASE__INST1_SEG2                       0
0716 #define MP1_BASE__INST1_SEG3                       0
0717 #define MP1_BASE__INST1_SEG4                       0
0718 #define MP1_BASE__INST1_SEG5                       0
0719 
0720 #define MP1_BASE__INST2_SEG0                       0
0721 #define MP1_BASE__INST2_SEG1                       0
0722 #define MP1_BASE__INST2_SEG2                       0
0723 #define MP1_BASE__INST2_SEG3                       0
0724 #define MP1_BASE__INST2_SEG4                       0
0725 #define MP1_BASE__INST2_SEG5                       0
0726 
0727 #define MP1_BASE__INST3_SEG0                       0
0728 #define MP1_BASE__INST3_SEG1                       0
0729 #define MP1_BASE__INST3_SEG2                       0
0730 #define MP1_BASE__INST3_SEG3                       0
0731 #define MP1_BASE__INST3_SEG4                       0
0732 #define MP1_BASE__INST3_SEG5                       0
0733 
0734 #define MP1_BASE__INST4_SEG0                       0
0735 #define MP1_BASE__INST4_SEG1                       0
0736 #define MP1_BASE__INST4_SEG2                       0
0737 #define MP1_BASE__INST4_SEG3                       0
0738 #define MP1_BASE__INST4_SEG4                       0
0739 #define MP1_BASE__INST4_SEG5                       0
0740 
0741 #define MP1_BASE__INST5_SEG0                       0
0742 #define MP1_BASE__INST5_SEG1                       0
0743 #define MP1_BASE__INST5_SEG2                       0
0744 #define MP1_BASE__INST5_SEG3                       0
0745 #define MP1_BASE__INST5_SEG4                       0
0746 #define MP1_BASE__INST5_SEG5                       0
0747 
0748 #define MP1_BASE__INST6_SEG0                       0
0749 #define MP1_BASE__INST6_SEG1                       0
0750 #define MP1_BASE__INST6_SEG2                       0
0751 #define MP1_BASE__INST6_SEG3                       0
0752 #define MP1_BASE__INST6_SEG4                       0
0753 #define MP1_BASE__INST6_SEG5                       0
0754 
0755 #define NBIO_BASE__INST0_SEG0                      0x00000000
0756 #define NBIO_BASE__INST0_SEG1                      0x00000014
0757 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0758 #define NBIO_BASE__INST0_SEG3                      0x00010400
0759 #define NBIO_BASE__INST0_SEG4                      0x0241B000
0760 #define NBIO_BASE__INST0_SEG5                      0x04040000
0761 
0762 #define NBIO_BASE__INST1_SEG0                      0
0763 #define NBIO_BASE__INST1_SEG1                      0
0764 #define NBIO_BASE__INST1_SEG2                      0
0765 #define NBIO_BASE__INST1_SEG3                      0
0766 #define NBIO_BASE__INST1_SEG4                      0
0767 #define NBIO_BASE__INST1_SEG5                      0
0768 
0769 #define NBIO_BASE__INST2_SEG0                      0
0770 #define NBIO_BASE__INST2_SEG1                      0
0771 #define NBIO_BASE__INST2_SEG2                      0
0772 #define NBIO_BASE__INST2_SEG3                      0
0773 #define NBIO_BASE__INST2_SEG4                      0
0774 #define NBIO_BASE__INST2_SEG5                      0
0775 
0776 #define NBIO_BASE__INST3_SEG0                      0
0777 #define NBIO_BASE__INST3_SEG1                      0
0778 #define NBIO_BASE__INST3_SEG2                      0
0779 #define NBIO_BASE__INST3_SEG3                      0
0780 #define NBIO_BASE__INST3_SEG4                      0
0781 #define NBIO_BASE__INST3_SEG5                      0
0782 
0783 #define NBIO_BASE__INST4_SEG0                      0
0784 #define NBIO_BASE__INST4_SEG1                      0
0785 #define NBIO_BASE__INST4_SEG2                      0
0786 #define NBIO_BASE__INST4_SEG3                      0
0787 #define NBIO_BASE__INST4_SEG4                      0
0788 #define NBIO_BASE__INST4_SEG5                      0
0789 
0790 #define NBIO_BASE__INST5_SEG0                      0
0791 #define NBIO_BASE__INST5_SEG1                      0
0792 #define NBIO_BASE__INST5_SEG2                      0
0793 #define NBIO_BASE__INST5_SEG3                      0
0794 #define NBIO_BASE__INST5_SEG4                      0
0795 #define NBIO_BASE__INST5_SEG5                      0
0796 
0797 #define NBIO_BASE__INST6_SEG0                      0
0798 #define NBIO_BASE__INST6_SEG1                      0
0799 #define NBIO_BASE__INST6_SEG2                      0
0800 #define NBIO_BASE__INST6_SEG3                      0
0801 #define NBIO_BASE__INST6_SEG4                      0
0802 #define NBIO_BASE__INST6_SEG5                      0
0803 
0804 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0805 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
0806 #define OSSSYS_BASE__INST0_SEG2                    0
0807 #define OSSSYS_BASE__INST0_SEG3                    0
0808 #define OSSSYS_BASE__INST0_SEG4                    0
0809 #define OSSSYS_BASE__INST0_SEG5                    0
0810 
0811 #define OSSSYS_BASE__INST1_SEG0                    0
0812 #define OSSSYS_BASE__INST1_SEG1                    0
0813 #define OSSSYS_BASE__INST1_SEG2                    0
0814 #define OSSSYS_BASE__INST1_SEG3                    0
0815 #define OSSSYS_BASE__INST1_SEG4                    0
0816 #define OSSSYS_BASE__INST1_SEG5                    0
0817 
0818 #define OSSSYS_BASE__INST2_SEG0                    0
0819 #define OSSSYS_BASE__INST2_SEG1                    0
0820 #define OSSSYS_BASE__INST2_SEG2                    0
0821 #define OSSSYS_BASE__INST2_SEG3                    0
0822 #define OSSSYS_BASE__INST2_SEG4                    0
0823 #define OSSSYS_BASE__INST2_SEG5                    0
0824 
0825 #define OSSSYS_BASE__INST3_SEG0                    0
0826 #define OSSSYS_BASE__INST3_SEG1                    0
0827 #define OSSSYS_BASE__INST3_SEG2                    0
0828 #define OSSSYS_BASE__INST3_SEG3                    0
0829 #define OSSSYS_BASE__INST3_SEG4                    0
0830 #define OSSSYS_BASE__INST3_SEG5                    0
0831 
0832 #define OSSSYS_BASE__INST4_SEG0                    0
0833 #define OSSSYS_BASE__INST4_SEG1                    0
0834 #define OSSSYS_BASE__INST4_SEG2                    0
0835 #define OSSSYS_BASE__INST4_SEG3                    0
0836 #define OSSSYS_BASE__INST4_SEG4                    0
0837 #define OSSSYS_BASE__INST4_SEG5                    0
0838 
0839 #define OSSSYS_BASE__INST5_SEG0                    0
0840 #define OSSSYS_BASE__INST5_SEG1                    0
0841 #define OSSSYS_BASE__INST5_SEG2                    0
0842 #define OSSSYS_BASE__INST5_SEG3                    0
0843 #define OSSSYS_BASE__INST5_SEG4                    0
0844 #define OSSSYS_BASE__INST5_SEG5                    0
0845 
0846 #define OSSSYS_BASE__INST6_SEG0                    0
0847 #define OSSSYS_BASE__INST6_SEG1                    0
0848 #define OSSSYS_BASE__INST6_SEG2                    0
0849 #define OSSSYS_BASE__INST6_SEG3                    0
0850 #define OSSSYS_BASE__INST6_SEG4                    0
0851 #define OSSSYS_BASE__INST6_SEG5                    0
0852 
0853 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0854 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0855 #define SMUIO_BASE__INST0_SEG2                     0x00440000
0856 #define SMUIO_BASE__INST0_SEG3                     0x02401000
0857 #define SMUIO_BASE__INST0_SEG4                     0
0858 #define SMUIO_BASE__INST0_SEG5                     0
0859 
0860 #define SMUIO_BASE__INST1_SEG0                     0
0861 #define SMUIO_BASE__INST1_SEG1                     0
0862 #define SMUIO_BASE__INST1_SEG2                     0
0863 #define SMUIO_BASE__INST1_SEG3                     0
0864 #define SMUIO_BASE__INST1_SEG4                     0
0865 #define SMUIO_BASE__INST1_SEG5                     0
0866 
0867 #define SMUIO_BASE__INST2_SEG0                     0
0868 #define SMUIO_BASE__INST2_SEG1                     0
0869 #define SMUIO_BASE__INST2_SEG2                     0
0870 #define SMUIO_BASE__INST2_SEG3                     0
0871 #define SMUIO_BASE__INST2_SEG4                     0
0872 #define SMUIO_BASE__INST2_SEG5                     0
0873 
0874 #define SMUIO_BASE__INST3_SEG0                     0
0875 #define SMUIO_BASE__INST3_SEG1                     0
0876 #define SMUIO_BASE__INST3_SEG2                     0
0877 #define SMUIO_BASE__INST3_SEG3                     0
0878 #define SMUIO_BASE__INST3_SEG4                     0
0879 #define SMUIO_BASE__INST3_SEG5                     0
0880 
0881 #define SMUIO_BASE__INST4_SEG0                     0
0882 #define SMUIO_BASE__INST4_SEG1                     0
0883 #define SMUIO_BASE__INST4_SEG2                     0
0884 #define SMUIO_BASE__INST4_SEG3                     0
0885 #define SMUIO_BASE__INST4_SEG4                     0
0886 #define SMUIO_BASE__INST4_SEG5                     0
0887 
0888 #define SMUIO_BASE__INST5_SEG0                     0
0889 #define SMUIO_BASE__INST5_SEG1                     0
0890 #define SMUIO_BASE__INST5_SEG2                     0
0891 #define SMUIO_BASE__INST5_SEG3                     0
0892 #define SMUIO_BASE__INST5_SEG4                     0
0893 #define SMUIO_BASE__INST5_SEG5                     0
0894 
0895 #define SMUIO_BASE__INST6_SEG0                     0
0896 #define SMUIO_BASE__INST6_SEG1                     0
0897 #define SMUIO_BASE__INST6_SEG2                     0
0898 #define SMUIO_BASE__INST6_SEG3                     0
0899 #define SMUIO_BASE__INST6_SEG4                     0
0900 #define SMUIO_BASE__INST6_SEG5                     0
0901 
0902 #define THM_BASE__INST0_SEG0                       0x00016600
0903 #define THM_BASE__INST0_SEG1                       0x02400C00
0904 #define THM_BASE__INST0_SEG2                       0
0905 #define THM_BASE__INST0_SEG3                       0
0906 #define THM_BASE__INST0_SEG4                       0
0907 #define THM_BASE__INST0_SEG5                       0
0908 
0909 #define THM_BASE__INST1_SEG0                       0
0910 #define THM_BASE__INST1_SEG1                       0
0911 #define THM_BASE__INST1_SEG2                       0
0912 #define THM_BASE__INST1_SEG3                       0
0913 #define THM_BASE__INST1_SEG4                       0
0914 #define THM_BASE__INST1_SEG5                       0
0915 
0916 #define THM_BASE__INST2_SEG0                       0
0917 #define THM_BASE__INST2_SEG1                       0
0918 #define THM_BASE__INST2_SEG2                       0
0919 #define THM_BASE__INST2_SEG3                       0
0920 #define THM_BASE__INST2_SEG4                       0
0921 #define THM_BASE__INST2_SEG5                       0
0922 
0923 #define THM_BASE__INST3_SEG0                       0
0924 #define THM_BASE__INST3_SEG1                       0
0925 #define THM_BASE__INST3_SEG2                       0
0926 #define THM_BASE__INST3_SEG3                       0
0927 #define THM_BASE__INST3_SEG4                       0
0928 #define THM_BASE__INST3_SEG5                       0
0929 
0930 #define THM_BASE__INST4_SEG0                       0
0931 #define THM_BASE__INST4_SEG1                       0
0932 #define THM_BASE__INST4_SEG2                       0
0933 #define THM_BASE__INST4_SEG3                       0
0934 #define THM_BASE__INST4_SEG4                       0
0935 #define THM_BASE__INST4_SEG5                       0
0936 
0937 #define THM_BASE__INST5_SEG0                       0
0938 #define THM_BASE__INST5_SEG1                       0
0939 #define THM_BASE__INST5_SEG2                       0
0940 #define THM_BASE__INST5_SEG3                       0
0941 #define THM_BASE__INST5_SEG4                       0
0942 #define THM_BASE__INST5_SEG5                       0
0943 
0944 #define THM_BASE__INST6_SEG0                       0
0945 #define THM_BASE__INST6_SEG1                       0
0946 #define THM_BASE__INST6_SEG2                       0
0947 #define THM_BASE__INST6_SEG3                       0
0948 #define THM_BASE__INST6_SEG4                       0
0949 #define THM_BASE__INST6_SEG5                       0
0950 
0951 #define UMC_BASE__INST0_SEG0                       0x00014000
0952 #define UMC_BASE__INST0_SEG1                       0x02425800
0953 #define UMC_BASE__INST0_SEG2                       0
0954 #define UMC_BASE__INST0_SEG3                       0
0955 #define UMC_BASE__INST0_SEG4                       0
0956 #define UMC_BASE__INST0_SEG5                       0
0957 
0958 #define UMC_BASE__INST1_SEG0                       0x00054000
0959 #define UMC_BASE__INST1_SEG1                       0x02425C00
0960 #define UMC_BASE__INST1_SEG2                       0
0961 #define UMC_BASE__INST1_SEG3                       0
0962 #define UMC_BASE__INST1_SEG4                       0
0963 #define UMC_BASE__INST1_SEG5                       0
0964 
0965 #define UMC_BASE__INST2_SEG0                       0x00094000
0966 #define UMC_BASE__INST2_SEG1                       0x02426000
0967 #define UMC_BASE__INST2_SEG2                       0
0968 #define UMC_BASE__INST2_SEG3                       0
0969 #define UMC_BASE__INST2_SEG4                       0
0970 #define UMC_BASE__INST2_SEG5                       0
0971 
0972 #define UMC_BASE__INST3_SEG0                       0x000D4000
0973 #define UMC_BASE__INST3_SEG1                       0x02426400
0974 #define UMC_BASE__INST3_SEG2                       0
0975 #define UMC_BASE__INST3_SEG3                       0
0976 #define UMC_BASE__INST3_SEG4                       0
0977 #define UMC_BASE__INST3_SEG5                       0
0978 
0979 #define UMC_BASE__INST4_SEG0                       0
0980 #define UMC_BASE__INST4_SEG1                       0
0981 #define UMC_BASE__INST4_SEG2                       0
0982 #define UMC_BASE__INST4_SEG3                       0
0983 #define UMC_BASE__INST4_SEG4                       0
0984 #define UMC_BASE__INST4_SEG5                       0
0985 
0986 #define UMC_BASE__INST5_SEG0                       0
0987 #define UMC_BASE__INST5_SEG1                       0
0988 #define UMC_BASE__INST5_SEG2                       0
0989 #define UMC_BASE__INST5_SEG3                       0
0990 #define UMC_BASE__INST5_SEG4                       0
0991 #define UMC_BASE__INST5_SEG5                       0
0992 
0993 #define UMC_BASE__INST6_SEG0                       0
0994 #define UMC_BASE__INST6_SEG1                       0
0995 #define UMC_BASE__INST6_SEG2                       0
0996 #define UMC_BASE__INST6_SEG3                       0
0997 #define UMC_BASE__INST6_SEG4                       0
0998 #define UMC_BASE__INST6_SEG5                       0
0999 
1000 #define VCN0_BASE__INST0_SEG0                      0x00007800
1001 #define VCN0_BASE__INST0_SEG1                      0x00007E00
1002 #define VCN0_BASE__INST0_SEG2                      0x02403000
1003 #define VCN0_BASE__INST0_SEG3                      0
1004 #define VCN0_BASE__INST0_SEG4                      0
1005 #define VCN0_BASE__INST0_SEG5                      0
1006 
1007 #define VCN0_BASE__INST1_SEG0                      0
1008 #define VCN0_BASE__INST1_SEG1                      0
1009 #define VCN0_BASE__INST1_SEG2                      0
1010 #define VCN0_BASE__INST1_SEG3                      0
1011 #define VCN0_BASE__INST1_SEG4                      0
1012 #define VCN0_BASE__INST1_SEG5                      0
1013 
1014 #define VCN0_BASE__INST2_SEG0                      0
1015 #define VCN0_BASE__INST2_SEG1                      0
1016 #define VCN0_BASE__INST2_SEG2                      0
1017 #define VCN0_BASE__INST2_SEG3                      0
1018 #define VCN0_BASE__INST2_SEG4                      0
1019 #define VCN0_BASE__INST2_SEG5                      0
1020 
1021 #define VCN0_BASE__INST3_SEG0                      0
1022 #define VCN0_BASE__INST3_SEG1                      0
1023 #define VCN0_BASE__INST3_SEG2                      0
1024 #define VCN0_BASE__INST3_SEG3                      0
1025 #define VCN0_BASE__INST3_SEG4                      0
1026 #define VCN0_BASE__INST3_SEG5                      0
1027 
1028 #define VCN0_BASE__INST4_SEG0                      0
1029 #define VCN0_BASE__INST4_SEG1                      0
1030 #define VCN0_BASE__INST4_SEG2                      0
1031 #define VCN0_BASE__INST4_SEG3                      0
1032 #define VCN0_BASE__INST4_SEG4                      0
1033 #define VCN0_BASE__INST4_SEG5                      0
1034 
1035 #define VCN0_BASE__INST5_SEG0                      0
1036 #define VCN0_BASE__INST5_SEG1                      0
1037 #define VCN0_BASE__INST5_SEG2                      0
1038 #define VCN0_BASE__INST5_SEG3                      0
1039 #define VCN0_BASE__INST5_SEG4                      0
1040 #define VCN0_BASE__INST5_SEG5                      0
1041 
1042 #define VCN0_BASE__INST6_SEG0                      0
1043 #define VCN0_BASE__INST6_SEG1                      0
1044 #define VCN0_BASE__INST6_SEG2                      0
1045 #define VCN0_BASE__INST6_SEG3                      0
1046 #define VCN0_BASE__INST6_SEG4                      0
1047 #define VCN0_BASE__INST6_SEG5                      0
1048 
1049 #endif
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