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0001 /*
0002  * Copyright (C) 2018  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _cyan_skillfish_ip_offset_HEADER
0022 #define _cyan_skillfish_ip_offset_HEADER
0023 
0024 #define MAX_INSTANCE                                       6
0025 #define MAX_SEGMENT                                        5
0026 
0027 
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 } __maybe_unused;
0032 
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037 
0038 
0039 static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C00, 0, 0, 0, 0 } },
0040                     { { 0, 0, 0, 0, 0 } },
0041                     { { 0, 0, 0, 0, 0 } },
0042                     { { 0, 0, 0, 0, 0 } },
0043                     { { 0, 0, 0, 0, 0 } },
0044                     { { 0, 0, 0, 0, 0 } } } };
0045 static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0, 0, 0, 0 } },
0046                                         { { 0x00016E00, 0, 0, 0, 0 } },
0047                                         { { 0x00017000, 0, 0, 0, 0 } },
0048                                         { { 0x00017200, 0, 0, 0, 0 } },
0049                                         { { 0x00017E00, 0, 0, 0, 0 } },
0050                                         { { 0x0001B000, 0, 0, 0, 0 } } } };
0051 static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0 } },
0053                                         { { 0, 0, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0 } } } };
0057 static const struct IP_BASE DMU_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } },
0058                                         { { 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0 } } } };
0063 static const struct IP_BASE FUSE_BASE            ={ { { { 0x00017400, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0 } } } };
0069 static const struct IP_BASE GC_BASE            ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0 } } } };
0075 static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0 } } } };
0081 static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0 } } } };
0087 static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0 } } } };
0093 static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0 } } } };
0099 static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
0100                                         { { 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0 } } } };
0105 static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0, 0, 0, 0 } },
0106                     { { 0, 0, 0, 0, 0 } },
0107                     { { 0, 0, 0, 0, 0 } },
0108                     { { 0, 0, 0, 0, 0 } },
0109                     { { 0, 0, 0, 0, 0 } },
0110                     { { 0, 0, 0, 0, 0 } } } };
0111 static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } },
0112                     { { 0, 0, 0, 0, 0 } },
0113                     { { 0, 0, 0, 0, 0 } },
0114                     { { 0, 0, 0, 0, 0 } },
0115                     { { 0, 0, 0, 0, 0 } },
0116                     { { 0, 0, 0, 0, 0 } } } };
0117 static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0 } } } };
0123 static const struct IP_BASE UMC0_BASE            ={ { { { 0x00014000, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0 } } } };
0129 static const struct IP_BASE UVD0_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0 } },
0133                     { { 0, 0, 0, 0, 0 } },
0134                     { { 0, 0, 0, 0, 0 } } } };
0135 
0136 
0137 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0138 #define ATHUB_BASE__INST0_SEG1                     0
0139 #define ATHUB_BASE__INST0_SEG2                     0
0140 #define ATHUB_BASE__INST0_SEG3                     0
0141 #define ATHUB_BASE__INST0_SEG4                     0
0142 
0143 #define ATHUB_BASE__INST1_SEG0                     0
0144 #define ATHUB_BASE__INST1_SEG1                     0
0145 #define ATHUB_BASE__INST1_SEG2                     0
0146 #define ATHUB_BASE__INST1_SEG3                     0
0147 #define ATHUB_BASE__INST1_SEG4                     0
0148 
0149 #define ATHUB_BASE__INST2_SEG0                     0
0150 #define ATHUB_BASE__INST2_SEG1                     0
0151 #define ATHUB_BASE__INST2_SEG2                     0
0152 #define ATHUB_BASE__INST2_SEG3                     0
0153 #define ATHUB_BASE__INST2_SEG4                     0
0154 
0155 #define ATHUB_BASE__INST3_SEG0                     0
0156 #define ATHUB_BASE__INST3_SEG1                     0
0157 #define ATHUB_BASE__INST3_SEG2                     0
0158 #define ATHUB_BASE__INST3_SEG3                     0
0159 #define ATHUB_BASE__INST3_SEG4                     0
0160 
0161 #define ATHUB_BASE__INST4_SEG0                     0
0162 #define ATHUB_BASE__INST4_SEG1                     0
0163 #define ATHUB_BASE__INST4_SEG2                     0
0164 #define ATHUB_BASE__INST4_SEG3                     0
0165 #define ATHUB_BASE__INST4_SEG4                     0
0166 
0167 #define ATHUB_BASE__INST5_SEG0                     0
0168 #define ATHUB_BASE__INST5_SEG1                     0
0169 #define ATHUB_BASE__INST5_SEG2                     0
0170 #define ATHUB_BASE__INST5_SEG3                     0
0171 #define ATHUB_BASE__INST5_SEG4                     0
0172 
0173 #define CLK_BASE__INST0_SEG0                       0x00016C00
0174 #define CLK_BASE__INST0_SEG1                       0
0175 #define CLK_BASE__INST0_SEG2                       0
0176 #define CLK_BASE__INST0_SEG3                       0
0177 #define CLK_BASE__INST0_SEG4                       0
0178 
0179 #define CLK_BASE__INST1_SEG0                       0x00016E00
0180 #define CLK_BASE__INST1_SEG1                       0
0181 #define CLK_BASE__INST1_SEG2                       0
0182 #define CLK_BASE__INST1_SEG3                       0
0183 #define CLK_BASE__INST1_SEG4                       0
0184 
0185 #define CLK_BASE__INST2_SEG0                       0x00017000
0186 #define CLK_BASE__INST2_SEG1                       0
0187 #define CLK_BASE__INST2_SEG2                       0
0188 #define CLK_BASE__INST2_SEG3                       0
0189 #define CLK_BASE__INST2_SEG4                       0
0190 
0191 #define CLK_BASE__INST3_SEG0                       0x00017200
0192 #define CLK_BASE__INST3_SEG1                       0
0193 #define CLK_BASE__INST3_SEG2                       0
0194 #define CLK_BASE__INST3_SEG3                       0
0195 #define CLK_BASE__INST3_SEG4                       0
0196 
0197 #define CLK_BASE__INST4_SEG0                       0x00017E00
0198 #define CLK_BASE__INST4_SEG1                       0
0199 #define CLK_BASE__INST4_SEG2                       0
0200 #define CLK_BASE__INST4_SEG3                       0
0201 #define CLK_BASE__INST4_SEG4                       0
0202 
0203 #define CLK_BASE__INST5_SEG0                       0x0001B000
0204 #define CLK_BASE__INST5_SEG1                       0
0205 #define CLK_BASE__INST5_SEG2                       0
0206 #define CLK_BASE__INST5_SEG3                       0
0207 #define CLK_BASE__INST5_SEG4                       0
0208 
0209 #define DF_BASE__INST0_SEG0                        0x00007000
0210 #define DF_BASE__INST0_SEG1                        0
0211 #define DF_BASE__INST0_SEG2                        0
0212 #define DF_BASE__INST0_SEG3                        0
0213 #define DF_BASE__INST0_SEG4                        0
0214 
0215 #define DF_BASE__INST1_SEG0                        0
0216 #define DF_BASE__INST1_SEG1                        0
0217 #define DF_BASE__INST1_SEG2                        0
0218 #define DF_BASE__INST1_SEG3                        0
0219 #define DF_BASE__INST1_SEG4                        0
0220 
0221 #define DF_BASE__INST2_SEG0                        0
0222 #define DF_BASE__INST2_SEG1                        0
0223 #define DF_BASE__INST2_SEG2                        0
0224 #define DF_BASE__INST2_SEG3                        0
0225 #define DF_BASE__INST2_SEG4                        0
0226 
0227 #define DF_BASE__INST3_SEG0                        0
0228 #define DF_BASE__INST3_SEG1                        0
0229 #define DF_BASE__INST3_SEG2                        0
0230 #define DF_BASE__INST3_SEG3                        0
0231 #define DF_BASE__INST3_SEG4                        0
0232 
0233 #define DF_BASE__INST4_SEG0                        0
0234 #define DF_BASE__INST4_SEG1                        0
0235 #define DF_BASE__INST4_SEG2                        0
0236 #define DF_BASE__INST4_SEG3                        0
0237 #define DF_BASE__INST4_SEG4                        0
0238 
0239 #define DF_BASE__INST5_SEG0                        0
0240 #define DF_BASE__INST5_SEG1                        0
0241 #define DF_BASE__INST5_SEG2                        0
0242 #define DF_BASE__INST5_SEG3                        0
0243 #define DF_BASE__INST5_SEG4                        0
0244 
0245 #define DMU_BASE__INST0_SEG0                       0x00000012
0246 #define DMU_BASE__INST0_SEG1                       0x000000C0
0247 #define DMU_BASE__INST0_SEG2                       0x000034C0
0248 #define DMU_BASE__INST0_SEG3                       0x00009000
0249 #define DMU_BASE__INST0_SEG4                       0
0250 
0251 #define DMU_BASE__INST1_SEG0                       0
0252 #define DMU_BASE__INST1_SEG1                       0
0253 #define DMU_BASE__INST1_SEG2                       0
0254 #define DMU_BASE__INST1_SEG3                       0
0255 #define DMU_BASE__INST1_SEG4                       0
0256 
0257 #define DMU_BASE__INST2_SEG0                       0
0258 #define DMU_BASE__INST2_SEG1                       0
0259 #define DMU_BASE__INST2_SEG2                       0
0260 #define DMU_BASE__INST2_SEG3                       0
0261 #define DMU_BASE__INST2_SEG4                       0
0262 
0263 #define DMU_BASE__INST3_SEG0                       0
0264 #define DMU_BASE__INST3_SEG1                       0
0265 #define DMU_BASE__INST3_SEG2                       0
0266 #define DMU_BASE__INST3_SEG3                       0
0267 #define DMU_BASE__INST3_SEG4                       0
0268 
0269 #define DMU_BASE__INST4_SEG0                       0
0270 #define DMU_BASE__INST4_SEG1                       0
0271 #define DMU_BASE__INST4_SEG2                       0
0272 #define DMU_BASE__INST4_SEG3                       0
0273 #define DMU_BASE__INST4_SEG4                       0
0274 
0275 #define DMU_BASE__INST5_SEG0                       0
0276 #define DMU_BASE__INST5_SEG1                       0
0277 #define DMU_BASE__INST5_SEG2                       0
0278 #define DMU_BASE__INST5_SEG3                       0
0279 #define DMU_BASE__INST5_SEG4                       0
0280 
0281 #define FUSE_BASE__INST0_SEG0                      0x00017400
0282 #define FUSE_BASE__INST0_SEG1                      0
0283 #define FUSE_BASE__INST0_SEG2                      0
0284 #define FUSE_BASE__INST0_SEG3                      0
0285 #define FUSE_BASE__INST0_SEG4                      0
0286 
0287 #define FUSE_BASE__INST1_SEG0                      0
0288 #define FUSE_BASE__INST1_SEG1                      0
0289 #define FUSE_BASE__INST1_SEG2                      0
0290 #define FUSE_BASE__INST1_SEG3                      0
0291 #define FUSE_BASE__INST1_SEG4                      0
0292 
0293 #define FUSE_BASE__INST2_SEG0                      0
0294 #define FUSE_BASE__INST2_SEG1                      0
0295 #define FUSE_BASE__INST2_SEG2                      0
0296 #define FUSE_BASE__INST2_SEG3                      0
0297 #define FUSE_BASE__INST2_SEG4                      0
0298 
0299 #define FUSE_BASE__INST3_SEG0                      0
0300 #define FUSE_BASE__INST3_SEG1                      0
0301 #define FUSE_BASE__INST3_SEG2                      0
0302 #define FUSE_BASE__INST3_SEG3                      0
0303 #define FUSE_BASE__INST3_SEG4                      0
0304 
0305 #define FUSE_BASE__INST4_SEG0                      0
0306 #define FUSE_BASE__INST4_SEG1                      0
0307 #define FUSE_BASE__INST4_SEG2                      0
0308 #define FUSE_BASE__INST4_SEG3                      0
0309 #define FUSE_BASE__INST4_SEG4                      0
0310 
0311 #define FUSE_BASE__INST5_SEG0                      0
0312 #define FUSE_BASE__INST5_SEG1                      0
0313 #define FUSE_BASE__INST5_SEG2                      0
0314 #define FUSE_BASE__INST5_SEG3                      0
0315 #define FUSE_BASE__INST5_SEG4                      0
0316 
0317 #define GC_BASE__INST0_SEG0                        0x00001260
0318 #define GC_BASE__INST0_SEG1                        0x0000A000
0319 #define GC_BASE__INST0_SEG2                        0
0320 #define GC_BASE__INST0_SEG3                        0
0321 #define GC_BASE__INST0_SEG4                        0
0322 
0323 #define GC_BASE__INST1_SEG0                        0
0324 #define GC_BASE__INST1_SEG1                        0
0325 #define GC_BASE__INST1_SEG2                        0
0326 #define GC_BASE__INST1_SEG3                        0
0327 #define GC_BASE__INST1_SEG4                        0
0328 
0329 #define GC_BASE__INST2_SEG0                        0
0330 #define GC_BASE__INST2_SEG1                        0
0331 #define GC_BASE__INST2_SEG2                        0
0332 #define GC_BASE__INST2_SEG3                        0
0333 #define GC_BASE__INST2_SEG4                        0
0334 
0335 #define GC_BASE__INST3_SEG0                        0
0336 #define GC_BASE__INST3_SEG1                        0
0337 #define GC_BASE__INST3_SEG2                        0
0338 #define GC_BASE__INST3_SEG3                        0
0339 #define GC_BASE__INST3_SEG4                        0
0340 
0341 #define GC_BASE__INST4_SEG0                        0
0342 #define GC_BASE__INST4_SEG1                        0
0343 #define GC_BASE__INST4_SEG2                        0
0344 #define GC_BASE__INST4_SEG3                        0
0345 #define GC_BASE__INST4_SEG4                        0
0346 
0347 #define GC_BASE__INST5_SEG0                        0
0348 #define GC_BASE__INST5_SEG1                        0
0349 #define GC_BASE__INST5_SEG2                        0
0350 #define GC_BASE__INST5_SEG3                        0
0351 #define GC_BASE__INST5_SEG4                        0
0352 
0353 #define HDP_BASE__INST0_SEG0                       0x00000F20
0354 #define HDP_BASE__INST0_SEG1                       0
0355 #define HDP_BASE__INST0_SEG2                       0
0356 #define HDP_BASE__INST0_SEG3                       0
0357 #define HDP_BASE__INST0_SEG4                       0
0358 
0359 #define HDP_BASE__INST1_SEG0                       0
0360 #define HDP_BASE__INST1_SEG1                       0
0361 #define HDP_BASE__INST1_SEG2                       0
0362 #define HDP_BASE__INST1_SEG3                       0
0363 #define HDP_BASE__INST1_SEG4                       0
0364 
0365 #define HDP_BASE__INST2_SEG0                       0
0366 #define HDP_BASE__INST2_SEG1                       0
0367 #define HDP_BASE__INST2_SEG2                       0
0368 #define HDP_BASE__INST2_SEG3                       0
0369 #define HDP_BASE__INST2_SEG4                       0
0370 
0371 #define HDP_BASE__INST3_SEG0                       0
0372 #define HDP_BASE__INST3_SEG1                       0
0373 #define HDP_BASE__INST3_SEG2                       0
0374 #define HDP_BASE__INST3_SEG3                       0
0375 #define HDP_BASE__INST3_SEG4                       0
0376 
0377 #define HDP_BASE__INST4_SEG0                       0
0378 #define HDP_BASE__INST4_SEG1                       0
0379 #define HDP_BASE__INST4_SEG2                       0
0380 #define HDP_BASE__INST4_SEG3                       0
0381 #define HDP_BASE__INST4_SEG4                       0
0382 
0383 #define HDP_BASE__INST5_SEG0                       0
0384 #define HDP_BASE__INST5_SEG1                       0
0385 #define HDP_BASE__INST5_SEG2                       0
0386 #define HDP_BASE__INST5_SEG3                       0
0387 #define HDP_BASE__INST5_SEG4                       0
0388 
0389 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0390 #define MMHUB_BASE__INST0_SEG1                     0
0391 #define MMHUB_BASE__INST0_SEG2                     0
0392 #define MMHUB_BASE__INST0_SEG3                     0
0393 #define MMHUB_BASE__INST0_SEG4                     0
0394 
0395 #define MMHUB_BASE__INST1_SEG0                     0
0396 #define MMHUB_BASE__INST1_SEG1                     0
0397 #define MMHUB_BASE__INST1_SEG2                     0
0398 #define MMHUB_BASE__INST1_SEG3                     0
0399 #define MMHUB_BASE__INST1_SEG4                     0
0400 
0401 #define MMHUB_BASE__INST2_SEG0                     0
0402 #define MMHUB_BASE__INST2_SEG1                     0
0403 #define MMHUB_BASE__INST2_SEG2                     0
0404 #define MMHUB_BASE__INST2_SEG3                     0
0405 #define MMHUB_BASE__INST2_SEG4                     0
0406 
0407 #define MMHUB_BASE__INST3_SEG0                     0
0408 #define MMHUB_BASE__INST3_SEG1                     0
0409 #define MMHUB_BASE__INST3_SEG2                     0
0410 #define MMHUB_BASE__INST3_SEG3                     0
0411 #define MMHUB_BASE__INST3_SEG4                     0
0412 
0413 #define MMHUB_BASE__INST4_SEG0                     0
0414 #define MMHUB_BASE__INST4_SEG1                     0
0415 #define MMHUB_BASE__INST4_SEG2                     0
0416 #define MMHUB_BASE__INST4_SEG3                     0
0417 #define MMHUB_BASE__INST4_SEG4                     0
0418 
0419 #define MMHUB_BASE__INST5_SEG0                     0
0420 #define MMHUB_BASE__INST5_SEG1                     0
0421 #define MMHUB_BASE__INST5_SEG2                     0
0422 #define MMHUB_BASE__INST5_SEG3                     0
0423 #define MMHUB_BASE__INST5_SEG4                     0
0424 
0425 #define MP0_BASE__INST0_SEG0                       0x00016000
0426 #define MP0_BASE__INST0_SEG1                       0
0427 #define MP0_BASE__INST0_SEG2                       0
0428 #define MP0_BASE__INST0_SEG3                       0
0429 #define MP0_BASE__INST0_SEG4                       0
0430 
0431 #define MP0_BASE__INST1_SEG0                       0
0432 #define MP0_BASE__INST1_SEG1                       0
0433 #define MP0_BASE__INST1_SEG2                       0
0434 #define MP0_BASE__INST1_SEG3                       0
0435 #define MP0_BASE__INST1_SEG4                       0
0436 
0437 #define MP0_BASE__INST2_SEG0                       0
0438 #define MP0_BASE__INST2_SEG1                       0
0439 #define MP0_BASE__INST2_SEG2                       0
0440 #define MP0_BASE__INST2_SEG3                       0
0441 #define MP0_BASE__INST2_SEG4                       0
0442 
0443 #define MP0_BASE__INST3_SEG0                       0
0444 #define MP0_BASE__INST3_SEG1                       0
0445 #define MP0_BASE__INST3_SEG2                       0
0446 #define MP0_BASE__INST3_SEG3                       0
0447 #define MP0_BASE__INST3_SEG4                       0
0448 
0449 #define MP0_BASE__INST4_SEG0                       0
0450 #define MP0_BASE__INST4_SEG1                       0
0451 #define MP0_BASE__INST4_SEG2                       0
0452 #define MP0_BASE__INST4_SEG3                       0
0453 #define MP0_BASE__INST4_SEG4                       0
0454 
0455 #define MP0_BASE__INST5_SEG0                       0
0456 #define MP0_BASE__INST5_SEG1                       0
0457 #define MP0_BASE__INST5_SEG2                       0
0458 #define MP0_BASE__INST5_SEG3                       0
0459 #define MP0_BASE__INST5_SEG4                       0
0460 
0461 #define MP1_BASE__INST0_SEG0                       0x00016000
0462 #define MP1_BASE__INST0_SEG1                       0
0463 #define MP1_BASE__INST0_SEG2                       0
0464 #define MP1_BASE__INST0_SEG3                       0
0465 #define MP1_BASE__INST0_SEG4                       0
0466 
0467 #define MP1_BASE__INST1_SEG0                       0
0468 #define MP1_BASE__INST1_SEG1                       0
0469 #define MP1_BASE__INST1_SEG2                       0
0470 #define MP1_BASE__INST1_SEG3                       0
0471 #define MP1_BASE__INST1_SEG4                       0
0472 
0473 #define MP1_BASE__INST2_SEG0                       0
0474 #define MP1_BASE__INST2_SEG1                       0
0475 #define MP1_BASE__INST2_SEG2                       0
0476 #define MP1_BASE__INST2_SEG3                       0
0477 #define MP1_BASE__INST2_SEG4                       0
0478 
0479 #define MP1_BASE__INST3_SEG0                       0
0480 #define MP1_BASE__INST3_SEG1                       0
0481 #define MP1_BASE__INST3_SEG2                       0
0482 #define MP1_BASE__INST3_SEG3                       0
0483 #define MP1_BASE__INST3_SEG4                       0
0484 
0485 #define MP1_BASE__INST4_SEG0                       0
0486 #define MP1_BASE__INST4_SEG1                       0
0487 #define MP1_BASE__INST4_SEG2                       0
0488 #define MP1_BASE__INST4_SEG3                       0
0489 #define MP1_BASE__INST4_SEG4                       0
0490 
0491 #define MP1_BASE__INST5_SEG0                       0
0492 #define MP1_BASE__INST5_SEG1                       0
0493 #define MP1_BASE__INST5_SEG2                       0
0494 #define MP1_BASE__INST5_SEG3                       0
0495 #define MP1_BASE__INST5_SEG4                       0
0496 
0497 #define NBIO_BASE__INST0_SEG0                     0x00000000
0498 #define NBIO_BASE__INST0_SEG1                     0x00000014
0499 #define NBIO_BASE__INST0_SEG2                     0x00000D20
0500 #define NBIO_BASE__INST0_SEG3                     0x00010400
0501 #define NBIO_BASE__INST0_SEG4                     0
0502 
0503 #define NBIO_BASE__INST1_SEG0                     0
0504 #define NBIO_BASE__INST1_SEG1                     0
0505 #define NBIO_BASE__INST1_SEG2                     0
0506 #define NBIO_BASE__INST1_SEG3                     0
0507 #define NBIO_BASE__INST1_SEG4                     0
0508 
0509 #define NBIO_BASE__INST2_SEG0                     0
0510 #define NBIO_BASE__INST2_SEG1                     0
0511 #define NBIO_BASE__INST2_SEG2                     0
0512 #define NBIO_BASE__INST2_SEG3                     0
0513 #define NBIO_BASE__INST2_SEG4                     0
0514 
0515 #define NBIO_BASE__INST3_SEG0                     0
0516 #define NBIO_BASE__INST3_SEG1                     0
0517 #define NBIO_BASE__INST3_SEG2                     0
0518 #define NBIO_BASE__INST3_SEG3                     0
0519 #define NBIO_BASE__INST3_SEG4                     0
0520 
0521 #define NBIO_BASE__INST4_SEG0                     0
0522 #define NBIO_BASE__INST4_SEG1                     0
0523 #define NBIO_BASE__INST4_SEG2                     0
0524 #define NBIO_BASE__INST4_SEG3                     0
0525 #define NBIO_BASE__INST4_SEG4                     0
0526 
0527 #define NBIO_BASE__INST5_SEG0                     0
0528 #define NBIO_BASE__INST5_SEG1                     0
0529 #define NBIO_BASE__INST5_SEG2                     0
0530 #define NBIO_BASE__INST5_SEG3                     0
0531 #define NBIO_BASE__INST5_SEG4                     0
0532 
0533 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0534 #define OSSSYS_BASE__INST0_SEG1                    0
0535 #define OSSSYS_BASE__INST0_SEG2                    0
0536 #define OSSSYS_BASE__INST0_SEG3                    0
0537 #define OSSSYS_BASE__INST0_SEG4                    0
0538 
0539 #define OSSSYS_BASE__INST1_SEG0                    0
0540 #define OSSSYS_BASE__INST1_SEG1                    0
0541 #define OSSSYS_BASE__INST1_SEG2                    0
0542 #define OSSSYS_BASE__INST1_SEG3                    0
0543 #define OSSSYS_BASE__INST1_SEG4                    0
0544 
0545 #define OSSSYS_BASE__INST2_SEG0                    0
0546 #define OSSSYS_BASE__INST2_SEG1                    0
0547 #define OSSSYS_BASE__INST2_SEG2                    0
0548 #define OSSSYS_BASE__INST2_SEG3                    0
0549 #define OSSSYS_BASE__INST2_SEG4                    0
0550 
0551 #define OSSSYS_BASE__INST3_SEG0                    0
0552 #define OSSSYS_BASE__INST3_SEG1                    0
0553 #define OSSSYS_BASE__INST3_SEG2                    0
0554 #define OSSSYS_BASE__INST3_SEG3                    0
0555 #define OSSSYS_BASE__INST3_SEG4                    0
0556 
0557 #define OSSSYS_BASE__INST4_SEG0                    0
0558 #define OSSSYS_BASE__INST4_SEG1                    0
0559 #define OSSSYS_BASE__INST4_SEG2                    0
0560 #define OSSSYS_BASE__INST4_SEG3                    0
0561 #define OSSSYS_BASE__INST4_SEG4                    0
0562 
0563 #define OSSSYS_BASE__INST5_SEG0                    0
0564 #define OSSSYS_BASE__INST5_SEG1                    0
0565 #define OSSSYS_BASE__INST5_SEG2                    0
0566 #define OSSSYS_BASE__INST5_SEG3                    0
0567 #define OSSSYS_BASE__INST5_SEG4                    0
0568 
0569 #define SMUIO_BASE__INST0_SEG0                     0x00016800
0570 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
0571 #define SMUIO_BASE__INST0_SEG2                     0
0572 #define SMUIO_BASE__INST0_SEG3                     0
0573 #define SMUIO_BASE__INST0_SEG4                     0
0574 
0575 #define SMUIO_BASE__INST1_SEG0                     0
0576 #define SMUIO_BASE__INST1_SEG1                     0
0577 #define SMUIO_BASE__INST1_SEG2                     0
0578 #define SMUIO_BASE__INST1_SEG3                     0
0579 #define SMUIO_BASE__INST1_SEG4                     0
0580 
0581 #define SMUIO_BASE__INST2_SEG0                     0
0582 #define SMUIO_BASE__INST2_SEG1                     0
0583 #define SMUIO_BASE__INST2_SEG2                     0
0584 #define SMUIO_BASE__INST2_SEG3                     0
0585 #define SMUIO_BASE__INST2_SEG4                     0
0586 
0587 #define SMUIO_BASE__INST3_SEG0                     0
0588 #define SMUIO_BASE__INST3_SEG1                     0
0589 #define SMUIO_BASE__INST3_SEG2                     0
0590 #define SMUIO_BASE__INST3_SEG3                     0
0591 #define SMUIO_BASE__INST3_SEG4                     0
0592 
0593 #define SMUIO_BASE__INST4_SEG0                     0
0594 #define SMUIO_BASE__INST4_SEG1                     0
0595 #define SMUIO_BASE__INST4_SEG2                     0
0596 #define SMUIO_BASE__INST4_SEG3                     0
0597 #define SMUIO_BASE__INST4_SEG4                     0
0598 
0599 #define SMUIO_BASE__INST5_SEG0                     0
0600 #define SMUIO_BASE__INST5_SEG1                     0
0601 #define SMUIO_BASE__INST5_SEG2                     0
0602 #define SMUIO_BASE__INST5_SEG3                     0
0603 #define SMUIO_BASE__INST5_SEG4                     0
0604 
0605 #define THM_BASE__INST0_SEG0                       0x00016600
0606 #define THM_BASE__INST0_SEG1                       0
0607 #define THM_BASE__INST0_SEG2                       0
0608 #define THM_BASE__INST0_SEG3                       0
0609 #define THM_BASE__INST0_SEG4                       0
0610 
0611 #define THM_BASE__INST1_SEG0                       0
0612 #define THM_BASE__INST1_SEG1                       0
0613 #define THM_BASE__INST1_SEG2                       0
0614 #define THM_BASE__INST1_SEG3                       0
0615 #define THM_BASE__INST1_SEG4                       0
0616 
0617 #define THM_BASE__INST2_SEG0                       0
0618 #define THM_BASE__INST2_SEG1                       0
0619 #define THM_BASE__INST2_SEG2                       0
0620 #define THM_BASE__INST2_SEG3                       0
0621 #define THM_BASE__INST2_SEG4                       0
0622 
0623 #define THM_BASE__INST3_SEG0                       0
0624 #define THM_BASE__INST3_SEG1                       0
0625 #define THM_BASE__INST3_SEG2                       0
0626 #define THM_BASE__INST3_SEG3                       0
0627 #define THM_BASE__INST3_SEG4                       0
0628 
0629 #define THM_BASE__INST4_SEG0                       0
0630 #define THM_BASE__INST4_SEG1                       0
0631 #define THM_BASE__INST4_SEG2                       0
0632 #define THM_BASE__INST4_SEG3                       0
0633 #define THM_BASE__INST4_SEG4                       0
0634 
0635 #define THM_BASE__INST5_SEG0                       0
0636 #define THM_BASE__INST5_SEG1                       0
0637 #define THM_BASE__INST5_SEG2                       0
0638 #define THM_BASE__INST5_SEG3                       0
0639 #define THM_BASE__INST5_SEG4                       0
0640 
0641 #define UMC0_BASE__INST0_SEG0                      0x00014000
0642 #define UMC0_BASE__INST0_SEG1                      0
0643 #define UMC0_BASE__INST0_SEG2                      0
0644 #define UMC0_BASE__INST0_SEG3                      0
0645 #define UMC0_BASE__INST0_SEG4                      0
0646 
0647 #define UMC0_BASE__INST1_SEG0                      0
0648 #define UMC0_BASE__INST1_SEG1                      0
0649 #define UMC0_BASE__INST1_SEG2                      0
0650 #define UMC0_BASE__INST1_SEG3                      0
0651 #define UMC0_BASE__INST1_SEG4                      0
0652 
0653 #define UMC0_BASE__INST2_SEG0                      0
0654 #define UMC0_BASE__INST2_SEG1                      0
0655 #define UMC0_BASE__INST2_SEG2                      0
0656 #define UMC0_BASE__INST2_SEG3                      0
0657 #define UMC0_BASE__INST2_SEG4                      0
0658 
0659 #define UMC0_BASE__INST3_SEG0                      0
0660 #define UMC0_BASE__INST3_SEG1                      0
0661 #define UMC0_BASE__INST3_SEG2                      0
0662 #define UMC0_BASE__INST3_SEG3                      0
0663 #define UMC0_BASE__INST3_SEG4                      0
0664 
0665 #define UMC0_BASE__INST4_SEG0                      0
0666 #define UMC0_BASE__INST4_SEG1                      0
0667 #define UMC0_BASE__INST4_SEG2                      0
0668 #define UMC0_BASE__INST4_SEG3                      0
0669 #define UMC0_BASE__INST4_SEG4                      0
0670 
0671 #define UMC0_BASE__INST5_SEG0                      0
0672 #define UMC0_BASE__INST5_SEG1                      0
0673 #define UMC0_BASE__INST5_SEG2                      0
0674 #define UMC0_BASE__INST5_SEG3                      0
0675 #define UMC0_BASE__INST5_SEG4                      0
0676 
0677 #define UVD0_BASE__INST0_SEG0                      0x00007800
0678 #define UVD0_BASE__INST0_SEG1                      0x00007E00
0679 #define UVD0_BASE__INST0_SEG2                      0
0680 #define UVD0_BASE__INST0_SEG3                      0
0681 #define UVD0_BASE__INST0_SEG4                      0
0682 
0683 #define UVD0_BASE__INST1_SEG0                      0
0684 #define UVD0_BASE__INST1_SEG1                      0
0685 #define UVD0_BASE__INST1_SEG2                      0
0686 #define UVD0_BASE__INST1_SEG3                      0
0687 #define UVD0_BASE__INST1_SEG4                      0
0688 
0689 #define UVD0_BASE__INST2_SEG0                      0
0690 #define UVD0_BASE__INST2_SEG1                      0
0691 #define UVD0_BASE__INST2_SEG2                      0
0692 #define UVD0_BASE__INST2_SEG3                      0
0693 #define UVD0_BASE__INST2_SEG4                      0
0694 
0695 #define UVD0_BASE__INST3_SEG0                      0
0696 #define UVD0_BASE__INST3_SEG1                      0
0697 #define UVD0_BASE__INST3_SEG2                      0
0698 #define UVD0_BASE__INST3_SEG3                      0
0699 #define UVD0_BASE__INST3_SEG4                      0
0700 
0701 #define UVD0_BASE__INST4_SEG0                      0
0702 #define UVD0_BASE__INST4_SEG1                      0
0703 #define UVD0_BASE__INST4_SEG2                      0
0704 #define UVD0_BASE__INST4_SEG3                      0
0705 #define UVD0_BASE__INST4_SEG4                      0
0706 
0707 #define UVD0_BASE__INST5_SEG0                      0
0708 #define UVD0_BASE__INST5_SEG1                      0
0709 #define UVD0_BASE__INST5_SEG2                      0
0710 #define UVD0_BASE__INST5_SEG3                      0
0711 #define UVD0_BASE__INST5_SEG4                      0
0712 
0713 #endif
0714
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