amd/include/cgs_common.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  *
0023  */
0024 #ifndef _CGS_COMMON_H
0025 #define _CGS_COMMON_H
0026
0027 #include "amd_shared.h"
0028
0029 struct cgs_device;
0030
0031 /**
0032  * enum cgs_ind_reg - Indirect register spaces
0033  */
0034 enum cgs_ind_reg {
0035     CGS_IND_REG__PCIE,
0036     CGS_IND_REG__SMC,
0037     CGS_IND_REG__UVD_CTX,
0038     CGS_IND_REG__DIDT,
0039     CGS_IND_REG_GC_CAC,
0040     CGS_IND_REG_SE_CAC,
0041     CGS_IND_REG__AUDIO_ENDPT
0042 };
0043
0044 /*
0045  * enum cgs_ucode_id - Firmware types for different IPs
0046  */
0047 enum cgs_ucode_id {
0048     CGS_UCODE_ID_SMU = 0,
0049     CGS_UCODE_ID_SMU_SK,
0050     CGS_UCODE_ID_SDMA0,
0051     CGS_UCODE_ID_SDMA1,
0052     CGS_UCODE_ID_CP_CE,
0053     CGS_UCODE_ID_CP_PFP,
0054     CGS_UCODE_ID_CP_ME,
0055     CGS_UCODE_ID_CP_MEC,
0056     CGS_UCODE_ID_CP_MEC_JT1,
0057     CGS_UCODE_ID_CP_MEC_JT2,
0058     CGS_UCODE_ID_GMCON_RENG,
0059     CGS_UCODE_ID_RLC_G,
0060     CGS_UCODE_ID_STORAGE,
0061     CGS_UCODE_ID_MAXIMUM,
0062 };
0063
0064 /**
0065  * struct cgs_firmware_info - Firmware information
0066  */
0067 struct cgs_firmware_info {
0068     uint16_t        version;
0069     uint16_t        fw_version;
0070     uint16_t        feature_version;
0071     uint32_t        image_size;
0072     uint64_t        mc_addr;
0073
0074     /* only for smc firmware */
0075     uint32_t        ucode_start_address;
0076
0077     void            *kptr;
0078     bool            is_kicker;
0079 };
0080
0081 typedef unsigned long cgs_handle_t;
0082
0083 /**
0084  * cgs_read_register() - Read an MMIO register
0085  * @cgs_device: opaque device handle
0086  * @offset: register offset
0087  *
0088  * Return:  register value
0089  */
0090 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
0091
0092 /**
0093  * cgs_write_register() - Write an MMIO register
0094  * @cgs_device: opaque device handle
0095  * @offset: register offset
0096  * @value:  register value
0097  */
0098 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
0099                      uint32_t value);
0100
0101 /**
0102  * cgs_read_ind_register() - Read an indirect register
0103  * @cgs_device: opaque device handle
0104  * @offset: register offset
0105  *
0106  * Return:  register value
0107  */
0108 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
0109                         unsigned index);
0110
0111 /**
0112  * cgs_write_ind_register() - Write an indirect register
0113  * @cgs_device: opaque device handle
0114  * @offset: register offset
0115  * @value:  register value
0116  */
0117 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
0118                      unsigned index, uint32_t value);
0119
0120 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
0121 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
0122
0123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val)          \
0124     (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) |           \
0125      (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
0126
0127 #define CGS_REG_GET_FIELD(value, reg, field)                \
0128     (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
0129
0130 #define CGS_WREG32_FIELD(device, reg, field, val)   \
0131     cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
0132
0133 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val)    \
0134     cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
0135
0136 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
0137                      enum cgs_ucode_id type,
0138                      struct cgs_firmware_info *info);
0139
0140 struct cgs_ops {
0141     /* MMIO access */
0142     cgs_read_register_t read_register;
0143     cgs_write_register_t write_register;
0144     cgs_read_ind_register_t read_ind_register;
0145     cgs_write_ind_register_t write_ind_register;
0146     /* Firmware Info */
0147     cgs_get_firmware_info get_firmware_info;
0148 };
0149
0150 struct cgs_os_ops; /* To be define in OS-specific CGS header */
0151
0152 struct cgs_device
0153 {
0154     const struct cgs_ops *ops;
0155     /* to be embedded at the start of driver private structure */
0156 };
0157
0158 /* Convenience macros that make CGS indirect function calls look like
0159  * normal function calls */
0160 #define CGS_CALL(func,dev,...) \
0161     (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
0162 #define CGS_OS_CALL(func,dev,...) \
0163     (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
0164
0165 #define cgs_read_register(dev,offset)       \
0166     CGS_CALL(read_register,dev,offset)
0167 #define cgs_write_register(dev,offset,value)        \
0168     CGS_CALL(write_register,dev,offset,value)
0169 #define cgs_read_ind_register(dev,space,index)      \
0170     CGS_CALL(read_ind_register,dev,space,index)
0171 #define cgs_write_ind_register(dev,space,index,value)       \
0172     CGS_CALL(write_ind_register,dev,space,index,value)
0173
0174 #define cgs_get_firmware_info(dev, type, info)  \
0175     CGS_CALL(get_firmware_info, dev, type, info)
0176
0177 #endif /* _CGS_COMMON_H */