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0001 /*
0002  * Copyright (C) 2020  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _beige_goby_ip_offset_HEADER
0022 #define _beige_goby_ip_offset_HEADER
0023 
0024 
0025 #define MAX_INSTANCE                                        7
0026 #define MAX_SEGMENT                                         6
0027 
0028 
0029 struct IP_BASE_INSTANCE
0030 {
0031     unsigned int segment[MAX_SEGMENT];
0032 };
0033 
0034 struct IP_BASE
0035 {
0036     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0037 };
0038 
0039 
0040 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0, 0 } },
0046                                         { { 0, 0, 0, 0, 0, 0 } } } };
0047 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
0048                                         { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
0049                                         { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
0050                                         { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
0051                                         { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
0052                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
0053                                         { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
0054 static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
0055                                         { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0, 0 } } } };
0061 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } },
0063                                         { { 0, 0, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0, 0 } } } };
0068 static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0, 0 } } } };
0075 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } },
0081                                         { { 0, 0, 0, 0, 0, 0 } } } };
0082 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0, 0 } } } };
0089 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0, 0 } } } };
0096 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0, 0 } } } };
0103 static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } },
0109                                         { { 0, 0, 0, 0, 0, 0 } } } };
0110 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0, 0 } },
0112                                         { { 0, 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0, 0 } } } };
0117 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } },
0119                                         { { 0, 0, 0, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } },
0123                                         { { 0, 0, 0, 0, 0, 0 } } } };
0124 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0, 0 } } } };
0131 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0, 0 } } } };
0138 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
0139                                         { { 0, 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0, 0 } },
0144                                         { { 0, 0, 0, 0, 0, 0 } } } };
0145 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0, 0 } },
0151                                         { { 0, 0, 0, 0, 0, 0 } } } };
0152 static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
0153                                         { { 0, 0, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0, 0 } },
0158                                         { { 0, 0, 0, 0, 0, 0 } } } };
0159 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0, 0 } },
0165                                         { { 0, 0, 0, 0, 0, 0 } } } };
0166 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0, 0 } },
0168                                         { { 0, 0, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0, 0 } },
0172                                         { { 0, 0, 0, 0, 0, 0 } } } };
0173 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0, 0 } },
0175                                         { { 0, 0, 0, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0, 0 } },
0179                                         { { 0, 0, 0, 0, 0, 0 } } } };
0180 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
0181                                         { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
0182                                         { { 0, 0, 0, 0, 0, 0 } },
0183                                         { { 0, 0, 0, 0, 0, 0 } },
0184                                         { { 0, 0, 0, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0, 0 } },
0186                                         { { 0, 0, 0, 0, 0, 0 } } } };
0187 static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0, 0 } },
0191                                         { { 0, 0, 0, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0, 0 } },
0193                                         { { 0, 0, 0, 0, 0, 0 } } } };
0194 
0195 
0196 #define ATHUB_BASE__INST0_SEG0                     0x00000C00
0197 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0198 #define ATHUB_BASE__INST0_SEG2                     0
0199 #define ATHUB_BASE__INST0_SEG3                     0
0200 #define ATHUB_BASE__INST0_SEG4                     0
0201 #define ATHUB_BASE__INST0_SEG5                     0
0202 
0203 #define ATHUB_BASE__INST1_SEG0                     0
0204 #define ATHUB_BASE__INST1_SEG1                     0
0205 #define ATHUB_BASE__INST1_SEG2                     0
0206 #define ATHUB_BASE__INST1_SEG3                     0
0207 #define ATHUB_BASE__INST1_SEG4                     0
0208 #define ATHUB_BASE__INST1_SEG5                     0
0209 
0210 #define ATHUB_BASE__INST2_SEG0                     0
0211 #define ATHUB_BASE__INST2_SEG1                     0
0212 #define ATHUB_BASE__INST2_SEG2                     0
0213 #define ATHUB_BASE__INST2_SEG3                     0
0214 #define ATHUB_BASE__INST2_SEG4                     0
0215 #define ATHUB_BASE__INST2_SEG5                     0
0216 
0217 #define ATHUB_BASE__INST3_SEG0                     0
0218 #define ATHUB_BASE__INST3_SEG1                     0
0219 #define ATHUB_BASE__INST3_SEG2                     0
0220 #define ATHUB_BASE__INST3_SEG3                     0
0221 #define ATHUB_BASE__INST3_SEG4                     0
0222 #define ATHUB_BASE__INST3_SEG5                     0
0223 
0224 #define ATHUB_BASE__INST4_SEG0                     0
0225 #define ATHUB_BASE__INST4_SEG1                     0
0226 #define ATHUB_BASE__INST4_SEG2                     0
0227 #define ATHUB_BASE__INST4_SEG3                     0
0228 #define ATHUB_BASE__INST4_SEG4                     0
0229 #define ATHUB_BASE__INST4_SEG5                     0
0230 
0231 #define ATHUB_BASE__INST5_SEG0                     0
0232 #define ATHUB_BASE__INST5_SEG1                     0
0233 #define ATHUB_BASE__INST5_SEG2                     0
0234 #define ATHUB_BASE__INST5_SEG3                     0
0235 #define ATHUB_BASE__INST5_SEG4                     0
0236 #define ATHUB_BASE__INST5_SEG5                     0
0237 
0238 #define ATHUB_BASE__INST6_SEG0                     0
0239 #define ATHUB_BASE__INST6_SEG1                     0
0240 #define ATHUB_BASE__INST6_SEG2                     0
0241 #define ATHUB_BASE__INST6_SEG3                     0
0242 #define ATHUB_BASE__INST6_SEG4                     0
0243 #define ATHUB_BASE__INST6_SEG5                     0
0244 
0245 #define CLK_BASE__INST0_SEG0                       0x00016C00
0246 #define CLK_BASE__INST0_SEG1                       0x02401800
0247 #define CLK_BASE__INST0_SEG2                       0
0248 #define CLK_BASE__INST0_SEG3                       0
0249 #define CLK_BASE__INST0_SEG4                       0
0250 #define CLK_BASE__INST0_SEG5                       0
0251 
0252 #define CLK_BASE__INST1_SEG0                       0x00016E00
0253 #define CLK_BASE__INST1_SEG1                       0x02401C00
0254 #define CLK_BASE__INST1_SEG2                       0
0255 #define CLK_BASE__INST1_SEG3                       0
0256 #define CLK_BASE__INST1_SEG4                       0
0257 #define CLK_BASE__INST1_SEG5                       0
0258 
0259 #define CLK_BASE__INST2_SEG0                       0x00017000
0260 #define CLK_BASE__INST2_SEG1                       0x02402000
0261 #define CLK_BASE__INST2_SEG2                       0
0262 #define CLK_BASE__INST2_SEG3                       0
0263 #define CLK_BASE__INST2_SEG4                       0
0264 #define CLK_BASE__INST2_SEG5                       0
0265 
0266 #define CLK_BASE__INST3_SEG0                       0x00017200
0267 #define CLK_BASE__INST3_SEG1                       0x02402400
0268 #define CLK_BASE__INST3_SEG2                       0
0269 #define CLK_BASE__INST3_SEG3                       0
0270 #define CLK_BASE__INST3_SEG4                       0
0271 #define CLK_BASE__INST3_SEG5                       0
0272 
0273 #define CLK_BASE__INST4_SEG0                       0x0001B000
0274 #define CLK_BASE__INST4_SEG1                       0x0242D800
0275 #define CLK_BASE__INST4_SEG2                       0
0276 #define CLK_BASE__INST4_SEG3                       0
0277 #define CLK_BASE__INST4_SEG4                       0
0278 #define CLK_BASE__INST4_SEG5                       0
0279 
0280 #define CLK_BASE__INST5_SEG0                       0x0001B200
0281 #define CLK_BASE__INST5_SEG1                       0x0242DC00
0282 #define CLK_BASE__INST5_SEG2                       0
0283 #define CLK_BASE__INST5_SEG3                       0
0284 #define CLK_BASE__INST5_SEG4                       0
0285 #define CLK_BASE__INST5_SEG5                       0
0286 
0287 #define CLK_BASE__INST6_SEG0                       0x00017E00
0288 #define CLK_BASE__INST6_SEG1                       0x0240BC00
0289 #define CLK_BASE__INST6_SEG2                       0
0290 #define CLK_BASE__INST6_SEG3                       0
0291 #define CLK_BASE__INST6_SEG4                       0
0292 #define CLK_BASE__INST6_SEG5                       0
0293 
0294 #define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
0295 #define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
0296 #define DBGU_IO0_BASE__INST0_SEG2                  0
0297 #define DBGU_IO0_BASE__INST0_SEG3                  0
0298 #define DBGU_IO0_BASE__INST0_SEG4                  0
0299 #define DBGU_IO0_BASE__INST0_SEG5                  0
0300 
0301 #define DBGU_IO0_BASE__INST1_SEG0                  0x00000260
0302 #define DBGU_IO0_BASE__INST1_SEG1                  0x02413C00
0303 #define DBGU_IO0_BASE__INST1_SEG2                  0
0304 #define DBGU_IO0_BASE__INST1_SEG3                  0
0305 #define DBGU_IO0_BASE__INST1_SEG4                  0
0306 #define DBGU_IO0_BASE__INST1_SEG5                  0
0307 
0308 #define DBGU_IO0_BASE__INST2_SEG0                  0
0309 #define DBGU_IO0_BASE__INST2_SEG1                  0
0310 #define DBGU_IO0_BASE__INST2_SEG2                  0
0311 #define DBGU_IO0_BASE__INST2_SEG3                  0
0312 #define DBGU_IO0_BASE__INST2_SEG4                  0
0313 #define DBGU_IO0_BASE__INST2_SEG5                  0
0314 
0315 #define DBGU_IO0_BASE__INST3_SEG0                  0
0316 #define DBGU_IO0_BASE__INST3_SEG1                  0
0317 #define DBGU_IO0_BASE__INST3_SEG2                  0
0318 #define DBGU_IO0_BASE__INST3_SEG3                  0
0319 #define DBGU_IO0_BASE__INST3_SEG4                  0
0320 #define DBGU_IO0_BASE__INST3_SEG5                  0
0321 
0322 #define DBGU_IO0_BASE__INST4_SEG0                  0
0323 #define DBGU_IO0_BASE__INST4_SEG1                  0
0324 #define DBGU_IO0_BASE__INST4_SEG2                  0
0325 #define DBGU_IO0_BASE__INST4_SEG3                  0
0326 #define DBGU_IO0_BASE__INST4_SEG4                  0
0327 #define DBGU_IO0_BASE__INST4_SEG5                  0
0328 
0329 #define DBGU_IO0_BASE__INST5_SEG0                  0
0330 #define DBGU_IO0_BASE__INST5_SEG1                  0
0331 #define DBGU_IO0_BASE__INST5_SEG2                  0
0332 #define DBGU_IO0_BASE__INST5_SEG3                  0
0333 #define DBGU_IO0_BASE__INST5_SEG4                  0
0334 #define DBGU_IO0_BASE__INST5_SEG5                  0
0335 
0336 #define DBGU_IO0_BASE__INST6_SEG0                  0
0337 #define DBGU_IO0_BASE__INST6_SEG1                  0
0338 #define DBGU_IO0_BASE__INST6_SEG2                  0
0339 #define DBGU_IO0_BASE__INST6_SEG3                  0
0340 #define DBGU_IO0_BASE__INST6_SEG4                  0
0341 #define DBGU_IO0_BASE__INST6_SEG5                  0
0342 
0343 #define DF_BASE__INST0_SEG0                        0x00007000
0344 #define DF_BASE__INST0_SEG1                        0x0240B800
0345 #define DF_BASE__INST0_SEG2                        0
0346 #define DF_BASE__INST0_SEG3                        0
0347 #define DF_BASE__INST0_SEG4                        0
0348 #define DF_BASE__INST0_SEG5                        0
0349 
0350 #define DF_BASE__INST1_SEG0                        0
0351 #define DF_BASE__INST1_SEG1                        0
0352 #define DF_BASE__INST1_SEG2                        0
0353 #define DF_BASE__INST1_SEG3                        0
0354 #define DF_BASE__INST1_SEG4                        0
0355 #define DF_BASE__INST1_SEG5                        0
0356 
0357 #define DF_BASE__INST2_SEG0                        0
0358 #define DF_BASE__INST2_SEG1                        0
0359 #define DF_BASE__INST2_SEG2                        0
0360 #define DF_BASE__INST2_SEG3                        0
0361 #define DF_BASE__INST2_SEG4                        0
0362 #define DF_BASE__INST2_SEG5                        0
0363 
0364 #define DF_BASE__INST3_SEG0                        0
0365 #define DF_BASE__INST3_SEG1                        0
0366 #define DF_BASE__INST3_SEG2                        0
0367 #define DF_BASE__INST3_SEG3                        0
0368 #define DF_BASE__INST3_SEG4                        0
0369 #define DF_BASE__INST3_SEG5                        0
0370 
0371 #define DF_BASE__INST4_SEG0                        0
0372 #define DF_BASE__INST4_SEG1                        0
0373 #define DF_BASE__INST4_SEG2                        0
0374 #define DF_BASE__INST4_SEG3                        0
0375 #define DF_BASE__INST4_SEG4                        0
0376 #define DF_BASE__INST4_SEG5                        0
0377 
0378 #define DF_BASE__INST5_SEG0                        0
0379 #define DF_BASE__INST5_SEG1                        0
0380 #define DF_BASE__INST5_SEG2                        0
0381 #define DF_BASE__INST5_SEG3                        0
0382 #define DF_BASE__INST5_SEG4                        0
0383 #define DF_BASE__INST5_SEG5                        0
0384 
0385 #define DF_BASE__INST6_SEG0                        0
0386 #define DF_BASE__INST6_SEG1                        0
0387 #define DF_BASE__INST6_SEG2                        0
0388 #define DF_BASE__INST6_SEG3                        0
0389 #define DF_BASE__INST6_SEG4                        0
0390 #define DF_BASE__INST6_SEG5                        0
0391 
0392 #define DIO_BASE__INST0_SEG0                       0x02404000
0393 #define DIO_BASE__INST0_SEG1                       0
0394 #define DIO_BASE__INST0_SEG2                       0
0395 #define DIO_BASE__INST0_SEG3                       0
0396 #define DIO_BASE__INST0_SEG4                       0
0397 #define DIO_BASE__INST0_SEG5                       0
0398 
0399 #define DIO_BASE__INST1_SEG0                       0
0400 #define DIO_BASE__INST1_SEG1                       0
0401 #define DIO_BASE__INST1_SEG2                       0
0402 #define DIO_BASE__INST1_SEG3                       0
0403 #define DIO_BASE__INST1_SEG4                       0
0404 #define DIO_BASE__INST1_SEG5                       0
0405 
0406 #define DIO_BASE__INST2_SEG0                       0
0407 #define DIO_BASE__INST2_SEG1                       0
0408 #define DIO_BASE__INST2_SEG2                       0
0409 #define DIO_BASE__INST2_SEG3                       0
0410 #define DIO_BASE__INST2_SEG4                       0
0411 #define DIO_BASE__INST2_SEG5                       0
0412 
0413 #define DIO_BASE__INST3_SEG0                       0
0414 #define DIO_BASE__INST3_SEG1                       0
0415 #define DIO_BASE__INST3_SEG2                       0
0416 #define DIO_BASE__INST3_SEG3                       0
0417 #define DIO_BASE__INST3_SEG4                       0
0418 #define DIO_BASE__INST3_SEG5                       0
0419 
0420 #define DIO_BASE__INST4_SEG0                       0
0421 #define DIO_BASE__INST4_SEG1                       0
0422 #define DIO_BASE__INST4_SEG2                       0
0423 #define DIO_BASE__INST4_SEG3                       0
0424 #define DIO_BASE__INST4_SEG4                       0
0425 #define DIO_BASE__INST4_SEG5                       0
0426 
0427 #define DIO_BASE__INST5_SEG0                       0
0428 #define DIO_BASE__INST5_SEG1                       0
0429 #define DIO_BASE__INST5_SEG2                       0
0430 #define DIO_BASE__INST5_SEG3                       0
0431 #define DIO_BASE__INST5_SEG4                       0
0432 #define DIO_BASE__INST5_SEG5                       0
0433 
0434 #define DIO_BASE__INST6_SEG0                       0
0435 #define DIO_BASE__INST6_SEG1                       0
0436 #define DIO_BASE__INST6_SEG2                       0
0437 #define DIO_BASE__INST6_SEG3                       0
0438 #define DIO_BASE__INST6_SEG4                       0
0439 #define DIO_BASE__INST6_SEG5                       0
0440 
0441 #define DCN_BASE__INST0_SEG0                       0x00000012
0442 #define DCN_BASE__INST0_SEG1                       0x000000C0
0443 #define DCN_BASE__INST0_SEG2                       0x000034C0
0444 #define DCN_BASE__INST0_SEG3                       0x00009000
0445 #define DCN_BASE__INST0_SEG4                       0x02403C00
0446 #define DCN_BASE__INST0_SEG5                       0
0447 
0448 #define DCN_BASE__INST1_SEG0                       0
0449 #define DCN_BASE__INST1_SEG1                       0
0450 #define DCN_BASE__INST1_SEG2                       0
0451 #define DCN_BASE__INST1_SEG3                       0
0452 #define DCN_BASE__INST1_SEG4                       0
0453 #define DCN_BASE__INST1_SEG5                       0
0454 
0455 #define DCN_BASE__INST2_SEG0                       0
0456 #define DCN_BASE__INST2_SEG1                       0
0457 #define DCN_BASE__INST2_SEG2                       0
0458 #define DCN_BASE__INST2_SEG3                       0
0459 #define DCN_BASE__INST2_SEG4                       0
0460 #define DCN_BASE__INST2_SEG5                       0
0461 
0462 #define DCN_BASE__INST3_SEG0                       0
0463 #define DCN_BASE__INST3_SEG1                       0
0464 #define DCN_BASE__INST3_SEG2                       0
0465 #define DCN_BASE__INST3_SEG3                       0
0466 #define DCN_BASE__INST3_SEG4                       0
0467 #define DCN_BASE__INST3_SEG5                       0
0468 
0469 #define DCN_BASE__INST4_SEG0                       0
0470 #define DCN_BASE__INST4_SEG1                       0
0471 #define DCN_BASE__INST4_SEG2                       0
0472 #define DCN_BASE__INST4_SEG3                       0
0473 #define DCN_BASE__INST4_SEG4                       0
0474 #define DCN_BASE__INST4_SEG5                       0
0475 
0476 #define DCN_BASE__INST5_SEG0                       0
0477 #define DCN_BASE__INST5_SEG1                       0
0478 #define DCN_BASE__INST5_SEG2                       0
0479 #define DCN_BASE__INST5_SEG3                       0
0480 #define DCN_BASE__INST5_SEG4                       0
0481 #define DCN_BASE__INST5_SEG5                       0
0482 
0483 #define DCN_BASE__INST6_SEG0                       0
0484 #define DCN_BASE__INST6_SEG1                       0
0485 #define DCN_BASE__INST6_SEG2                       0
0486 #define DCN_BASE__INST6_SEG3                       0
0487 #define DCN_BASE__INST6_SEG4                       0
0488 #define DCN_BASE__INST6_SEG5                       0
0489 
0490 #define DPCS_BASE__INST0_SEG0                      0x00000012
0491 #define DPCS_BASE__INST0_SEG1                      0x000000C0
0492 #define DPCS_BASE__INST0_SEG2                      0x000034C0
0493 #define DPCS_BASE__INST0_SEG3                      0x00009000
0494 #define DPCS_BASE__INST0_SEG4                      0x02403C00
0495 #define DPCS_BASE__INST0_SEG5                      0
0496 
0497 #define DPCS_BASE__INST1_SEG0                      0
0498 #define DPCS_BASE__INST1_SEG1                      0
0499 #define DPCS_BASE__INST1_SEG2                      0
0500 #define DPCS_BASE__INST1_SEG3                      0
0501 #define DPCS_BASE__INST1_SEG4                      0
0502 #define DPCS_BASE__INST1_SEG5                      0
0503 
0504 #define DPCS_BASE__INST2_SEG0                      0
0505 #define DPCS_BASE__INST2_SEG1                      0
0506 #define DPCS_BASE__INST2_SEG2                      0
0507 #define DPCS_BASE__INST2_SEG3                      0
0508 #define DPCS_BASE__INST2_SEG4                      0
0509 #define DPCS_BASE__INST2_SEG5                      0
0510 
0511 #define DPCS_BASE__INST3_SEG0                      0
0512 #define DPCS_BASE__INST3_SEG1                      0
0513 #define DPCS_BASE__INST3_SEG2                      0
0514 #define DPCS_BASE__INST3_SEG3                      0
0515 #define DPCS_BASE__INST3_SEG4                      0
0516 #define DPCS_BASE__INST3_SEG5                      0
0517 
0518 #define DPCS_BASE__INST4_SEG0                      0
0519 #define DPCS_BASE__INST4_SEG1                      0
0520 #define DPCS_BASE__INST4_SEG2                      0
0521 #define DPCS_BASE__INST4_SEG3                      0
0522 #define DPCS_BASE__INST4_SEG4                      0
0523 #define DPCS_BASE__INST4_SEG5                      0
0524 
0525 #define DPCS_BASE__INST5_SEG0                      0
0526 #define DPCS_BASE__INST5_SEG1                      0
0527 #define DPCS_BASE__INST5_SEG2                      0
0528 #define DPCS_BASE__INST5_SEG3                      0
0529 #define DPCS_BASE__INST5_SEG4                      0
0530 #define DPCS_BASE__INST5_SEG5                      0
0531 
0532 #define DPCS_BASE__INST6_SEG0                      0
0533 #define DPCS_BASE__INST6_SEG1                      0
0534 #define DPCS_BASE__INST6_SEG2                      0
0535 #define DPCS_BASE__INST6_SEG3                      0
0536 #define DPCS_BASE__INST6_SEG4                      0
0537 #define DPCS_BASE__INST6_SEG5                      0
0538 
0539 #define FUSE_BASE__INST0_SEG0                      0x00017400
0540 #define FUSE_BASE__INST0_SEG1                      0x02401400
0541 #define FUSE_BASE__INST0_SEG2                      0
0542 #define FUSE_BASE__INST0_SEG3                      0
0543 #define FUSE_BASE__INST0_SEG4                      0
0544 #define FUSE_BASE__INST0_SEG5                      0
0545 
0546 #define FUSE_BASE__INST1_SEG0                      0
0547 #define FUSE_BASE__INST1_SEG1                      0
0548 #define FUSE_BASE__INST1_SEG2                      0
0549 #define FUSE_BASE__INST1_SEG3                      0
0550 #define FUSE_BASE__INST1_SEG4                      0
0551 #define FUSE_BASE__INST1_SEG5                      0
0552 
0553 #define FUSE_BASE__INST2_SEG0                      0
0554 #define FUSE_BASE__INST2_SEG1                      0
0555 #define FUSE_BASE__INST2_SEG2                      0
0556 #define FUSE_BASE__INST2_SEG3                      0
0557 #define FUSE_BASE__INST2_SEG4                      0
0558 #define FUSE_BASE__INST2_SEG5                      0
0559 
0560 #define FUSE_BASE__INST3_SEG0                      0
0561 #define FUSE_BASE__INST3_SEG1                      0
0562 #define FUSE_BASE__INST3_SEG2                      0
0563 #define FUSE_BASE__INST3_SEG3                      0
0564 #define FUSE_BASE__INST3_SEG4                      0
0565 #define FUSE_BASE__INST3_SEG5                      0
0566 
0567 #define FUSE_BASE__INST4_SEG0                      0
0568 #define FUSE_BASE__INST4_SEG1                      0
0569 #define FUSE_BASE__INST4_SEG2                      0
0570 #define FUSE_BASE__INST4_SEG3                      0
0571 #define FUSE_BASE__INST4_SEG4                      0
0572 #define FUSE_BASE__INST4_SEG5                      0
0573 
0574 #define FUSE_BASE__INST5_SEG0                      0
0575 #define FUSE_BASE__INST5_SEG1                      0
0576 #define FUSE_BASE__INST5_SEG2                      0
0577 #define FUSE_BASE__INST5_SEG3                      0
0578 #define FUSE_BASE__INST5_SEG4                      0
0579 #define FUSE_BASE__INST5_SEG5                      0
0580 
0581 #define FUSE_BASE__INST6_SEG0                      0
0582 #define FUSE_BASE__INST6_SEG1                      0
0583 #define FUSE_BASE__INST6_SEG2                      0
0584 #define FUSE_BASE__INST6_SEG3                      0
0585 #define FUSE_BASE__INST6_SEG4                      0
0586 #define FUSE_BASE__INST6_SEG5                      0
0587 
0588 #define GC_BASE__INST0_SEG0                        0x00001260
0589 #define GC_BASE__INST0_SEG1                        0x0000A000
0590 #define GC_BASE__INST0_SEG2                        0x0001C000
0591 #define GC_BASE__INST0_SEG3                        0x02402C00
0592 #define GC_BASE__INST0_SEG4                        0
0593 #define GC_BASE__INST0_SEG5                        0
0594 
0595 #define GC_BASE__INST1_SEG0                        0
0596 #define GC_BASE__INST1_SEG1                        0
0597 #define GC_BASE__INST1_SEG2                        0
0598 #define GC_BASE__INST1_SEG3                        0
0599 #define GC_BASE__INST1_SEG4                        0
0600 #define GC_BASE__INST1_SEG5                        0
0601 
0602 #define GC_BASE__INST2_SEG0                        0
0603 #define GC_BASE__INST2_SEG1                        0
0604 #define GC_BASE__INST2_SEG2                        0
0605 #define GC_BASE__INST2_SEG3                        0
0606 #define GC_BASE__INST2_SEG4                        0
0607 #define GC_BASE__INST2_SEG5                        0
0608 
0609 #define GC_BASE__INST3_SEG0                        0
0610 #define GC_BASE__INST3_SEG1                        0
0611 #define GC_BASE__INST3_SEG2                        0
0612 #define GC_BASE__INST3_SEG3                        0
0613 #define GC_BASE__INST3_SEG4                        0
0614 #define GC_BASE__INST3_SEG5                        0
0615 
0616 #define GC_BASE__INST4_SEG0                        0
0617 #define GC_BASE__INST4_SEG1                        0
0618 #define GC_BASE__INST4_SEG2                        0
0619 #define GC_BASE__INST4_SEG3                        0
0620 #define GC_BASE__INST4_SEG4                        0
0621 #define GC_BASE__INST4_SEG5                        0
0622 
0623 #define GC_BASE__INST5_SEG0                        0
0624 #define GC_BASE__INST5_SEG1                        0
0625 #define GC_BASE__INST5_SEG2                        0
0626 #define GC_BASE__INST5_SEG3                        0
0627 #define GC_BASE__INST5_SEG4                        0
0628 #define GC_BASE__INST5_SEG5                        0
0629 
0630 #define GC_BASE__INST6_SEG0                        0
0631 #define GC_BASE__INST6_SEG1                        0
0632 #define GC_BASE__INST6_SEG2                        0
0633 #define GC_BASE__INST6_SEG3                        0
0634 #define GC_BASE__INST6_SEG4                        0
0635 #define GC_BASE__INST6_SEG5                        0
0636 
0637 #define HDA_BASE__INST0_SEG0                       0x004C0000
0638 #define HDA_BASE__INST0_SEG1                       0x02404800
0639 #define HDA_BASE__INST0_SEG2                       0
0640 #define HDA_BASE__INST0_SEG3                       0
0641 #define HDA_BASE__INST0_SEG4                       0
0642 #define HDA_BASE__INST0_SEG5                       0
0643 
0644 #define HDA_BASE__INST1_SEG0                       0
0645 #define HDA_BASE__INST1_SEG1                       0
0646 #define HDA_BASE__INST1_SEG2                       0
0647 #define HDA_BASE__INST1_SEG3                       0
0648 #define HDA_BASE__INST1_SEG4                       0
0649 #define HDA_BASE__INST1_SEG5                       0
0650 
0651 #define HDA_BASE__INST2_SEG0                       0
0652 #define HDA_BASE__INST2_SEG1                       0
0653 #define HDA_BASE__INST2_SEG2                       0
0654 #define HDA_BASE__INST2_SEG3                       0
0655 #define HDA_BASE__INST2_SEG4                       0
0656 #define HDA_BASE__INST2_SEG5                       0
0657 
0658 #define HDA_BASE__INST3_SEG0                       0
0659 #define HDA_BASE__INST3_SEG1                       0
0660 #define HDA_BASE__INST3_SEG2                       0
0661 #define HDA_BASE__INST3_SEG3                       0
0662 #define HDA_BASE__INST3_SEG4                       0
0663 #define HDA_BASE__INST3_SEG5                       0
0664 
0665 #define HDA_BASE__INST4_SEG0                       0
0666 #define HDA_BASE__INST4_SEG1                       0
0667 #define HDA_BASE__INST4_SEG2                       0
0668 #define HDA_BASE__INST4_SEG3                       0
0669 #define HDA_BASE__INST4_SEG4                       0
0670 #define HDA_BASE__INST4_SEG5                       0
0671 
0672 #define HDA_BASE__INST5_SEG0                       0
0673 #define HDA_BASE__INST5_SEG1                       0
0674 #define HDA_BASE__INST5_SEG2                       0
0675 #define HDA_BASE__INST5_SEG3                       0
0676 #define HDA_BASE__INST5_SEG4                       0
0677 #define HDA_BASE__INST5_SEG5                       0
0678 
0679 #define HDA_BASE__INST6_SEG0                       0
0680 #define HDA_BASE__INST6_SEG1                       0
0681 #define HDA_BASE__INST6_SEG2                       0
0682 #define HDA_BASE__INST6_SEG3                       0
0683 #define HDA_BASE__INST6_SEG4                       0
0684 #define HDA_BASE__INST6_SEG5                       0
0685 
0686 #define HDP_BASE__INST0_SEG0                       0x00000F20
0687 #define HDP_BASE__INST0_SEG1                       0x0240A400
0688 #define HDP_BASE__INST0_SEG2                       0
0689 #define HDP_BASE__INST0_SEG3                       0
0690 #define HDP_BASE__INST0_SEG4                       0
0691 #define HDP_BASE__INST0_SEG5                       0
0692 
0693 #define HDP_BASE__INST1_SEG0                       0
0694 #define HDP_BASE__INST1_SEG1                       0
0695 #define HDP_BASE__INST1_SEG2                       0
0696 #define HDP_BASE__INST1_SEG3                       0
0697 #define HDP_BASE__INST1_SEG4                       0
0698 #define HDP_BASE__INST1_SEG5                       0
0699 
0700 #define HDP_BASE__INST2_SEG0                       0
0701 #define HDP_BASE__INST2_SEG1                       0
0702 #define HDP_BASE__INST2_SEG2                       0
0703 #define HDP_BASE__INST2_SEG3                       0
0704 #define HDP_BASE__INST2_SEG4                       0
0705 #define HDP_BASE__INST2_SEG5                       0
0706 
0707 #define HDP_BASE__INST3_SEG0                       0
0708 #define HDP_BASE__INST3_SEG1                       0
0709 #define HDP_BASE__INST3_SEG2                       0
0710 #define HDP_BASE__INST3_SEG3                       0
0711 #define HDP_BASE__INST3_SEG4                       0
0712 #define HDP_BASE__INST3_SEG5                       0
0713 
0714 #define HDP_BASE__INST4_SEG0                       0
0715 #define HDP_BASE__INST4_SEG1                       0
0716 #define HDP_BASE__INST4_SEG2                       0
0717 #define HDP_BASE__INST4_SEG3                       0
0718 #define HDP_BASE__INST4_SEG4                       0
0719 #define HDP_BASE__INST4_SEG5                       0
0720 
0721 #define HDP_BASE__INST5_SEG0                       0
0722 #define HDP_BASE__INST5_SEG1                       0
0723 #define HDP_BASE__INST5_SEG2                       0
0724 #define HDP_BASE__INST5_SEG3                       0
0725 #define HDP_BASE__INST5_SEG4                       0
0726 #define HDP_BASE__INST5_SEG5                       0
0727 
0728 #define HDP_BASE__INST6_SEG0                       0
0729 #define HDP_BASE__INST6_SEG1                       0
0730 #define HDP_BASE__INST6_SEG2                       0
0731 #define HDP_BASE__INST6_SEG3                       0
0732 #define HDP_BASE__INST6_SEG4                       0
0733 #define HDP_BASE__INST6_SEG5                       0
0734 
0735 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0736 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0737 #define MMHUB_BASE__INST0_SEG2                     0
0738 #define MMHUB_BASE__INST0_SEG3                     0
0739 #define MMHUB_BASE__INST0_SEG4                     0
0740 #define MMHUB_BASE__INST0_SEG5                     0
0741 
0742 #define MMHUB_BASE__INST1_SEG0                     0
0743 #define MMHUB_BASE__INST1_SEG1                     0
0744 #define MMHUB_BASE__INST1_SEG2                     0
0745 #define MMHUB_BASE__INST1_SEG3                     0
0746 #define MMHUB_BASE__INST1_SEG4                     0
0747 #define MMHUB_BASE__INST1_SEG5                     0
0748 
0749 #define MMHUB_BASE__INST2_SEG0                     0
0750 #define MMHUB_BASE__INST2_SEG1                     0
0751 #define MMHUB_BASE__INST2_SEG2                     0
0752 #define MMHUB_BASE__INST2_SEG3                     0
0753 #define MMHUB_BASE__INST2_SEG4                     0
0754 #define MMHUB_BASE__INST2_SEG5                     0
0755 
0756 #define MMHUB_BASE__INST3_SEG0                     0
0757 #define MMHUB_BASE__INST3_SEG1                     0
0758 #define MMHUB_BASE__INST3_SEG2                     0
0759 #define MMHUB_BASE__INST3_SEG3                     0
0760 #define MMHUB_BASE__INST3_SEG4                     0
0761 #define MMHUB_BASE__INST3_SEG5                     0
0762 
0763 #define MMHUB_BASE__INST4_SEG0                     0
0764 #define MMHUB_BASE__INST4_SEG1                     0
0765 #define MMHUB_BASE__INST4_SEG2                     0
0766 #define MMHUB_BASE__INST4_SEG3                     0
0767 #define MMHUB_BASE__INST4_SEG4                     0
0768 #define MMHUB_BASE__INST4_SEG5                     0
0769 
0770 #define MMHUB_BASE__INST5_SEG0                     0
0771 #define MMHUB_BASE__INST5_SEG1                     0
0772 #define MMHUB_BASE__INST5_SEG2                     0
0773 #define MMHUB_BASE__INST5_SEG3                     0
0774 #define MMHUB_BASE__INST5_SEG4                     0
0775 #define MMHUB_BASE__INST5_SEG5                     0
0776 
0777 #define MMHUB_BASE__INST6_SEG0                     0
0778 #define MMHUB_BASE__INST6_SEG1                     0
0779 #define MMHUB_BASE__INST6_SEG2                     0
0780 #define MMHUB_BASE__INST6_SEG3                     0
0781 #define MMHUB_BASE__INST6_SEG4                     0
0782 #define MMHUB_BASE__INST6_SEG5                     0
0783 
0784 #define MP0_BASE__INST0_SEG0                       0x00016000
0785 #define MP0_BASE__INST0_SEG1                       0x00DC0000
0786 #define MP0_BASE__INST0_SEG2                       0x00E00000
0787 #define MP0_BASE__INST0_SEG3                       0x00E40000
0788 #define MP0_BASE__INST0_SEG4                       0x0243FC00
0789 #define MP0_BASE__INST0_SEG5                       0
0790 
0791 #define MP0_BASE__INST1_SEG0                       0
0792 #define MP0_BASE__INST1_SEG1                       0
0793 #define MP0_BASE__INST1_SEG2                       0
0794 #define MP0_BASE__INST1_SEG3                       0
0795 #define MP0_BASE__INST1_SEG4                       0
0796 #define MP0_BASE__INST1_SEG5                       0
0797 
0798 #define MP0_BASE__INST2_SEG0                       0
0799 #define MP0_BASE__INST2_SEG1                       0
0800 #define MP0_BASE__INST2_SEG2                       0
0801 #define MP0_BASE__INST2_SEG3                       0
0802 #define MP0_BASE__INST2_SEG4                       0
0803 #define MP0_BASE__INST2_SEG5                       0
0804 
0805 #define MP0_BASE__INST3_SEG0                       0
0806 #define MP0_BASE__INST3_SEG1                       0
0807 #define MP0_BASE__INST3_SEG2                       0
0808 #define MP0_BASE__INST3_SEG3                       0
0809 #define MP0_BASE__INST3_SEG4                       0
0810 #define MP0_BASE__INST3_SEG5                       0
0811 
0812 #define MP0_BASE__INST4_SEG0                       0
0813 #define MP0_BASE__INST4_SEG1                       0
0814 #define MP0_BASE__INST4_SEG2                       0
0815 #define MP0_BASE__INST4_SEG3                       0
0816 #define MP0_BASE__INST4_SEG4                       0
0817 #define MP0_BASE__INST4_SEG5                       0
0818 
0819 #define MP0_BASE__INST5_SEG0                       0
0820 #define MP0_BASE__INST5_SEG1                       0
0821 #define MP0_BASE__INST5_SEG2                       0
0822 #define MP0_BASE__INST5_SEG3                       0
0823 #define MP0_BASE__INST5_SEG4                       0
0824 #define MP0_BASE__INST5_SEG5                       0
0825 
0826 #define MP0_BASE__INST6_SEG0                       0
0827 #define MP0_BASE__INST6_SEG1                       0
0828 #define MP0_BASE__INST6_SEG2                       0
0829 #define MP0_BASE__INST6_SEG3                       0
0830 #define MP0_BASE__INST6_SEG4                       0
0831 #define MP0_BASE__INST6_SEG5                       0
0832 
0833 #define MP1_BASE__INST0_SEG0                       0x00016000
0834 #define MP1_BASE__INST0_SEG1                       0x00DC0000
0835 #define MP1_BASE__INST0_SEG2                       0x00E00000
0836 #define MP1_BASE__INST0_SEG3                       0x00E40000
0837 #define MP1_BASE__INST0_SEG4                       0x0243FC00
0838 #define MP1_BASE__INST0_SEG5                       0
0839 
0840 #define MP1_BASE__INST1_SEG0                       0
0841 #define MP1_BASE__INST1_SEG1                       0
0842 #define MP1_BASE__INST1_SEG2                       0
0843 #define MP1_BASE__INST1_SEG3                       0
0844 #define MP1_BASE__INST1_SEG4                       0
0845 #define MP1_BASE__INST1_SEG5                       0
0846 
0847 #define MP1_BASE__INST2_SEG0                       0
0848 #define MP1_BASE__INST2_SEG1                       0
0849 #define MP1_BASE__INST2_SEG2                       0
0850 #define MP1_BASE__INST2_SEG3                       0
0851 #define MP1_BASE__INST2_SEG4                       0
0852 #define MP1_BASE__INST2_SEG5                       0
0853 
0854 #define MP1_BASE__INST3_SEG0                       0
0855 #define MP1_BASE__INST3_SEG1                       0
0856 #define MP1_BASE__INST3_SEG2                       0
0857 #define MP1_BASE__INST3_SEG3                       0
0858 #define MP1_BASE__INST3_SEG4                       0
0859 #define MP1_BASE__INST3_SEG5                       0
0860 
0861 #define MP1_BASE__INST4_SEG0                       0
0862 #define MP1_BASE__INST4_SEG1                       0
0863 #define MP1_BASE__INST4_SEG2                       0
0864 #define MP1_BASE__INST4_SEG3                       0
0865 #define MP1_BASE__INST4_SEG4                       0
0866 #define MP1_BASE__INST4_SEG5                       0
0867 
0868 #define MP1_BASE__INST5_SEG0                       0
0869 #define MP1_BASE__INST5_SEG1                       0
0870 #define MP1_BASE__INST5_SEG2                       0
0871 #define MP1_BASE__INST5_SEG3                       0
0872 #define MP1_BASE__INST5_SEG4                       0
0873 #define MP1_BASE__INST5_SEG5                       0
0874 
0875 #define MP1_BASE__INST6_SEG0                       0
0876 #define MP1_BASE__INST6_SEG1                       0
0877 #define MP1_BASE__INST6_SEG2                       0
0878 #define MP1_BASE__INST6_SEG3                       0
0879 #define MP1_BASE__INST6_SEG4                       0
0880 #define MP1_BASE__INST6_SEG5                       0
0881 
0882 #define NBIO_BASE__INST0_SEG0                      0x00000000
0883 #define NBIO_BASE__INST0_SEG1                      0x00000014
0884 #define NBIO_BASE__INST0_SEG2                      0x00000D20
0885 #define NBIO_BASE__INST0_SEG3                      0x00010400
0886 #define NBIO_BASE__INST0_SEG4                      0x0241B000
0887 #define NBIO_BASE__INST0_SEG5                      0x04040000
0888 
0889 #define NBIO_BASE__INST1_SEG0                      0
0890 #define NBIO_BASE__INST1_SEG1                      0
0891 #define NBIO_BASE__INST1_SEG2                      0
0892 #define NBIO_BASE__INST1_SEG3                      0
0893 #define NBIO_BASE__INST1_SEG4                      0
0894 #define NBIO_BASE__INST1_SEG5                      0
0895 
0896 #define NBIO_BASE__INST2_SEG0                      0
0897 #define NBIO_BASE__INST2_SEG1                      0
0898 #define NBIO_BASE__INST2_SEG2                      0
0899 #define NBIO_BASE__INST2_SEG3                      0
0900 #define NBIO_BASE__INST2_SEG4                      0
0901 #define NBIO_BASE__INST2_SEG5                      0
0902 
0903 #define NBIO_BASE__INST3_SEG0                      0
0904 #define NBIO_BASE__INST3_SEG1                      0
0905 #define NBIO_BASE__INST3_SEG2                      0
0906 #define NBIO_BASE__INST3_SEG3                      0
0907 #define NBIO_BASE__INST3_SEG4                      0
0908 #define NBIO_BASE__INST3_SEG5                      0
0909 
0910 #define NBIO_BASE__INST4_SEG0                      0
0911 #define NBIO_BASE__INST4_SEG1                      0
0912 #define NBIO_BASE__INST4_SEG2                      0
0913 #define NBIO_BASE__INST4_SEG3                      0
0914 #define NBIO_BASE__INST4_SEG4                      0
0915 #define NBIO_BASE__INST4_SEG5                      0
0916 
0917 #define NBIO_BASE__INST5_SEG0                      0
0918 #define NBIO_BASE__INST5_SEG1                      0
0919 #define NBIO_BASE__INST5_SEG2                      0
0920 #define NBIO_BASE__INST5_SEG3                      0
0921 #define NBIO_BASE__INST5_SEG4                      0
0922 #define NBIO_BASE__INST5_SEG5                      0
0923 
0924 #define NBIO_BASE__INST6_SEG0                      0
0925 #define NBIO_BASE__INST6_SEG1                      0
0926 #define NBIO_BASE__INST6_SEG2                      0
0927 #define NBIO_BASE__INST6_SEG3                      0
0928 #define NBIO_BASE__INST6_SEG4                      0
0929 #define NBIO_BASE__INST6_SEG5                      0
0930 
0931 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0932 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
0933 #define OSSSYS_BASE__INST0_SEG2                    0
0934 #define OSSSYS_BASE__INST0_SEG3                    0
0935 #define OSSSYS_BASE__INST0_SEG4                    0
0936 #define OSSSYS_BASE__INST0_SEG5                    0
0937 
0938 #define OSSSYS_BASE__INST1_SEG0                    0
0939 #define OSSSYS_BASE__INST1_SEG1                    0
0940 #define OSSSYS_BASE__INST1_SEG2                    0
0941 #define OSSSYS_BASE__INST1_SEG3                    0
0942 #define OSSSYS_BASE__INST1_SEG4                    0
0943 #define OSSSYS_BASE__INST1_SEG5                    0
0944 
0945 #define OSSSYS_BASE__INST2_SEG0                    0
0946 #define OSSSYS_BASE__INST2_SEG1                    0
0947 #define OSSSYS_BASE__INST2_SEG2                    0
0948 #define OSSSYS_BASE__INST2_SEG3                    0
0949 #define OSSSYS_BASE__INST2_SEG4                    0
0950 #define OSSSYS_BASE__INST2_SEG5                    0
0951 
0952 #define OSSSYS_BASE__INST3_SEG0                    0
0953 #define OSSSYS_BASE__INST3_SEG1                    0
0954 #define OSSSYS_BASE__INST3_SEG2                    0
0955 #define OSSSYS_BASE__INST3_SEG3                    0
0956 #define OSSSYS_BASE__INST3_SEG4                    0
0957 #define OSSSYS_BASE__INST3_SEG5                    0
0958 
0959 #define OSSSYS_BASE__INST4_SEG0                    0
0960 #define OSSSYS_BASE__INST4_SEG1                    0
0961 #define OSSSYS_BASE__INST4_SEG2                    0
0962 #define OSSSYS_BASE__INST4_SEG3                    0
0963 #define OSSSYS_BASE__INST4_SEG4                    0
0964 #define OSSSYS_BASE__INST4_SEG5                    0
0965 
0966 #define OSSSYS_BASE__INST5_SEG0                    0
0967 #define OSSSYS_BASE__INST5_SEG1                    0
0968 #define OSSSYS_BASE__INST5_SEG2                    0
0969 #define OSSSYS_BASE__INST5_SEG3                    0
0970 #define OSSSYS_BASE__INST5_SEG4                    0
0971 #define OSSSYS_BASE__INST5_SEG5                    0
0972 
0973 #define OSSSYS_BASE__INST6_SEG0                    0
0974 #define OSSSYS_BASE__INST6_SEG1                    0
0975 #define OSSSYS_BASE__INST6_SEG2                    0
0976 #define OSSSYS_BASE__INST6_SEG3                    0
0977 #define OSSSYS_BASE__INST6_SEG4                    0
0978 #define OSSSYS_BASE__INST6_SEG5                    0
0979 
0980 #define PCIE0_BASE__INST0_SEG0                     0x00000000
0981 #define PCIE0_BASE__INST0_SEG1                     0x00000014
0982 #define PCIE0_BASE__INST0_SEG2                     0x00000D20
0983 #define PCIE0_BASE__INST0_SEG3                     0x00010400
0984 #define PCIE0_BASE__INST0_SEG4                     0x0241B000
0985 #define PCIE0_BASE__INST0_SEG5                     0x04040000
0986 
0987 #define PCIE0_BASE__INST1_SEG0                     0
0988 #define PCIE0_BASE__INST1_SEG1                     0
0989 #define PCIE0_BASE__INST1_SEG2                     0
0990 #define PCIE0_BASE__INST1_SEG3                     0
0991 #define PCIE0_BASE__INST1_SEG4                     0
0992 #define PCIE0_BASE__INST1_SEG5                     0
0993 
0994 #define PCIE0_BASE__INST2_SEG0                     0
0995 #define PCIE0_BASE__INST2_SEG1                     0
0996 #define PCIE0_BASE__INST2_SEG2                     0
0997 #define PCIE0_BASE__INST2_SEG3                     0
0998 #define PCIE0_BASE__INST2_SEG4                     0
0999 #define PCIE0_BASE__INST2_SEG5                     0
1000 
1001 #define PCIE0_BASE__INST3_SEG0                     0
1002 #define PCIE0_BASE__INST3_SEG1                     0
1003 #define PCIE0_BASE__INST3_SEG2                     0
1004 #define PCIE0_BASE__INST3_SEG3                     0
1005 #define PCIE0_BASE__INST3_SEG4                     0
1006 #define PCIE0_BASE__INST3_SEG5                     0
1007 
1008 #define PCIE0_BASE__INST4_SEG0                     0
1009 #define PCIE0_BASE__INST4_SEG1                     0
1010 #define PCIE0_BASE__INST4_SEG2                     0
1011 #define PCIE0_BASE__INST4_SEG3                     0
1012 #define PCIE0_BASE__INST4_SEG4                     0
1013 #define PCIE0_BASE__INST4_SEG5                     0
1014 
1015 #define PCIE0_BASE__INST5_SEG0                     0
1016 #define PCIE0_BASE__INST5_SEG1                     0
1017 #define PCIE0_BASE__INST5_SEG2                     0
1018 #define PCIE0_BASE__INST5_SEG3                     0
1019 #define PCIE0_BASE__INST5_SEG4                     0
1020 #define PCIE0_BASE__INST5_SEG5                     0
1021 
1022 #define PCIE0_BASE__INST6_SEG0                     0
1023 #define PCIE0_BASE__INST6_SEG1                     0
1024 #define PCIE0_BASE__INST6_SEG2                     0
1025 #define PCIE0_BASE__INST6_SEG3                     0
1026 #define PCIE0_BASE__INST6_SEG4                     0
1027 #define PCIE0_BASE__INST6_SEG5                     0
1028 
1029 #define SDMA0_BASE__INST0_SEG0                     0x00001260
1030 #define SDMA0_BASE__INST0_SEG1                     0x0000A000
1031 #define SDMA0_BASE__INST0_SEG2                     0x0001C000
1032 #define SDMA0_BASE__INST0_SEG3                     0x02402C00
1033 #define SDMA0_BASE__INST0_SEG4                     0
1034 #define SDMA0_BASE__INST0_SEG5                     0
1035 
1036 #define SDMA0_BASE__INST1_SEG0                     0
1037 #define SDMA0_BASE__INST1_SEG1                     0
1038 #define SDMA0_BASE__INST1_SEG2                     0
1039 #define SDMA0_BASE__INST1_SEG3                     0
1040 #define SDMA0_BASE__INST1_SEG4                     0
1041 #define SDMA0_BASE__INST1_SEG5                     0
1042 
1043 #define SDMA0_BASE__INST2_SEG0                     0
1044 #define SDMA0_BASE__INST2_SEG1                     0
1045 #define SDMA0_BASE__INST2_SEG2                     0
1046 #define SDMA0_BASE__INST2_SEG3                     0
1047 #define SDMA0_BASE__INST2_SEG4                     0
1048 #define SDMA0_BASE__INST2_SEG5                     0
1049 
1050 #define SDMA0_BASE__INST3_SEG0                     0
1051 #define SDMA0_BASE__INST3_SEG1                     0
1052 #define SDMA0_BASE__INST3_SEG2                     0
1053 #define SDMA0_BASE__INST3_SEG3                     0
1054 #define SDMA0_BASE__INST3_SEG4                     0
1055 #define SDMA0_BASE__INST3_SEG5                     0
1056 
1057 #define SDMA0_BASE__INST4_SEG0                     0
1058 #define SDMA0_BASE__INST4_SEG1                     0
1059 #define SDMA0_BASE__INST4_SEG2                     0
1060 #define SDMA0_BASE__INST4_SEG3                     0
1061 #define SDMA0_BASE__INST4_SEG4                     0
1062 #define SDMA0_BASE__INST4_SEG5                     0
1063 
1064 #define SDMA0_BASE__INST5_SEG0                     0
1065 #define SDMA0_BASE__INST5_SEG1                     0
1066 #define SDMA0_BASE__INST5_SEG2                     0
1067 #define SDMA0_BASE__INST5_SEG3                     0
1068 #define SDMA0_BASE__INST5_SEG4                     0
1069 #define SDMA0_BASE__INST5_SEG5                     0
1070 
1071 #define SDMA0_BASE__INST6_SEG0                     0
1072 #define SDMA0_BASE__INST6_SEG1                     0
1073 #define SDMA0_BASE__INST6_SEG2                     0
1074 #define SDMA0_BASE__INST6_SEG3                     0
1075 #define SDMA0_BASE__INST6_SEG4                     0
1076 #define SDMA0_BASE__INST6_SEG5                     0
1077 
1078 #define SMUIO_BASE__INST0_SEG0                     0x00016800
1079 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
1080 #define SMUIO_BASE__INST0_SEG2                     0x00440000
1081 #define SMUIO_BASE__INST0_SEG3                     0x02401000
1082 #define SMUIO_BASE__INST0_SEG4                     0
1083 #define SMUIO_BASE__INST0_SEG5                     0
1084 
1085 #define SMUIO_BASE__INST1_SEG0                     0
1086 #define SMUIO_BASE__INST1_SEG1                     0
1087 #define SMUIO_BASE__INST1_SEG2                     0
1088 #define SMUIO_BASE__INST1_SEG3                     0
1089 #define SMUIO_BASE__INST1_SEG4                     0
1090 #define SMUIO_BASE__INST1_SEG5                     0
1091 
1092 #define SMUIO_BASE__INST2_SEG0                     0
1093 #define SMUIO_BASE__INST2_SEG1                     0
1094 #define SMUIO_BASE__INST2_SEG2                     0
1095 #define SMUIO_BASE__INST2_SEG3                     0
1096 #define SMUIO_BASE__INST2_SEG4                     0
1097 #define SMUIO_BASE__INST2_SEG5                     0
1098 
1099 #define SMUIO_BASE__INST3_SEG0                     0
1100 #define SMUIO_BASE__INST3_SEG1                     0
1101 #define SMUIO_BASE__INST3_SEG2                     0
1102 #define SMUIO_BASE__INST3_SEG3                     0
1103 #define SMUIO_BASE__INST3_SEG4                     0
1104 #define SMUIO_BASE__INST3_SEG5                     0
1105 
1106 #define SMUIO_BASE__INST4_SEG0                     0
1107 #define SMUIO_BASE__INST4_SEG1                     0
1108 #define SMUIO_BASE__INST4_SEG2                     0
1109 #define SMUIO_BASE__INST4_SEG3                     0
1110 #define SMUIO_BASE__INST4_SEG4                     0
1111 #define SMUIO_BASE__INST4_SEG5                     0
1112 
1113 #define SMUIO_BASE__INST5_SEG0                     0
1114 #define SMUIO_BASE__INST5_SEG1                     0
1115 #define SMUIO_BASE__INST5_SEG2                     0
1116 #define SMUIO_BASE__INST5_SEG3                     0
1117 #define SMUIO_BASE__INST5_SEG4                     0
1118 #define SMUIO_BASE__INST5_SEG5                     0
1119 
1120 #define SMUIO_BASE__INST6_SEG0                     0
1121 #define SMUIO_BASE__INST6_SEG1                     0
1122 #define SMUIO_BASE__INST6_SEG2                     0
1123 #define SMUIO_BASE__INST6_SEG3                     0
1124 #define SMUIO_BASE__INST6_SEG4                     0
1125 #define SMUIO_BASE__INST6_SEG5                     0
1126 
1127 #define THM_BASE__INST0_SEG0                       0x00016600
1128 #define THM_BASE__INST0_SEG1                       0x02400C00
1129 #define THM_BASE__INST0_SEG2                       0
1130 #define THM_BASE__INST0_SEG3                       0
1131 #define THM_BASE__INST0_SEG4                       0
1132 #define THM_BASE__INST0_SEG5                       0
1133 
1134 #define THM_BASE__INST1_SEG0                       0
1135 #define THM_BASE__INST1_SEG1                       0
1136 #define THM_BASE__INST1_SEG2                       0
1137 #define THM_BASE__INST1_SEG3                       0
1138 #define THM_BASE__INST1_SEG4                       0
1139 #define THM_BASE__INST1_SEG5                       0
1140 
1141 #define THM_BASE__INST2_SEG0                       0
1142 #define THM_BASE__INST2_SEG1                       0
1143 #define THM_BASE__INST2_SEG2                       0
1144 #define THM_BASE__INST2_SEG3                       0
1145 #define THM_BASE__INST2_SEG4                       0
1146 #define THM_BASE__INST2_SEG5                       0
1147 
1148 #define THM_BASE__INST3_SEG0                       0
1149 #define THM_BASE__INST3_SEG1                       0
1150 #define THM_BASE__INST3_SEG2                       0
1151 #define THM_BASE__INST3_SEG3                       0
1152 #define THM_BASE__INST3_SEG4                       0
1153 #define THM_BASE__INST3_SEG5                       0
1154 
1155 #define THM_BASE__INST4_SEG0                       0
1156 #define THM_BASE__INST4_SEG1                       0
1157 #define THM_BASE__INST4_SEG2                       0
1158 #define THM_BASE__INST4_SEG3                       0
1159 #define THM_BASE__INST4_SEG4                       0
1160 #define THM_BASE__INST4_SEG5                       0
1161 
1162 #define THM_BASE__INST5_SEG0                       0
1163 #define THM_BASE__INST5_SEG1                       0
1164 #define THM_BASE__INST5_SEG2                       0
1165 #define THM_BASE__INST5_SEG3                       0
1166 #define THM_BASE__INST5_SEG4                       0
1167 #define THM_BASE__INST5_SEG5                       0
1168 
1169 #define THM_BASE__INST6_SEG0                       0
1170 #define THM_BASE__INST6_SEG1                       0
1171 #define THM_BASE__INST6_SEG2                       0
1172 #define THM_BASE__INST6_SEG3                       0
1173 #define THM_BASE__INST6_SEG4                       0
1174 #define THM_BASE__INST6_SEG5                       0
1175 
1176 #define UMC_BASE__INST0_SEG0                       0x00014000
1177 #define UMC_BASE__INST0_SEG1                       0x02425800
1178 #define UMC_BASE__INST0_SEG2                       0
1179 #define UMC_BASE__INST0_SEG3                       0
1180 #define UMC_BASE__INST0_SEG4                       0
1181 #define UMC_BASE__INST0_SEG5                       0
1182 
1183 #define UMC_BASE__INST1_SEG0                       0x00054000
1184 #define UMC_BASE__INST1_SEG1                       0x02425C00
1185 #define UMC_BASE__INST1_SEG2                       0
1186 #define UMC_BASE__INST1_SEG3                       0
1187 #define UMC_BASE__INST1_SEG4                       0
1188 #define UMC_BASE__INST1_SEG5                       0
1189 
1190 #define UMC_BASE__INST2_SEG0                       0
1191 #define UMC_BASE__INST2_SEG1                       0
1192 #define UMC_BASE__INST2_SEG2                       0
1193 #define UMC_BASE__INST2_SEG3                       0
1194 #define UMC_BASE__INST2_SEG4                       0
1195 #define UMC_BASE__INST2_SEG5                       0
1196 
1197 #define UMC_BASE__INST3_SEG0                       0
1198 #define UMC_BASE__INST3_SEG1                       0
1199 #define UMC_BASE__INST3_SEG2                       0
1200 #define UMC_BASE__INST3_SEG3                       0
1201 #define UMC_BASE__INST3_SEG4                       0
1202 #define UMC_BASE__INST3_SEG5                       0
1203 
1204 #define UMC_BASE__INST4_SEG0                       0
1205 #define UMC_BASE__INST4_SEG1                       0
1206 #define UMC_BASE__INST4_SEG2                       0
1207 #define UMC_BASE__INST4_SEG3                       0
1208 #define UMC_BASE__INST4_SEG4                       0
1209 #define UMC_BASE__INST4_SEG5                       0
1210 
1211 #define UMC_BASE__INST5_SEG0                       0
1212 #define UMC_BASE__INST5_SEG1                       0
1213 #define UMC_BASE__INST5_SEG2                       0
1214 #define UMC_BASE__INST5_SEG3                       0
1215 #define UMC_BASE__INST5_SEG4                       0
1216 #define UMC_BASE__INST5_SEG5                       0
1217 
1218 #define UMC_BASE__INST6_SEG0                       0
1219 #define UMC_BASE__INST6_SEG1                       0
1220 #define UMC_BASE__INST6_SEG2                       0
1221 #define UMC_BASE__INST6_SEG3                       0
1222 #define UMC_BASE__INST6_SEG4                       0
1223 #define UMC_BASE__INST6_SEG5                       0
1224 
1225 #define VCN0_BASE__INST0_SEG0                      0x00007800
1226 #define VCN0_BASE__INST0_SEG1                      0x00007E00
1227 #define VCN0_BASE__INST0_SEG2                      0x02403000
1228 #define VCN0_BASE__INST0_SEG3                      0
1229 #define VCN0_BASE__INST0_SEG4                      0
1230 #define VCN0_BASE__INST0_SEG5                      0
1231 
1232 #define VCN0_BASE__INST1_SEG0                      0
1233 #define VCN0_BASE__INST1_SEG1                      0
1234 #define VCN0_BASE__INST1_SEG2                      0
1235 #define VCN0_BASE__INST1_SEG3                      0
1236 #define VCN0_BASE__INST1_SEG4                      0
1237 #define VCN0_BASE__INST1_SEG5                      0
1238 
1239 #define VCN0_BASE__INST2_SEG0                      0
1240 #define VCN0_BASE__INST2_SEG1                      0
1241 #define VCN0_BASE__INST2_SEG2                      0
1242 #define VCN0_BASE__INST2_SEG3                      0
1243 #define VCN0_BASE__INST2_SEG4                      0
1244 #define VCN0_BASE__INST2_SEG5                      0
1245 
1246 #define VCN0_BASE__INST3_SEG0                      0
1247 #define VCN0_BASE__INST3_SEG1                      0
1248 #define VCN0_BASE__INST3_SEG2                      0
1249 #define VCN0_BASE__INST3_SEG3                      0
1250 #define VCN0_BASE__INST3_SEG4                      0
1251 #define VCN0_BASE__INST3_SEG5                      0
1252 
1253 #define VCN0_BASE__INST4_SEG0                      0
1254 #define VCN0_BASE__INST4_SEG1                      0
1255 #define VCN0_BASE__INST4_SEG2                      0
1256 #define VCN0_BASE__INST4_SEG3                      0
1257 #define VCN0_BASE__INST4_SEG4                      0
1258 #define VCN0_BASE__INST4_SEG5                      0
1259 
1260 #define VCN0_BASE__INST5_SEG0                      0
1261 #define VCN0_BASE__INST5_SEG1                      0
1262 #define VCN0_BASE__INST5_SEG2                      0
1263 #define VCN0_BASE__INST5_SEG3                      0
1264 #define VCN0_BASE__INST5_SEG4                      0
1265 #define VCN0_BASE__INST5_SEG5                      0
1266 
1267 #define VCN0_BASE__INST6_SEG0                      0
1268 #define VCN0_BASE__INST6_SEG1                      0
1269 #define VCN0_BASE__INST6_SEG2                      0
1270 #define VCN0_BASE__INST6_SEG3                      0
1271 #define VCN0_BASE__INST6_SEG4                      0
1272 #define VCN0_BASE__INST6_SEG5                      0
1273 
1274 #endif
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