amd/include/arct_ip_offset.h

0001 /*
0002  * Copyright (C) 2018  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _arct_ip_offset_HEADER
0022 #define _arct_ip_offset_HEADER
0023
0024 #define MAX_INSTANCE                                       8
0025 #define MAX_SEGMENT                                         6
0026
0027
0028 struct IP_BASE_INSTANCE
0029 {
0030     unsigned int segment[MAX_SEGMENT];
0031 } __maybe_unused;
0032
0033 struct IP_BASE
0034 {
0035     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0036 } __maybe_unused;
0037
0038
0039 static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } },
0042                                         { { 0, 0, 0, 0, 0, 0 } },
0043                                         { { 0, 0, 0, 0, 0, 0 } },
0044                                         { { 0, 0, 0, 0, 0, 0 } },
0045                                         { { 0, 0, 0, 0, 0, 0 } },
0046                                         { { 0, 0, 0, 0, 0, 0 } } } };
0047 static const struct IP_BASE CLK_BASE            ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
0048                                         { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },
0049                                         { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },
0050                                         { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },
0051                                         { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },
0052                                         { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },
0053                                         { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0, 0 } } } };
0055 static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },
0056                                         { { 0, 0, 0, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } } } };
0063 static const struct IP_BASE FUSE_BASE            ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0, 0 } },
0070                                         { { 0, 0, 0, 0, 0, 0 } } } };
0071 static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0, 0 } },
0075                                         { { 0, 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } },
0077                                         { { 0, 0, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } } } };
0079 static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } },
0081                                         { { 0, 0, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } },
0084                                         { { 0, 0, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } } } };
0087 static const struct IP_BASE MMHUB_BASE            ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } },
0091                                         { { 0, 0, 0, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } } } };
0095 static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0, 0 } },
0098                                         { { 0, 0, 0, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0, 0 } } } };
0103 static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } },
0105                                         { { 0, 0, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } },
0109                                         { { 0, 0, 0, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0, 0 } } } };
0111 static const struct IP_BASE NBIF0_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },
0112                                         { { 0, 0, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0, 0 } },
0117                                         { { 0, 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } } } };
0119 static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } },
0123                                         { { 0, 0, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } },
0126                                         { { 0, 0, 0, 0, 0, 0 } } } };
0127 static const struct IP_BASE PCIE0_BASE            ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } },
0133                                         { { 0, 0, 0, 0, 0, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } } } };
0135 static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0, 0 } },
0140                                         { { 0, 0, 0, 0, 0, 0 } },
0141                                         { { 0, 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0, 0 } } } };
0143 static const struct IP_BASE SDMA1_BASE            ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
0144                                         { { 0, 0, 0, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0, 0 } },
0147                                         { { 0, 0, 0, 0, 0, 0 } },
0148                                         { { 0, 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0, 0 } } } };
0151 static const struct IP_BASE SDMA2_BASE            ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
0152                                         { { 0, 0, 0, 0, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0, 0 } },
0154                                         { { 0, 0, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0, 0 } },
0158                                         { { 0, 0, 0, 0, 0, 0 } } } };
0159 static const struct IP_BASE SDMA3_BASE            ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0, 0 } },
0161                                         { { 0, 0, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0, 0 } },
0165                                         { { 0, 0, 0, 0, 0, 0 } },
0166                                         { { 0, 0, 0, 0, 0, 0 } } } };
0167 static const struct IP_BASE SDMA4_BASE            ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
0168                                         { { 0, 0, 0, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0, 0 } },
0172                                         { { 0, 0, 0, 0, 0, 0 } },
0173                                         { { 0, 0, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0, 0 } } } };
0175 static const struct IP_BASE SDMA5_BASE            ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0, 0 } },
0179                                         { { 0, 0, 0, 0, 0, 0 } },
0180                                         { { 0, 0, 0, 0, 0, 0 } },
0181                                         { { 0, 0, 0, 0, 0, 0 } },
0182                                         { { 0, 0, 0, 0, 0, 0 } } } };
0183 static const struct IP_BASE SDMA6_BASE            ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },
0184                                        { { 0, 0, 0, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0, 0 } },
0186                                         { { 0, 0, 0, 0, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0, 0 } },
0189                                         { { 0, 0, 0, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0, 0 } } } };
0191 static const struct IP_BASE SDMA7_BASE            ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0, 0 } },
0193                                         { { 0, 0, 0, 0, 0, 0 } },
0194                                         { { 0, 0, 0, 0, 0, 0 } },
0195                                         { { 0, 0, 0, 0, 0, 0 } },
0196                                         { { 0, 0, 0, 0, 0, 0 } },
0197                                         { { 0, 0, 0, 0, 0, 0 } },
0198                                         { { 0, 0, 0, 0, 0, 0 } } } };
0199 static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
0200                                         { { 0, 0, 0, 0, 0, 0 } },
0201                                         { { 0, 0, 0, 0, 0, 0 } },
0202                                         { { 0, 0, 0, 0, 0, 0 } },
0203                                         { { 0, 0, 0, 0, 0, 0 } },
0204                                         { { 0, 0, 0, 0, 0, 0 } } } };
0205 static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
0206                                         { { 0, 0, 0, 0, 0, 0 } },
0207                                         { { 0, 0, 0, 0, 0, 0 } },
0208                                         { { 0, 0, 0, 0, 0, 0 } },
0209                                         { { 0, 0, 0, 0, 0, 0 } },
0210                                         { { 0, 0, 0, 0, 0, 0 } } } };
0211 static const struct IP_BASE UMC_BASE            ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },
0212                                         { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },
0213                                         { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },
0214                                         { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },
0215                                         { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },
0216                                         { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },
0217                                         { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },
0218                                         { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };
0219 static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },
0220                                         { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },
0221                                         { { 0, 0, 0, 0, 0, 0 } },
0222                                         { { 0, 0, 0, 0, 0, 0 } },
0223                                         { { 0, 0, 0, 0, 0, 0 } },
0224                                         { { 0, 0, 0, 0, 0, 0 } },
0225                                         { { 0, 0, 0, 0, 0, 0 } },
0226                                         { { 0, 0, 0, 0, 0, 0 } } } };
0227 static const struct IP_BASE DBGU_IO_BASE            ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },
0228                                         { { 0, 0, 0, 0, 0, 0 } },
0229                                         { { 0, 0, 0, 0, 0, 0 } },
0230                                         { { 0, 0, 0, 0, 0, 0 } },
0231                                         { { 0, 0, 0, 0, 0, 0 } },
0232                                         { { 0, 0, 0, 0, 0, 0 } },
0233                                         { { 0, 0, 0, 0, 0, 0 } },
0234                                         { { 0, 0, 0, 0, 0, 0 } } } };
0235 static const struct IP_BASE RSMU_BASE            ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
0236                                         { { 0, 0, 0, 0, 0, 0 } },
0237                                         { { 0, 0, 0, 0, 0, 0 } },
0238                                         { { 0, 0, 0, 0, 0, 0 } },
0239                                         { { 0, 0, 0, 0, 0, 0 } },
0240                                         { { 0, 0, 0, 0, 0, 0 } },
0241                                         { { 0, 0, 0, 0, 0, 0 } },
0242                                         { { 0, 0, 0, 0, 0, 0 } } } };
0243
0244
0245
0246 #define ATHUB_BASE__INST0_SEG0                     0x00000C20
0247 #define ATHUB_BASE__INST0_SEG1                     0x00012460
0248 #define ATHUB_BASE__INST0_SEG2                     0x00408C00
0249 #define ATHUB_BASE__INST0_SEG3                     0
0250 #define ATHUB_BASE__INST0_SEG4                     0
0251 #define ATHUB_BASE__INST0_SEG5                     0
0252
0253 #define ATHUB_BASE__INST1_SEG0                     0
0254 #define ATHUB_BASE__INST1_SEG1                     0
0255 #define ATHUB_BASE__INST1_SEG2                     0
0256 #define ATHUB_BASE__INST1_SEG3                     0
0257 #define ATHUB_BASE__INST1_SEG4                     0
0258 #define ATHUB_BASE__INST1_SEG5                     0
0259
0260 #define ATHUB_BASE__INST2_SEG0                     0
0261 #define ATHUB_BASE__INST2_SEG1                     0
0262 #define ATHUB_BASE__INST2_SEG2                     0
0263 #define ATHUB_BASE__INST2_SEG3                     0
0264 #define ATHUB_BASE__INST2_SEG4                     0
0265 #define ATHUB_BASE__INST2_SEG5                     0
0266
0267 #define ATHUB_BASE__INST3_SEG0                     0
0268 #define ATHUB_BASE__INST3_SEG1                     0
0269 #define ATHUB_BASE__INST3_SEG2                     0
0270 #define ATHUB_BASE__INST3_SEG3                     0
0271 #define ATHUB_BASE__INST3_SEG4                     0
0272 #define ATHUB_BASE__INST3_SEG5                     0
0273
0274 #define ATHUB_BASE__INST4_SEG0                     0
0275 #define ATHUB_BASE__INST4_SEG1                     0
0276 #define ATHUB_BASE__INST4_SEG2                     0
0277 #define ATHUB_BASE__INST4_SEG3                     0
0278 #define ATHUB_BASE__INST4_SEG4                     0
0279 #define ATHUB_BASE__INST4_SEG5                     0
0280
0281 #define ATHUB_BASE__INST5_SEG0                     0
0282 #define ATHUB_BASE__INST5_SEG1                     0
0283 #define ATHUB_BASE__INST5_SEG2                     0
0284 #define ATHUB_BASE__INST5_SEG3                     0
0285 #define ATHUB_BASE__INST5_SEG4                     0
0286 #define ATHUB_BASE__INST5_SEG5                     0
0287
0288 #define ATHUB_BASE__INST6_SEG0                     0
0289 #define ATHUB_BASE__INST6_SEG1                     0
0290 #define ATHUB_BASE__INST6_SEG2                     0
0291 #define ATHUB_BASE__INST6_SEG3                     0
0292 #define ATHUB_BASE__INST6_SEG4                     0
0293 #define ATHUB_BASE__INST6_SEG5                     0
0294
0295 #define ATHUB_BASE__INST7_SEG0                     0
0296 #define ATHUB_BASE__INST7_SEG1                     0
0297 #define ATHUB_BASE__INST7_SEG2                     0
0298 #define ATHUB_BASE__INST7_SEG3                     0
0299 #define ATHUB_BASE__INST7_SEG4                     0
0300 #define ATHUB_BASE__INST7_SEG5                     0
0301
0302 #define CLK_BASE__INST0_SEG0                       0x000120C0
0303 #define CLK_BASE__INST0_SEG1                       0x00016C00
0304 #define CLK_BASE__INST0_SEG2                       0x00401800
0305 #define CLK_BASE__INST0_SEG3                       0
0306 #define CLK_BASE__INST0_SEG4                       0
0307 #define CLK_BASE__INST0_SEG5                       0
0308
0309 #define CLK_BASE__INST1_SEG0                       0x000120E0
0310 #define CLK_BASE__INST1_SEG1                       0x00016E00
0311 #define CLK_BASE__INST1_SEG2                       0x00401C00
0312 #define CLK_BASE__INST1_SEG3                       0
0313 #define CLK_BASE__INST1_SEG4                       0
0314 #define CLK_BASE__INST1_SEG5                       0
0315
0316 #define CLK_BASE__INST2_SEG0                       0x00012100
0317 #define CLK_BASE__INST2_SEG1                       0x00017000
0318 #define CLK_BASE__INST2_SEG2                       0x00402000
0319 #define CLK_BASE__INST2_SEG3                       0
0320 #define CLK_BASE__INST2_SEG4                       0
0321 #define CLK_BASE__INST2_SEG5                       0
0322
0323 #define CLK_BASE__INST3_SEG0                       0x00012120
0324 #define CLK_BASE__INST3_SEG1                       0x00017200
0325 #define CLK_BASE__INST3_SEG2                       0x00402400
0326 #define CLK_BASE__INST3_SEG3                       0
0327 #define CLK_BASE__INST3_SEG4                       0
0328 #define CLK_BASE__INST3_SEG5                       0
0329
0330 #define CLK_BASE__INST4_SEG0                       0x000136C0
0331 #define CLK_BASE__INST4_SEG1                       0x0001B000
0332 #define CLK_BASE__INST4_SEG2                       0x0042D800
0333 #define CLK_BASE__INST4_SEG3                       0
0334 #define CLK_BASE__INST4_SEG4                       0
0335 #define CLK_BASE__INST4_SEG5                       0
0336
0337 #define CLK_BASE__INST5_SEG0                       0x00013720
0338 #define CLK_BASE__INST5_SEG1                       0x0001B200
0339 #define CLK_BASE__INST5_SEG2                       0x0042E400
0340 #define CLK_BASE__INST5_SEG3                       0
0341 #define CLK_BASE__INST5_SEG4                       0
0342 #define CLK_BASE__INST5_SEG5                       0
0343
0344 #define CLK_BASE__INST6_SEG0                       0x000125E0
0345 #define CLK_BASE__INST6_SEG1                       0x00017E00
0346 #define CLK_BASE__INST6_SEG2                       0x0040BC00
0347 #define CLK_BASE__INST6_SEG3                       0
0348 #define CLK_BASE__INST6_SEG4                       0
0349 #define CLK_BASE__INST6_SEG5                       0
0350
0351 #define CLK_BASE__INST7_SEG0                       0
0352 #define CLK_BASE__INST7_SEG1                       0
0353 #define CLK_BASE__INST7_SEG2                       0
0354 #define CLK_BASE__INST7_SEG3                       0
0355 #define CLK_BASE__INST7_SEG4                       0
0356 #define CLK_BASE__INST7_SEG5                       0
0357
0358 #define DF_BASE__INST0_SEG0                        0x00007000
0359 #define DF_BASE__INST0_SEG1                        0x000125C0
0360 #define DF_BASE__INST0_SEG2                        0x0040B800
0361 #define DF_BASE__INST0_SEG3                        0
0362 #define DF_BASE__INST0_SEG4                        0
0363 #define DF_BASE__INST0_SEG5                        0
0364
0365 #define DF_BASE__INST1_SEG0                        0
0366 #define DF_BASE__INST1_SEG1                        0
0367 #define DF_BASE__INST1_SEG2                        0
0368 #define DF_BASE__INST1_SEG3                        0
0369 #define DF_BASE__INST1_SEG4                        0
0370 #define DF_BASE__INST1_SEG5                        0
0371
0372 #define DF_BASE__INST2_SEG0                        0
0373 #define DF_BASE__INST2_SEG1                        0
0374 #define DF_BASE__INST2_SEG2                        0
0375 #define DF_BASE__INST2_SEG3                        0
0376 #define DF_BASE__INST2_SEG4                        0
0377 #define DF_BASE__INST2_SEG5                        0
0378
0379 #define DF_BASE__INST3_SEG0                        0
0380 #define DF_BASE__INST3_SEG1                        0
0381 #define DF_BASE__INST3_SEG2                        0
0382 #define DF_BASE__INST3_SEG3                        0
0383 #define DF_BASE__INST3_SEG4                        0
0384 #define DF_BASE__INST3_SEG5                        0
0385
0386 #define DF_BASE__INST4_SEG0                        0
0387 #define DF_BASE__INST4_SEG1                        0
0388 #define DF_BASE__INST4_SEG2                        0
0389 #define DF_BASE__INST4_SEG3                        0
0390 #define DF_BASE__INST4_SEG4                        0
0391 #define DF_BASE__INST4_SEG5                        0
0392
0393 #define DF_BASE__INST5_SEG0                        0
0394 #define DF_BASE__INST5_SEG1                        0
0395 #define DF_BASE__INST5_SEG2                        0
0396 #define DF_BASE__INST5_SEG3                        0
0397 #define DF_BASE__INST5_SEG4                        0
0398 #define DF_BASE__INST5_SEG5                        0
0399
0400 #define DF_BASE__INST6_SEG0                        0
0401 #define DF_BASE__INST6_SEG1                        0
0402 #define DF_BASE__INST6_SEG2                        0
0403 #define DF_BASE__INST6_SEG3                        0
0404 #define DF_BASE__INST6_SEG4                        0
0405 #define DF_BASE__INST6_SEG5                        0
0406
0407 #define DF_BASE__INST7_SEG0                        0
0408 #define DF_BASE__INST7_SEG1                        0
0409 #define DF_BASE__INST7_SEG2                        0
0410 #define DF_BASE__INST7_SEG3                        0
0411 #define DF_BASE__INST7_SEG4                        0
0412 #define DF_BASE__INST7_SEG5                        0
0413
0414 #define FUSE_BASE__INST0_SEG0                      0x000120A0
0415 #define FUSE_BASE__INST0_SEG1                      0x00017400
0416 #define FUSE_BASE__INST0_SEG2                      0x00401400
0417 #define FUSE_BASE__INST0_SEG3                      0
0418 #define FUSE_BASE__INST0_SEG4                      0
0419 #define FUSE_BASE__INST0_SEG5                      0
0420
0421 #define FUSE_BASE__INST1_SEG0                      0
0422 #define FUSE_BASE__INST1_SEG1                      0
0423 #define FUSE_BASE__INST1_SEG2                      0
0424 #define FUSE_BASE__INST1_SEG3                      0
0425 #define FUSE_BASE__INST1_SEG4                      0
0426 #define FUSE_BASE__INST1_SEG5                      0
0427
0428 #define FUSE_BASE__INST2_SEG0                      0
0429 #define FUSE_BASE__INST2_SEG1                      0
0430 #define FUSE_BASE__INST2_SEG2                      0
0431 #define FUSE_BASE__INST2_SEG3                      0
0432 #define FUSE_BASE__INST2_SEG4                      0
0433 #define FUSE_BASE__INST2_SEG5                      0
0434
0435 #define FUSE_BASE__INST3_SEG0                      0
0436 #define FUSE_BASE__INST3_SEG1                      0
0437 #define FUSE_BASE__INST3_SEG2                      0
0438 #define FUSE_BASE__INST3_SEG3                      0
0439 #define FUSE_BASE__INST3_SEG4                      0
0440 #define FUSE_BASE__INST3_SEG5                      0
0441
0442 #define FUSE_BASE__INST4_SEG0                      0
0443 #define FUSE_BASE__INST4_SEG1                      0
0444 #define FUSE_BASE__INST4_SEG2                      0
0445 #define FUSE_BASE__INST4_SEG3                      0
0446 #define FUSE_BASE__INST4_SEG4                      0
0447 #define FUSE_BASE__INST4_SEG5                      0
0448
0449 #define FUSE_BASE__INST5_SEG0                      0
0450 #define FUSE_BASE__INST5_SEG1                      0
0451 #define FUSE_BASE__INST5_SEG2                      0
0452 #define FUSE_BASE__INST5_SEG3                      0
0453 #define FUSE_BASE__INST5_SEG4                      0
0454 #define FUSE_BASE__INST5_SEG5                      0
0455
0456 #define FUSE_BASE__INST6_SEG0                      0
0457 #define FUSE_BASE__INST6_SEG1                      0
0458 #define FUSE_BASE__INST6_SEG2                      0
0459 #define FUSE_BASE__INST6_SEG3                      0
0460 #define FUSE_BASE__INST6_SEG4                      0
0461 #define FUSE_BASE__INST6_SEG5                      0
0462
0463 #define FUSE_BASE__INST7_SEG0                      0
0464 #define FUSE_BASE__INST7_SEG1                      0
0465 #define FUSE_BASE__INST7_SEG2                      0
0466 #define FUSE_BASE__INST7_SEG3                      0
0467 #define FUSE_BASE__INST7_SEG4                      0
0468 #define FUSE_BASE__INST7_SEG5                      0
0469
0470 #define GC_BASE__INST0_SEG0                        0x00002000
0471 #define GC_BASE__INST0_SEG1                        0x0000A000
0472 #define GC_BASE__INST0_SEG2                        0x00012160
0473 #define GC_BASE__INST0_SEG3                        0x00402C00
0474 #define GC_BASE__INST0_SEG4                        0
0475 #define GC_BASE__INST0_SEG5                        0
0476
0477 #define GC_BASE__INST1_SEG0                        0
0478 #define GC_BASE__INST1_SEG1                        0
0479 #define GC_BASE__INST1_SEG2                        0
0480 #define GC_BASE__INST1_SEG3                        0
0481 #define GC_BASE__INST1_SEG4                        0
0482 #define GC_BASE__INST1_SEG5                        0
0483
0484 #define GC_BASE__INST2_SEG0                        0
0485 #define GC_BASE__INST2_SEG1                        0
0486 #define GC_BASE__INST2_SEG2                        0
0487 #define GC_BASE__INST2_SEG3                        0
0488 #define GC_BASE__INST2_SEG4                        0
0489 #define GC_BASE__INST2_SEG5                        0
0490
0491 #define GC_BASE__INST3_SEG0                        0
0492 #define GC_BASE__INST3_SEG1                        0
0493 #define GC_BASE__INST3_SEG2                        0
0494 #define GC_BASE__INST3_SEG3                        0
0495 #define GC_BASE__INST3_SEG4                        0
0496 #define GC_BASE__INST3_SEG5                        0
0497
0498 #define GC_BASE__INST4_SEG0                        0
0499 #define GC_BASE__INST4_SEG1                        0
0500 #define GC_BASE__INST4_SEG2                        0
0501 #define GC_BASE__INST4_SEG3                        0
0502 #define GC_BASE__INST4_SEG4                        0
0503 #define GC_BASE__INST4_SEG5                        0
0504
0505 #define GC_BASE__INST5_SEG0                        0
0506 #define GC_BASE__INST5_SEG1                        0
0507 #define GC_BASE__INST5_SEG2                        0
0508 #define GC_BASE__INST5_SEG3                        0
0509 #define GC_BASE__INST5_SEG4                        0
0510 #define GC_BASE__INST5_SEG5                        0
0511
0512 #define GC_BASE__INST6_SEG0                        0
0513 #define GC_BASE__INST6_SEG1                        0
0514 #define GC_BASE__INST6_SEG2                        0
0515 #define GC_BASE__INST6_SEG3                        0
0516 #define GC_BASE__INST6_SEG4                        0
0517 #define GC_BASE__INST6_SEG5                        0
0518
0519 #define GC_BASE__INST7_SEG0                        0
0520 #define GC_BASE__INST7_SEG1                        0
0521 #define GC_BASE__INST7_SEG2                        0
0522 #define GC_BASE__INST7_SEG3                        0
0523 #define GC_BASE__INST7_SEG4                        0
0524 #define GC_BASE__INST7_SEG5                        0
0525
0526 #define HDP_BASE__INST0_SEG0                       0x00000F20
0527 #define HDP_BASE__INST0_SEG1                       0x00012520
0528 #define HDP_BASE__INST0_SEG2                       0x0040A400
0529 #define HDP_BASE__INST0_SEG3                       0
0530 #define HDP_BASE__INST0_SEG4                       0
0531 #define HDP_BASE__INST0_SEG5                       0
0532
0533 #define HDP_BASE__INST1_SEG0                       0
0534 #define HDP_BASE__INST1_SEG1                       0
0535 #define HDP_BASE__INST1_SEG2                       0
0536 #define HDP_BASE__INST1_SEG3                       0
0537 #define HDP_BASE__INST1_SEG4                       0
0538 #define HDP_BASE__INST1_SEG5                       0
0539
0540 #define HDP_BASE__INST2_SEG0                       0
0541 #define HDP_BASE__INST2_SEG1                       0
0542 #define HDP_BASE__INST2_SEG2                       0
0543 #define HDP_BASE__INST2_SEG3                       0
0544 #define HDP_BASE__INST2_SEG4                       0
0545 #define HDP_BASE__INST2_SEG5                       0
0546
0547 #define HDP_BASE__INST3_SEG0                       0
0548 #define HDP_BASE__INST3_SEG1                       0
0549 #define HDP_BASE__INST3_SEG2                       0
0550 #define HDP_BASE__INST3_SEG3                       0
0551 #define HDP_BASE__INST3_SEG4                       0
0552 #define HDP_BASE__INST3_SEG5                       0
0553
0554 #define HDP_BASE__INST4_SEG0                       0
0555 #define HDP_BASE__INST4_SEG1                       0
0556 #define HDP_BASE__INST4_SEG2                       0
0557 #define HDP_BASE__INST4_SEG3                       0
0558 #define HDP_BASE__INST4_SEG4                       0
0559 #define HDP_BASE__INST4_SEG5                       0
0560
0561 #define HDP_BASE__INST5_SEG0                       0
0562 #define HDP_BASE__INST5_SEG1                       0
0563 #define HDP_BASE__INST5_SEG2                       0
0564 #define HDP_BASE__INST5_SEG3                       0
0565 #define HDP_BASE__INST5_SEG4                       0
0566 #define HDP_BASE__INST5_SEG5                       0
0567
0568 #define HDP_BASE__INST6_SEG0                       0
0569 #define HDP_BASE__INST6_SEG1                       0
0570 #define HDP_BASE__INST6_SEG2                       0
0571 #define HDP_BASE__INST6_SEG3                       0
0572 #define HDP_BASE__INST6_SEG4                       0
0573 #define HDP_BASE__INST6_SEG5                       0
0574
0575 #define HDP_BASE__INST7_SEG0                       0
0576 #define HDP_BASE__INST7_SEG1                       0
0577 #define HDP_BASE__INST7_SEG2                       0
0578 #define HDP_BASE__INST7_SEG3                       0
0579 #define HDP_BASE__INST7_SEG4                       0
0580 #define HDP_BASE__INST7_SEG5                       0
0581
0582 #define MMHUB_BASE__INST0_SEG0                     0x00012440
0583 #define MMHUB_BASE__INST0_SEG1                     0x0001A000
0584 #define MMHUB_BASE__INST0_SEG2                     0x00408800
0585 #define MMHUB_BASE__INST0_SEG3                     0
0586 #define MMHUB_BASE__INST0_SEG4                     0
0587 #define MMHUB_BASE__INST0_SEG5                     0
0588
0589 #define MMHUB_BASE__INST1_SEG0                     0
0590 #define MMHUB_BASE__INST1_SEG1                     0
0591 #define MMHUB_BASE__INST1_SEG2                     0
0592 #define MMHUB_BASE__INST1_SEG3                     0
0593 #define MMHUB_BASE__INST1_SEG4                     0
0594 #define MMHUB_BASE__INST1_SEG5                     0
0595
0596 #define MMHUB_BASE__INST2_SEG0                     0
0597 #define MMHUB_BASE__INST2_SEG1                     0
0598 #define MMHUB_BASE__INST2_SEG2                     0
0599 #define MMHUB_BASE__INST2_SEG3                     0
0600 #define MMHUB_BASE__INST2_SEG4                     0
0601 #define MMHUB_BASE__INST2_SEG5                     0
0602
0603 #define MMHUB_BASE__INST3_SEG0                     0
0604 #define MMHUB_BASE__INST3_SEG1                     0
0605 #define MMHUB_BASE__INST3_SEG2                     0
0606 #define MMHUB_BASE__INST3_SEG3                     0
0607 #define MMHUB_BASE__INST3_SEG4                     0
0608 #define MMHUB_BASE__INST3_SEG5                     0
0609
0610 #define MMHUB_BASE__INST4_SEG0                     0
0611 #define MMHUB_BASE__INST4_SEG1                     0
0612 #define MMHUB_BASE__INST4_SEG2                     0
0613 #define MMHUB_BASE__INST4_SEG3                     0
0614 #define MMHUB_BASE__INST4_SEG4                     0
0615 #define MMHUB_BASE__INST4_SEG5                     0
0616
0617 #define MMHUB_BASE__INST5_SEG0                     0
0618 #define MMHUB_BASE__INST5_SEG1                     0
0619 #define MMHUB_BASE__INST5_SEG2                     0
0620 #define MMHUB_BASE__INST5_SEG3                     0
0621 #define MMHUB_BASE__INST5_SEG4                     0
0622 #define MMHUB_BASE__INST5_SEG5                     0
0623
0624 #define MMHUB_BASE__INST6_SEG0                     0
0625 #define MMHUB_BASE__INST6_SEG1                     0
0626 #define MMHUB_BASE__INST6_SEG2                     0
0627 #define MMHUB_BASE__INST6_SEG3                     0
0628 #define MMHUB_BASE__INST6_SEG4                     0
0629 #define MMHUB_BASE__INST6_SEG5                     0
0630
0631 #define MMHUB_BASE__INST7_SEG0                     0
0632 #define MMHUB_BASE__INST7_SEG1                     0
0633 #define MMHUB_BASE__INST7_SEG2                     0
0634 #define MMHUB_BASE__INST7_SEG3                     0
0635 #define MMHUB_BASE__INST7_SEG4                     0
0636 #define MMHUB_BASE__INST7_SEG5                     0
0637
0638 #define MP0_BASE__INST0_SEG0                       0x00013FE0
0639 #define MP0_BASE__INST0_SEG1                       0x00016000
0640 #define MP0_BASE__INST0_SEG2                       0x0043FC00
0641 #define MP0_BASE__INST0_SEG3                       0x00DC0000
0642 #define MP0_BASE__INST0_SEG4                       0x00E00000
0643 #define MP0_BASE__INST0_SEG5                       0x00E40000
0644
0645 #define MP0_BASE__INST1_SEG0                       0
0646 #define MP0_BASE__INST1_SEG1                       0
0647 #define MP0_BASE__INST1_SEG2                       0
0648 #define MP0_BASE__INST1_SEG3                       0
0649 #define MP0_BASE__INST1_SEG4                       0
0650 #define MP0_BASE__INST1_SEG5                       0
0651
0652 #define MP0_BASE__INST2_SEG0                       0
0653 #define MP0_BASE__INST2_SEG1                       0
0654 #define MP0_BASE__INST2_SEG2                       0
0655 #define MP0_BASE__INST2_SEG3                       0
0656 #define MP0_BASE__INST2_SEG4                       0
0657 #define MP0_BASE__INST2_SEG5                       0
0658
0659 #define MP0_BASE__INST3_SEG0                       0
0660 #define MP0_BASE__INST3_SEG1                       0
0661 #define MP0_BASE__INST3_SEG2                       0
0662 #define MP0_BASE__INST3_SEG3                       0
0663 #define MP0_BASE__INST3_SEG4                       0
0664 #define MP0_BASE__INST3_SEG5                       0
0665
0666 #define MP0_BASE__INST4_SEG0                       0
0667 #define MP0_BASE__INST4_SEG1                       0
0668 #define MP0_BASE__INST4_SEG2                       0
0669 #define MP0_BASE__INST4_SEG3                       0
0670 #define MP0_BASE__INST4_SEG4                       0
0671 #define MP0_BASE__INST4_SEG5                       0
0672
0673 #define MP0_BASE__INST5_SEG0                       0
0674 #define MP0_BASE__INST5_SEG1                       0
0675 #define MP0_BASE__INST5_SEG2                       0
0676 #define MP0_BASE__INST5_SEG3                       0
0677 #define MP0_BASE__INST5_SEG4                       0
0678 #define MP0_BASE__INST5_SEG5                       0
0679
0680 #define MP0_BASE__INST6_SEG0                       0
0681 #define MP0_BASE__INST6_SEG1                       0
0682 #define MP0_BASE__INST6_SEG2                       0
0683 #define MP0_BASE__INST6_SEG3                       0
0684 #define MP0_BASE__INST6_SEG4                       0
0685 #define MP0_BASE__INST6_SEG5                       0
0686
0687 #define MP0_BASE__INST7_SEG0                       0
0688 #define MP0_BASE__INST7_SEG1                       0
0689 #define MP0_BASE__INST7_SEG2                       0
0690 #define MP0_BASE__INST7_SEG3                       0
0691 #define MP0_BASE__INST7_SEG4                       0
0692 #define MP0_BASE__INST7_SEG5                       0
0693
0694 #define MP1_BASE__INST0_SEG0                       0x00012020
0695 #define MP1_BASE__INST0_SEG1                       0x00016200
0696 #define MP1_BASE__INST0_SEG2                       0x00400400
0697 #define MP1_BASE__INST0_SEG3                       0x00E80000
0698 #define MP1_BASE__INST0_SEG4                       0x00EC0000
0699 #define MP1_BASE__INST0_SEG5                       0x00F00000
0700
0701 #define MP1_BASE__INST1_SEG0                       0
0702 #define MP1_BASE__INST1_SEG1                       0
0703 #define MP1_BASE__INST1_SEG2                       0
0704 #define MP1_BASE__INST1_SEG3                       0
0705 #define MP1_BASE__INST1_SEG4                       0
0706 #define MP1_BASE__INST1_SEG5                       0
0707
0708 #define MP1_BASE__INST2_SEG0                       0
0709 #define MP1_BASE__INST2_SEG1                       0
0710 #define MP1_BASE__INST2_SEG2                       0
0711 #define MP1_BASE__INST2_SEG3                       0
0712 #define MP1_BASE__INST2_SEG4                       0
0713 #define MP1_BASE__INST2_SEG5                       0
0714
0715 #define MP1_BASE__INST3_SEG0                       0
0716 #define MP1_BASE__INST3_SEG1                       0
0717 #define MP1_BASE__INST3_SEG2                       0
0718 #define MP1_BASE__INST3_SEG3                       0
0719 #define MP1_BASE__INST3_SEG4                       0
0720 #define MP1_BASE__INST3_SEG5                       0
0721
0722 #define MP1_BASE__INST4_SEG0                       0
0723 #define MP1_BASE__INST4_SEG1                       0
0724 #define MP1_BASE__INST4_SEG2                       0
0725 #define MP1_BASE__INST4_SEG3                       0
0726 #define MP1_BASE__INST4_SEG4                       0
0727 #define MP1_BASE__INST4_SEG5                       0
0728
0729 #define MP1_BASE__INST5_SEG0                       0
0730 #define MP1_BASE__INST5_SEG1                       0
0731 #define MP1_BASE__INST5_SEG2                       0
0732 #define MP1_BASE__INST5_SEG3                       0
0733 #define MP1_BASE__INST5_SEG4                       0
0734 #define MP1_BASE__INST5_SEG5                       0
0735
0736 #define MP1_BASE__INST6_SEG0                       0
0737 #define MP1_BASE__INST6_SEG1                       0
0738 #define MP1_BASE__INST6_SEG2                       0
0739 #define MP1_BASE__INST6_SEG3                       0
0740 #define MP1_BASE__INST6_SEG4                       0
0741 #define MP1_BASE__INST6_SEG5                       0
0742
0743 #define MP1_BASE__INST7_SEG0                       0
0744 #define MP1_BASE__INST7_SEG1                       0
0745 #define MP1_BASE__INST7_SEG2                       0
0746 #define MP1_BASE__INST7_SEG3                       0
0747 #define MP1_BASE__INST7_SEG4                       0
0748 #define MP1_BASE__INST7_SEG5                       0
0749
0750 #define NBIF0_BASE__INST0_SEG0                     0x00000000
0751 #define NBIF0_BASE__INST0_SEG1                     0x00000014
0752 #define NBIF0_BASE__INST0_SEG2                     0x00000D20
0753 #define NBIF0_BASE__INST0_SEG3                     0x00010400
0754 #define NBIF0_BASE__INST0_SEG4                     0x00012D80
0755 #define NBIF0_BASE__INST0_SEG5                     0x0041B000
0756
0757 #define NBIF0_BASE__INST1_SEG0                     0
0758 #define NBIF0_BASE__INST1_SEG1                     0
0759 #define NBIF0_BASE__INST1_SEG2                     0
0760 #define NBIF0_BASE__INST1_SEG3                     0
0761 #define NBIF0_BASE__INST1_SEG4                     0
0762 #define NBIF0_BASE__INST1_SEG5                     0
0763
0764 #define NBIF0_BASE__INST2_SEG0                     0
0765 #define NBIF0_BASE__INST2_SEG1                     0
0766 #define NBIF0_BASE__INST2_SEG2                     0
0767 #define NBIF0_BASE__INST2_SEG3                     0
0768 #define NBIF0_BASE__INST2_SEG4                     0
0769 #define NBIF0_BASE__INST2_SEG5                     0
0770
0771 #define NBIF0_BASE__INST3_SEG0                     0
0772 #define NBIF0_BASE__INST3_SEG1                     0
0773 #define NBIF0_BASE__INST3_SEG2                     0
0774 #define NBIF0_BASE__INST3_SEG3                     0
0775 #define NBIF0_BASE__INST3_SEG4                     0
0776 #define NBIF0_BASE__INST3_SEG5                     0
0777
0778 #define NBIF0_BASE__INST4_SEG0                     0
0779 #define NBIF0_BASE__INST4_SEG1                     0
0780 #define NBIF0_BASE__INST4_SEG2                     0
0781 #define NBIF0_BASE__INST4_SEG3                     0
0782 #define NBIF0_BASE__INST4_SEG4                     0
0783 #define NBIF0_BASE__INST4_SEG5                     0
0784
0785 #define NBIF0_BASE__INST5_SEG0                     0
0786 #define NBIF0_BASE__INST5_SEG1                     0
0787 #define NBIF0_BASE__INST5_SEG2                     0
0788 #define NBIF0_BASE__INST5_SEG3                     0
0789 #define NBIF0_BASE__INST5_SEG4                     0
0790 #define NBIF0_BASE__INST5_SEG5                     0
0791
0792 #define NBIF0_BASE__INST6_SEG0                     0
0793 #define NBIF0_BASE__INST6_SEG1                     0
0794 #define NBIF0_BASE__INST6_SEG2                     0
0795 #define NBIF0_BASE__INST6_SEG3                     0
0796 #define NBIF0_BASE__INST6_SEG4                     0
0797 #define NBIF0_BASE__INST6_SEG5                     0
0798
0799 #define NBIF0_BASE__INST7_SEG0                     0
0800 #define NBIF0_BASE__INST7_SEG1                     0
0801 #define NBIF0_BASE__INST7_SEG2                     0
0802 #define NBIF0_BASE__INST7_SEG3                     0
0803 #define NBIF0_BASE__INST7_SEG4                     0
0804 #define NBIF0_BASE__INST7_SEG5                     0
0805
0806 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
0807 #define OSSSYS_BASE__INST0_SEG1                    0x00012500
0808 #define OSSSYS_BASE__INST0_SEG2                    0x0040A000
0809 #define OSSSYS_BASE__INST0_SEG3                    0
0810 #define OSSSYS_BASE__INST0_SEG4                    0
0811 #define OSSSYS_BASE__INST0_SEG5                    0
0812
0813 #define OSSSYS_BASE__INST1_SEG0                    0
0814 #define OSSSYS_BASE__INST1_SEG1                    0
0815 #define OSSSYS_BASE__INST1_SEG2                    0
0816 #define OSSSYS_BASE__INST1_SEG3                    0
0817 #define OSSSYS_BASE__INST1_SEG4                    0
0818 #define OSSSYS_BASE__INST1_SEG5                    0
0819
0820 #define OSSSYS_BASE__INST2_SEG0                    0
0821 #define OSSSYS_BASE__INST2_SEG1                    0
0822 #define OSSSYS_BASE__INST2_SEG2                    0
0823 #define OSSSYS_BASE__INST2_SEG3                    0
0824 #define OSSSYS_BASE__INST2_SEG4                    0
0825 #define OSSSYS_BASE__INST2_SEG5                    0
0826
0827 #define OSSSYS_BASE__INST3_SEG0                    0
0828 #define OSSSYS_BASE__INST3_SEG1                    0
0829 #define OSSSYS_BASE__INST3_SEG2                    0
0830 #define OSSSYS_BASE__INST3_SEG3                    0
0831 #define OSSSYS_BASE__INST3_SEG4                    0
0832 #define OSSSYS_BASE__INST3_SEG5                    0
0833
0834 #define OSSSYS_BASE__INST4_SEG0                    0
0835 #define OSSSYS_BASE__INST4_SEG1                    0
0836 #define OSSSYS_BASE__INST4_SEG2                    0
0837 #define OSSSYS_BASE__INST4_SEG3                    0
0838 #define OSSSYS_BASE__INST4_SEG4                    0
0839 #define OSSSYS_BASE__INST4_SEG5                    0
0840
0841 #define OSSSYS_BASE__INST5_SEG0                    0
0842 #define OSSSYS_BASE__INST5_SEG1                    0
0843 #define OSSSYS_BASE__INST5_SEG2                    0
0844 #define OSSSYS_BASE__INST5_SEG3                    0
0845 #define OSSSYS_BASE__INST5_SEG4                    0
0846 #define OSSSYS_BASE__INST5_SEG5                    0
0847
0848 #define OSSSYS_BASE__INST6_SEG0                    0
0849 #define OSSSYS_BASE__INST6_SEG1                    0
0850 #define OSSSYS_BASE__INST6_SEG2                    0
0851 #define OSSSYS_BASE__INST6_SEG3                    0
0852 #define OSSSYS_BASE__INST6_SEG4                    0
0853 #define OSSSYS_BASE__INST6_SEG5                    0
0854
0855 #define OSSSYS_BASE__INST7_SEG0                    0
0856 #define OSSSYS_BASE__INST7_SEG1                    0
0857 #define OSSSYS_BASE__INST7_SEG2                    0
0858 #define OSSSYS_BASE__INST7_SEG3                    0
0859 #define OSSSYS_BASE__INST7_SEG4                    0
0860 #define OSSSYS_BASE__INST7_SEG5                    0
0861
0862 #define PCIE0_BASE__INST0_SEG0                     0x000128C0
0863 #define PCIE0_BASE__INST0_SEG1                     0x00411800
0864 #define PCIE0_BASE__INST0_SEG2                     0x04440000
0865 #define PCIE0_BASE__INST0_SEG3                     0
0866 #define PCIE0_BASE__INST0_SEG4                     0
0867 #define PCIE0_BASE__INST0_SEG5                     0
0868
0869 #define PCIE0_BASE__INST1_SEG0                     0
0870 #define PCIE0_BASE__INST1_SEG1                     0
0871 #define PCIE0_BASE__INST1_SEG2                     0
0872 #define PCIE0_BASE__INST1_SEG3                     0
0873 #define PCIE0_BASE__INST1_SEG4                     0
0874 #define PCIE0_BASE__INST1_SEG5                     0
0875
0876 #define PCIE0_BASE__INST2_SEG0                     0
0877 #define PCIE0_BASE__INST2_SEG1                     0
0878 #define PCIE0_BASE__INST2_SEG2                     0
0879 #define PCIE0_BASE__INST2_SEG3                     0
0880 #define PCIE0_BASE__INST2_SEG4                     0
0881 #define PCIE0_BASE__INST2_SEG5                     0
0882
0883 #define PCIE0_BASE__INST3_SEG0                     0
0884 #define PCIE0_BASE__INST3_SEG1                     0
0885 #define PCIE0_BASE__INST3_SEG2                     0
0886 #define PCIE0_BASE__INST3_SEG3                     0
0887 #define PCIE0_BASE__INST3_SEG4                     0
0888 #define PCIE0_BASE__INST3_SEG5                     0
0889
0890 #define PCIE0_BASE__INST4_SEG0                     0
0891 #define PCIE0_BASE__INST4_SEG1                     0
0892 #define PCIE0_BASE__INST4_SEG2                     0
0893 #define PCIE0_BASE__INST4_SEG3                     0
0894 #define PCIE0_BASE__INST4_SEG4                     0
0895 #define PCIE0_BASE__INST4_SEG5                     0
0896
0897 #define PCIE0_BASE__INST5_SEG0                     0
0898 #define PCIE0_BASE__INST5_SEG1                     0
0899 #define PCIE0_BASE__INST5_SEG2                     0
0900 #define PCIE0_BASE__INST5_SEG3                     0
0901 #define PCIE0_BASE__INST5_SEG4                     0
0902 #define PCIE0_BASE__INST5_SEG5                     0
0903
0904 #define PCIE0_BASE__INST6_SEG0                     0
0905 #define PCIE0_BASE__INST6_SEG1                     0
0906 #define PCIE0_BASE__INST6_SEG2                     0
0907 #define PCIE0_BASE__INST6_SEG3                     0
0908 #define PCIE0_BASE__INST6_SEG4                     0
0909 #define PCIE0_BASE__INST6_SEG5                     0
0910
0911 #define PCIE0_BASE__INST7_SEG0                     0
0912 #define PCIE0_BASE__INST7_SEG1                     0
0913 #define PCIE0_BASE__INST7_SEG2                     0
0914 #define PCIE0_BASE__INST7_SEG3                     0
0915 #define PCIE0_BASE__INST7_SEG4                     0
0916 #define PCIE0_BASE__INST7_SEG5                     0
0917
0918 #define SDMA0_BASE__INST0_SEG0                     0x00001260
0919 #define SDMA0_BASE__INST0_SEG1                     0x00012540
0920 #define SDMA0_BASE__INST0_SEG2                     0x0040A800
0921 #define SDMA0_BASE__INST0_SEG3                     0
0922 #define SDMA0_BASE__INST0_SEG4                     0
0923 #define SDMA0_BASE__INST0_SEG5                     0
0924
0925 #define SDMA0_BASE__INST1_SEG0                     0
0926 #define SDMA0_BASE__INST1_SEG1                     0
0927 #define SDMA0_BASE__INST1_SEG2                     0
0928 #define SDMA0_BASE__INST1_SEG3                     0
0929 #define SDMA0_BASE__INST1_SEG4                     0
0930 #define SDMA0_BASE__INST1_SEG5                     0
0931
0932 #define SDMA0_BASE__INST2_SEG0                     0
0933 #define SDMA0_BASE__INST2_SEG1                     0
0934 #define SDMA0_BASE__INST2_SEG2                     0
0935 #define SDMA0_BASE__INST2_SEG3                     0
0936 #define SDMA0_BASE__INST2_SEG4                     0
0937 #define SDMA0_BASE__INST2_SEG5                     0
0938
0939 #define SDMA0_BASE__INST3_SEG0                     0
0940 #define SDMA0_BASE__INST3_SEG1                     0
0941 #define SDMA0_BASE__INST3_SEG2                     0
0942 #define SDMA0_BASE__INST3_SEG3                     0
0943 #define SDMA0_BASE__INST3_SEG4                     0
0944 #define SDMA0_BASE__INST3_SEG5                     0
0945
0946 #define SDMA0_BASE__INST4_SEG0                     0
0947 #define SDMA0_BASE__INST4_SEG1                     0
0948 #define SDMA0_BASE__INST4_SEG2                     0
0949 #define SDMA0_BASE__INST4_SEG3                     0
0950 #define SDMA0_BASE__INST4_SEG4                     0
0951 #define SDMA0_BASE__INST4_SEG5                     0
0952
0953 #define SDMA0_BASE__INST5_SEG0                     0
0954 #define SDMA0_BASE__INST5_SEG1                     0
0955 #define SDMA0_BASE__INST5_SEG2                     0
0956 #define SDMA0_BASE__INST5_SEG3                     0
0957 #define SDMA0_BASE__INST5_SEG4                     0
0958 #define SDMA0_BASE__INST5_SEG5                     0
0959
0960 #define SDMA0_BASE__INST6_SEG0                     0
0961 #define SDMA0_BASE__INST6_SEG1                     0
0962 #define SDMA0_BASE__INST6_SEG2                     0
0963 #define SDMA0_BASE__INST6_SEG3                     0
0964 #define SDMA0_BASE__INST6_SEG4                     0
0965 #define SDMA0_BASE__INST6_SEG5                     0
0966
0967 #define SDMA1_BASE__INST0_SEG0                     0x00001860
0968 #define SDMA1_BASE__INST0_SEG1                     0x00012560
0969 #define SDMA1_BASE__INST0_SEG2                     0x0040AC00
0970 #define SDMA1_BASE__INST0_SEG3                     0
0971 #define SDMA1_BASE__INST0_SEG4                     0
0972 #define SDMA1_BASE__INST0_SEG5                     0
0973
0974 #define SDMA1_BASE__INST1_SEG0                     0
0975 #define SDMA1_BASE__INST1_SEG1                     0
0976 #define SDMA1_BASE__INST1_SEG2                     0
0977 #define SDMA1_BASE__INST1_SEG3                     0
0978 #define SDMA1_BASE__INST1_SEG4                     0
0979 #define SDMA1_BASE__INST1_SEG5                     0
0980
0981 #define SDMA1_BASE__INST2_SEG0                     0
0982 #define SDMA1_BASE__INST2_SEG1                     0
0983 #define SDMA1_BASE__INST2_SEG2                     0
0984 #define SDMA1_BASE__INST2_SEG3                     0
0985 #define SDMA1_BASE__INST2_SEG4                     0
0986 #define SDMA1_BASE__INST2_SEG5                     0
0987
0988 #define SDMA1_BASE__INST3_SEG0                     0
0989 #define SDMA1_BASE__INST3_SEG1                     0
0990 #define SDMA1_BASE__INST3_SEG2                     0
0991 #define SDMA1_BASE__INST3_SEG3                     0
0992 #define SDMA1_BASE__INST3_SEG4                     0
0993 #define SDMA1_BASE__INST3_SEG5                     0
0994
0995 #define SDMA1_BASE__INST4_SEG0                     0
0996 #define SDMA1_BASE__INST4_SEG1                     0
0997 #define SDMA1_BASE__INST4_SEG2                     0
0998 #define SDMA1_BASE__INST4_SEG3                     0
0999 #define SDMA1_BASE__INST4_SEG4                     0
1000 #define SDMA1_BASE__INST4_SEG5                     0
1001
1002 #define SDMA1_BASE__INST5_SEG0                     0
1003 #define SDMA1_BASE__INST5_SEG1                     0
1004 #define SDMA1_BASE__INST5_SEG2                     0
1005 #define SDMA1_BASE__INST5_SEG3                     0
1006 #define SDMA1_BASE__INST5_SEG4                     0
1007 #define SDMA1_BASE__INST5_SEG5                     0
1008
1009
1010 #define SDMA1_BASE__INST6_SEG0                     0
1011 #define SDMA1_BASE__INST6_SEG1                     0
1012 #define SDMA1_BASE__INST6_SEG2                     0
1013 #define SDMA1_BASE__INST6_SEG3                     0
1014 #define SDMA1_BASE__INST6_SEG4                     0
1015 #define SDMA1_BASE__INST6_SEG5                     0
1016
1017
1018 #define SDMA2_BASE__INST0_SEG0                     0x00013760
1019 #define SDMA2_BASE__INST0_SEG1                     0x0001E000
1020 #define SDMA2_BASE__INST0_SEG2                     0x0042EC00
1021 #define SDMA2_BASE__INST0_SEG3                     0
1022 #define SDMA2_BASE__INST0_SEG4                     0
1023 #define SDMA2_BASE__INST0_SEG5                     0
1024
1025
1026 #define SDMA2_BASE__INST1_SEG0                     0
1027 #define SDMA2_BASE__INST1_SEG1                     0
1028 #define SDMA2_BASE__INST1_SEG2                     0
1029 #define SDMA2_BASE__INST1_SEG3                     0
1030 #define SDMA2_BASE__INST1_SEG4                     0
1031 #define SDMA2_BASE__INST1_SEG5                     0
1032
1033 #define SDMA2_BASE__INST2_SEG0                     0
1034 #define SDMA2_BASE__INST2_SEG1                     0
1035 #define SDMA2_BASE__INST2_SEG2                     0
1036 #define SDMA2_BASE__INST2_SEG3                     0
1037 #define SDMA2_BASE__INST2_SEG4                     0
1038 #define SDMA2_BASE__INST2_SEG5                     0
1039
1040 #define SDMA2_BASE__INST3_SEG0                     0
1041 #define SDMA2_BASE__INST3_SEG1                     0
1042 #define SDMA2_BASE__INST3_SEG2                     0
1043 #define SDMA2_BASE__INST3_SEG3                     0
1044 #define SDMA2_BASE__INST3_SEG4                     0
1045 #define SDMA2_BASE__INST3_SEG5                     0
1046
1047 #define SDMA2_BASE__INST4_SEG0                     0
1048 #define SDMA2_BASE__INST4_SEG1                     0
1049 #define SDMA2_BASE__INST4_SEG2                     0
1050 #define SDMA2_BASE__INST4_SEG3                     0
1051 #define SDMA2_BASE__INST4_SEG4                     0
1052 #define SDMA2_BASE__INST4_SEG5                     0
1053
1054 #define SDMA2_BASE__INST5_SEG0                     0
1055 #define SDMA2_BASE__INST5_SEG1                     0
1056 #define SDMA2_BASE__INST5_SEG2                     0
1057 #define SDMA2_BASE__INST5_SEG3                     0
1058 #define SDMA2_BASE__INST5_SEG4                     0
1059 #define SDMA2_BASE__INST5_SEG5                     0
1060
1061 #define SDMA2_BASE__INST6_SEG0                     0
1062 #define SDMA2_BASE__INST6_SEG1                     0
1063 #define SDMA2_BASE__INST6_SEG2                     0
1064 #define SDMA2_BASE__INST6_SEG3                     0
1065 #define SDMA2_BASE__INST6_SEG4                     0
1066 #define SDMA2_BASE__INST6_SEG5                     0
1067
1068 #define SDMA3_BASE__INST0_SEG0                     0x00013780
1069 #define SDMA3_BASE__INST0_SEG1                     0x0001E400
1070 #define SDMA3_BASE__INST0_SEG2                     0x0042F000
1071 #define SDMA3_BASE__INST0_SEG3                     0
1072 #define SDMA3_BASE__INST0_SEG4                     0
1073 #define SDMA3_BASE__INST0_SEG5                     0
1074
1075 #define SDMA3_BASE__INST1_SEG0                     0
1076 #define SDMA3_BASE__INST1_SEG1                     0
1077 #define SDMA3_BASE__INST1_SEG2                     0
1078 #define SDMA3_BASE__INST1_SEG3                     0
1079 #define SDMA3_BASE__INST1_SEG4                     0
1080 #define SDMA3_BASE__INST1_SEG5                     0
1081
1082 #define SDMA3_BASE__INST2_SEG0                     0
1083 #define SDMA3_BASE__INST2_SEG1                     0
1084 #define SDMA3_BASE__INST2_SEG2                     0
1085 #define SDMA3_BASE__INST2_SEG3                     0
1086 #define SDMA3_BASE__INST2_SEG4                     0
1087 #define SDMA3_BASE__INST2_SEG5                     0
1088
1089 #define SDMA3_BASE__INST3_SEG0                     0
1090 #define SDMA3_BASE__INST3_SEG1                     0
1091 #define SDMA3_BASE__INST3_SEG2                     0
1092 #define SDMA3_BASE__INST3_SEG3                     0
1093 #define SDMA3_BASE__INST3_SEG4                     0
1094 #define SDMA3_BASE__INST3_SEG5                     0
1095
1096 #define SDMA3_BASE__INST4_SEG0                     0
1097 #define SDMA3_BASE__INST4_SEG1                     0
1098 #define SDMA3_BASE__INST4_SEG2                     0
1099 #define SDMA3_BASE__INST4_SEG3                     0
1100 #define SDMA3_BASE__INST4_SEG4                     0
1101 #define SDMA3_BASE__INST4_SEG5                     0
1102
1103 #define SDMA3_BASE__INST5_SEG0                     0
1104 #define SDMA3_BASE__INST5_SEG1                     0
1105 #define SDMA3_BASE__INST5_SEG2                     0
1106 #define SDMA3_BASE__INST5_SEG3                     0
1107 #define SDMA3_BASE__INST5_SEG4                     0
1108 #define SDMA3_BASE__INST5_SEG5                     0
1109
1110 #define SDMA3_BASE__INST6_SEG0                     0
1111 #define SDMA3_BASE__INST6_SEG1                     0
1112 #define SDMA3_BASE__INST6_SEG2                     0
1113 #define SDMA3_BASE__INST6_SEG3                     0
1114 #define SDMA3_BASE__INST6_SEG4                     0
1115 #define SDMA3_BASE__INST6_SEG5                     0
1116
1117 #define SDMA4_BASE__INST0_SEG0                     0x000137A0
1118 #define SDMA4_BASE__INST0_SEG1                     0x0001E800
1119 #define SDMA4_BASE__INST0_SEG2                     0x0042F400
1120 #define SDMA4_BASE__INST0_SEG3                     0
1121 #define SDMA4_BASE__INST0_SEG4                     0
1122 #define SDMA4_BASE__INST0_SEG5                     0
1123
1124 #define SDMA4_BASE__INST1_SEG0                     0
1125 #define SDMA4_BASE__INST1_SEG1                     0
1126 #define SDMA4_BASE__INST1_SEG2                     0
1127 #define SDMA4_BASE__INST1_SEG3                     0
1128 #define SDMA4_BASE__INST1_SEG4                     0
1129 #define SDMA4_BASE__INST1_SEG5                     0
1130
1131 #define SDMA4_BASE__INST2_SEG0                     0
1132 #define SDMA4_BASE__INST2_SEG1                     0
1133 #define SDMA4_BASE__INST2_SEG2                     0
1134 #define SDMA4_BASE__INST2_SEG3                     0
1135 #define SDMA4_BASE__INST2_SEG4                     0
1136 #define SDMA4_BASE__INST2_SEG5                     0
1137
1138 #define SDMA4_BASE__INST3_SEG0                     0
1139 #define SDMA4_BASE__INST3_SEG1                     0
1140 #define SDMA4_BASE__INST3_SEG2                     0
1141 #define SDMA4_BASE__INST3_SEG3                     0
1142 #define SDMA4_BASE__INST3_SEG4                     0
1143 #define SDMA4_BASE__INST3_SEG5                     0
1144
1145 #define SDMA4_BASE__INST4_SEG0                     0
1146 #define SDMA4_BASE__INST4_SEG1                     0
1147 #define SDMA4_BASE__INST4_SEG2                     0
1148 #define SDMA4_BASE__INST4_SEG3                     0
1149 #define SDMA4_BASE__INST4_SEG4                     0
1150 #define SDMA4_BASE__INST4_SEG5                     0
1151
1152 #define SDMA4_BASE__INST5_SEG0                     0
1153 #define SDMA4_BASE__INST5_SEG1                     0
1154 #define SDMA4_BASE__INST5_SEG2                     0
1155 #define SDMA4_BASE__INST5_SEG3                     0
1156 #define SDMA4_BASE__INST5_SEG4                     0
1157 #define SDMA4_BASE__INST5_SEG5                     0
1158
1159 #define SDMA4_BASE__INST6_SEG0                     0
1160 #define SDMA4_BASE__INST6_SEG1                     0
1161 #define SDMA4_BASE__INST6_SEG2                     0
1162 #define SDMA4_BASE__INST6_SEG3                     0
1163 #define SDMA4_BASE__INST6_SEG4                     0
1164 #define SDMA4_BASE__INST6_SEG5                     0
1165
1166 #define SDMA5_BASE__INST0_SEG0                     0x000137C0
1167 #define SDMA5_BASE__INST0_SEG1                     0x0001EC00
1168 #define SDMA5_BASE__INST0_SEG2                     0x0042F800
1169 #define SDMA5_BASE__INST0_SEG3                     0
1170 #define SDMA5_BASE__INST0_SEG4                     0
1171 #define SDMA5_BASE__INST0_SEG5                     0
1172
1173 #define SDMA5_BASE__INST1_SEG0                     0
1174 #define SDMA5_BASE__INST1_SEG1                     0
1175 #define SDMA5_BASE__INST1_SEG2                     0
1176 #define SDMA5_BASE__INST1_SEG3                     0
1177 #define SDMA5_BASE__INST1_SEG4                     0
1178 #define SDMA5_BASE__INST1_SEG5                     0
1179
1180 #define SDMA5_BASE__INST2_SEG0                     0
1181 #define SDMA5_BASE__INST2_SEG1                     0
1182 #define SDMA5_BASE__INST2_SEG2                     0
1183 #define SDMA5_BASE__INST2_SEG3                     0
1184 #define SDMA5_BASE__INST2_SEG4                     0
1185 #define SDMA5_BASE__INST2_SEG5                     0
1186
1187 #define SDMA5_BASE__INST3_SEG0                     0
1188 #define SDMA5_BASE__INST3_SEG1                     0
1189 #define SDMA5_BASE__INST3_SEG2                     0
1190 #define SDMA5_BASE__INST3_SEG3                     0
1191 #define SDMA5_BASE__INST3_SEG4                     0
1192 #define SDMA5_BASE__INST3_SEG5                     0
1193
1194 #define SDMA5_BASE__INST4_SEG0                     0
1195 #define SDMA5_BASE__INST4_SEG1                     0
1196 #define SDMA5_BASE__INST4_SEG2                     0
1197 #define SDMA5_BASE__INST4_SEG3                     0
1198 #define SDMA5_BASE__INST4_SEG4                     0
1199 #define SDMA5_BASE__INST4_SEG5                     0
1200
1201 #define SDMA5_BASE__INST5_SEG0                     0
1202 #define SDMA5_BASE__INST5_SEG1                     0
1203 #define SDMA5_BASE__INST5_SEG2                     0
1204 #define SDMA5_BASE__INST5_SEG3                     0
1205 #define SDMA5_BASE__INST5_SEG4                     0
1206 #define SDMA5_BASE__INST5_SEG5                     0
1207
1208 #define SDMA5_BASE__INST6_SEG0                     0
1209 #define SDMA5_BASE__INST6_SEG1                     0
1210 #define SDMA5_BASE__INST6_SEG2                     0
1211 #define SDMA5_BASE__INST6_SEG3                     0
1212 #define SDMA5_BASE__INST6_SEG4                     0
1213 #define SDMA5_BASE__INST6_SEG5                     0
1214
1215 #define SDMA6_BASE__INST0_SEG0                     0x000137E0
1216 #define SDMA6_BASE__INST0_SEG1                     0x0001F000
1217 #define SDMA6_BASE__INST0_SEG2                     0x0042FC00
1218 #define SDMA6_BASE__INST0_SEG3                     0
1219 #define SDMA6_BASE__INST0_SEG4                     0
1220 #define SDMA6_BASE__INST0_SEG5                     0
1221
1222 #define SDMA6_BASE__INST1_SEG0                     0
1223 #define SDMA6_BASE__INST1_SEG1                     0
1224 #define SDMA6_BASE__INST1_SEG2                     0
1225 #define SDMA6_BASE__INST1_SEG3                     0
1226 #define SDMA6_BASE__INST1_SEG4                     0
1227 #define SDMA6_BASE__INST1_SEG5                     0
1228
1229 #define SDMA6_BASE__INST2_SEG0                     0
1230 #define SDMA6_BASE__INST2_SEG1                     0
1231 #define SDMA6_BASE__INST2_SEG2                     0
1232 #define SDMA6_BASE__INST2_SEG3                     0
1233 #define SDMA6_BASE__INST2_SEG4                     0
1234 #define SDMA6_BASE__INST2_SEG5                     0
1235
1236 #define SDMA6_BASE__INST3_SEG0                     0
1237 #define SDMA6_BASE__INST3_SEG1                     0
1238 #define SDMA6_BASE__INST3_SEG2                     0
1239 #define SDMA6_BASE__INST3_SEG3                     0
1240 #define SDMA6_BASE__INST3_SEG4                     0
1241 #define SDMA6_BASE__INST3_SEG5                     0
1242
1243 #define SDMA6_BASE__INST4_SEG0                     0
1244 #define SDMA6_BASE__INST4_SEG1                     0
1245 #define SDMA6_BASE__INST4_SEG2                     0
1246 #define SDMA6_BASE__INST4_SEG3                     0
1247 #define SDMA6_BASE__INST4_SEG4                     0
1248 #define SDMA6_BASE__INST4_SEG5                     0
1249
1250 #define SDMA6_BASE__INST5_SEG0                     0
1251 #define SDMA6_BASE__INST5_SEG1                     0
1252 #define SDMA6_BASE__INST5_SEG2                     0
1253 #define SDMA6_BASE__INST5_SEG3                     0
1254 #define SDMA6_BASE__INST5_SEG4                     0
1255 #define SDMA6_BASE__INST5_SEG5                     0
1256
1257 #define SDMA6_BASE__INST6_SEG0                     0
1258 #define SDMA6_BASE__INST6_SEG1                     0
1259 #define SDMA6_BASE__INST6_SEG2                     0
1260 #define SDMA6_BASE__INST6_SEG3                     0
1261 #define SDMA6_BASE__INST6_SEG4                     0
1262 #define SDMA6_BASE__INST6_SEG5                     0
1263
1264 #define SDMA7_BASE__INST0_SEG0                     0x00013800
1265 #define SDMA7_BASE__INST0_SEG1                     0x0001F400
1266 #define SDMA7_BASE__INST0_SEG2                     0x00430000
1267 #define SDMA7_BASE__INST0_SEG3                     0
1268 #define SDMA7_BASE__INST0_SEG4                     0
1269 #define SDMA7_BASE__INST0_SEG5                     0
1270
1271 #define SDMA7_BASE__INST1_SEG0                     0
1272 #define SDMA7_BASE__INST1_SEG1                     0
1273 #define SDMA7_BASE__INST1_SEG2                     0
1274 #define SDMA7_BASE__INST1_SEG3                     0
1275 #define SDMA7_BASE__INST1_SEG4                     0
1276 #define SDMA7_BASE__INST1_SEG5                     0
1277
1278 #define SDMA7_BASE__INST2_SEG0                     0
1279 #define SDMA7_BASE__INST2_SEG1                     0
1280 #define SDMA7_BASE__INST2_SEG2                     0
1281 #define SDMA7_BASE__INST2_SEG3                     0
1282 #define SDMA7_BASE__INST2_SEG4                     0
1283 #define SDMA7_BASE__INST2_SEG5                     0
1284
1285 #define SDMA7_BASE__INST3_SEG0                     0
1286 #define SDMA7_BASE__INST3_SEG1                     0
1287 #define SDMA7_BASE__INST3_SEG2                     0
1288 #define SDMA7_BASE__INST3_SEG3                     0
1289 #define SDMA7_BASE__INST3_SEG4                     0
1290 #define SDMA7_BASE__INST3_SEG5                     0
1291
1292 #define SDMA7_BASE__INST4_SEG0                     0
1293 #define SDMA7_BASE__INST4_SEG1                     0
1294 #define SDMA7_BASE__INST4_SEG2                     0
1295 #define SDMA7_BASE__INST4_SEG3                     0
1296 #define SDMA7_BASE__INST4_SEG4                     0
1297 #define SDMA7_BASE__INST4_SEG5                     0
1298
1299 #define SDMA7_BASE__INST5_SEG0                     0
1300 #define SDMA7_BASE__INST5_SEG1                     0
1301 #define SDMA7_BASE__INST5_SEG2                     0
1302 #define SDMA7_BASE__INST5_SEG3                     0
1303 #define SDMA7_BASE__INST5_SEG4                     0
1304 #define SDMA7_BASE__INST5_SEG5                     0
1305
1306 #define SDMA7_BASE__INST6_SEG0                     0
1307 #define SDMA7_BASE__INST6_SEG1                     0
1308 #define SDMA7_BASE__INST6_SEG2                     0
1309 #define SDMA7_BASE__INST6_SEG3                     0
1310 #define SDMA7_BASE__INST6_SEG4                     0
1311 #define SDMA7_BASE__INST6_SEG5                     0
1312
1313 #define SMUIO_BASE__INST0_SEG0                     0x00012080
1314 #define SMUIO_BASE__INST0_SEG1                     0x00016800
1315 #define SMUIO_BASE__INST0_SEG2                     0x00016A00
1316 #define SMUIO_BASE__INST0_SEG3                     0x00401000
1317 #define SMUIO_BASE__INST0_SEG4                     0x00440000
1318 #define SMUIO_BASE__INST0_SEG5                     0
1319
1320 #define SMUIO_BASE__INST1_SEG0                     0
1321 #define SMUIO_BASE__INST1_SEG1                     0
1322 #define SMUIO_BASE__INST1_SEG2                     0
1323 #define SMUIO_BASE__INST1_SEG3                     0
1324 #define SMUIO_BASE__INST1_SEG4                     0
1325 #define SMUIO_BASE__INST1_SEG5                     0
1326
1327 #define SMUIO_BASE__INST2_SEG0                     0
1328 #define SMUIO_BASE__INST2_SEG1                     0
1329 #define SMUIO_BASE__INST2_SEG2                     0
1330 #define SMUIO_BASE__INST2_SEG3                     0
1331 #define SMUIO_BASE__INST2_SEG4                     0
1332 #define SMUIO_BASE__INST2_SEG5                     0
1333
1334 #define SMUIO_BASE__INST3_SEG0                     0
1335 #define SMUIO_BASE__INST3_SEG1                     0
1336 #define SMUIO_BASE__INST3_SEG2                     0
1337 #define SMUIO_BASE__INST3_SEG3                     0
1338 #define SMUIO_BASE__INST3_SEG4                     0
1339 #define SMUIO_BASE__INST3_SEG5                     0
1340
1341 #define SMUIO_BASE__INST4_SEG0                     0
1342 #define SMUIO_BASE__INST4_SEG1                     0
1343 #define SMUIO_BASE__INST4_SEG2                     0
1344 #define SMUIO_BASE__INST4_SEG3                     0
1345 #define SMUIO_BASE__INST4_SEG4                     0
1346 #define SMUIO_BASE__INST4_SEG5                     0
1347
1348 #define SMUIO_BASE__INST5_SEG0                     0
1349 #define SMUIO_BASE__INST5_SEG1                     0
1350 #define SMUIO_BASE__INST5_SEG2                     0
1351 #define SMUIO_BASE__INST5_SEG3                     0
1352 #define SMUIO_BASE__INST5_SEG4                     0
1353 #define SMUIO_BASE__INST5_SEG5                     0
1354
1355 #define SMUIO_BASE__INST6_SEG0                     0
1356 #define SMUIO_BASE__INST6_SEG1                     0
1357 #define SMUIO_BASE__INST6_SEG2                     0
1358 #define SMUIO_BASE__INST6_SEG3                     0
1359 #define SMUIO_BASE__INST6_SEG4                     0
1360 #define SMUIO_BASE__INST6_SEG5                     0
1361
1362 #define SMUIO_BASE__INST7_SEG0                     0
1363 #define SMUIO_BASE__INST7_SEG1                     0
1364 #define SMUIO_BASE__INST7_SEG2                     0
1365 #define SMUIO_BASE__INST7_SEG3                     0
1366 #define SMUIO_BASE__INST7_SEG4                     0
1367 #define SMUIO_BASE__INST7_SEG5                     0
1368
1369 #define THM_BASE__INST0_SEG0                       0x00012060
1370 #define THM_BASE__INST0_SEG1                       0x00016600
1371 #define THM_BASE__INST0_SEG2                       0x00400C00
1372 #define THM_BASE__INST0_SEG3                       0
1373 #define THM_BASE__INST0_SEG4                       0
1374 #define THM_BASE__INST0_SEG5                       0
1375
1376 #define THM_BASE__INST1_SEG0                       0
1377 #define THM_BASE__INST1_SEG1                       0
1378 #define THM_BASE__INST1_SEG2                       0
1379 #define THM_BASE__INST1_SEG3                       0
1380 #define THM_BASE__INST1_SEG4                       0
1381 #define THM_BASE__INST1_SEG5                       0
1382
1383 #define THM_BASE__INST2_SEG0                       0
1384 #define THM_BASE__INST2_SEG1                       0
1385 #define THM_BASE__INST2_SEG2                       0
1386 #define THM_BASE__INST2_SEG3                       0
1387 #define THM_BASE__INST2_SEG4                       0
1388 #define THM_BASE__INST2_SEG5                       0
1389
1390 #define THM_BASE__INST3_SEG0                       0
1391 #define THM_BASE__INST3_SEG1                       0
1392 #define THM_BASE__INST3_SEG2                       0
1393 #define THM_BASE__INST3_SEG3                       0
1394 #define THM_BASE__INST3_SEG4                       0
1395 #define THM_BASE__INST3_SEG5                       0
1396
1397 #define THM_BASE__INST4_SEG0                       0
1398 #define THM_BASE__INST4_SEG1                       0
1399 #define THM_BASE__INST4_SEG2                       0
1400 #define THM_BASE__INST4_SEG3                       0
1401 #define THM_BASE__INST4_SEG4                       0
1402 #define THM_BASE__INST4_SEG5                       0
1403
1404 #define THM_BASE__INST5_SEG0                       0
1405 #define THM_BASE__INST5_SEG1                       0
1406 #define THM_BASE__INST5_SEG2                       0
1407 #define THM_BASE__INST5_SEG3                       0
1408 #define THM_BASE__INST5_SEG4                       0
1409 #define THM_BASE__INST5_SEG5                       0
1410
1411 #define THM_BASE__INST6_SEG0                       0
1412 #define THM_BASE__INST6_SEG1                       0
1413 #define THM_BASE__INST6_SEG2                       0
1414 #define THM_BASE__INST6_SEG3                       0
1415 #define THM_BASE__INST6_SEG4                       0
1416 #define THM_BASE__INST6_SEG5                       0
1417
1418 #define THM_BASE__INST7_SEG0                       0
1419 #define THM_BASE__INST7_SEG1                       0
1420 #define THM_BASE__INST7_SEG2                       0
1421 #define THM_BASE__INST7_SEG3                       0
1422 #define THM_BASE__INST7_SEG4                       0
1423 #define THM_BASE__INST7_SEG5                       0
1424
1425 #define UMC_BASE__INST0_SEG0                       0x000132C0
1426 #define UMC_BASE__INST0_SEG1                       0x00014000
1427 #define UMC_BASE__INST0_SEG2                       0x00425800
1428 #define UMC_BASE__INST0_SEG3                       0
1429 #define UMC_BASE__INST0_SEG4                       0
1430 #define UMC_BASE__INST0_SEG5                       0
1431
1432 #define UMC_BASE__INST1_SEG0                       0x000132E0
1433 #define UMC_BASE__INST1_SEG1                       0x00054000
1434 #define UMC_BASE__INST1_SEG2                       0x00425C00
1435 #define UMC_BASE__INST1_SEG3                       0
1436 #define UMC_BASE__INST1_SEG4                       0
1437 #define UMC_BASE__INST1_SEG5                       0
1438
1439 #define UMC_BASE__INST2_SEG0                       0x00013300
1440 #define UMC_BASE__INST2_SEG1                       0x00094000
1441 #define UMC_BASE__INST2_SEG2                       0x00426000
1442 #define UMC_BASE__INST2_SEG3                       0
1443 #define UMC_BASE__INST2_SEG4                       0
1444 #define UMC_BASE__INST2_SEG5                       0
1445
1446 #define UMC_BASE__INST3_SEG0                       0x00013320
1447 #define UMC_BASE__INST3_SEG1                       0x000D4000
1448 #define UMC_BASE__INST3_SEG2                       0x00426400
1449 #define UMC_BASE__INST3_SEG3                       0
1450 #define UMC_BASE__INST3_SEG4                       0
1451 #define UMC_BASE__INST3_SEG5                       0
1452
1453 #define UMC_BASE__INST4_SEG0                       0x00013340
1454 #define UMC_BASE__INST4_SEG1                       0x00114000
1455 #define UMC_BASE__INST4_SEG2                       0x00426800
1456 #define UMC_BASE__INST4_SEG3                       0
1457 #define UMC_BASE__INST4_SEG4                       0
1458 #define UMC_BASE__INST4_SEG5                       0
1459
1460 #define UMC_BASE__INST5_SEG0                       0x00013360
1461 #define UMC_BASE__INST5_SEG1                       0x00154000
1462 #define UMC_BASE__INST5_SEG2                       0x00426C00
1463 #define UMC_BASE__INST5_SEG3                       0
1464 #define UMC_BASE__INST5_SEG4                       0
1465 #define UMC_BASE__INST5_SEG5                       0
1466
1467 #define UMC_BASE__INST6_SEG0                       0x00013380
1468 #define UMC_BASE__INST6_SEG1                       0x00194000
1469 #define UMC_BASE__INST6_SEG2                       0x00427000
1470 #define UMC_BASE__INST6_SEG3                       0
1471 #define UMC_BASE__INST6_SEG4                       0
1472 #define UMC_BASE__INST6_SEG5                       0
1473
1474 #define UMC_BASE__INST7_SEG0                       0x000133A0
1475 #define UMC_BASE__INST7_SEG1                       0x001D4000
1476 #define UMC_BASE__INST7_SEG2                       0x00427400
1477 #define UMC_BASE__INST7_SEG3                       0
1478 #define UMC_BASE__INST7_SEG4                       0
1479 #define UMC_BASE__INST7_SEG5                       0
1480
1481 #define UVD_BASE__INST0_SEG0                       0x00007800
1482 #define UVD_BASE__INST0_SEG1                       0x00007E00
1483 #define UVD_BASE__INST0_SEG2                       0x00012180
1484 #define UVD_BASE__INST0_SEG3                       0x00403000
1485 #define UVD_BASE__INST0_SEG4                       0
1486 #define UVD_BASE__INST0_SEG5                       0
1487
1488 #define UVD_BASE__INST1_SEG0                       0x00007A00
1489 #define UVD_BASE__INST1_SEG1                       0x00009000
1490 #define UVD_BASE__INST1_SEG2                       0x000136E0
1491 #define UVD_BASE__INST1_SEG3                       0x0042DC00
1492 #define UVD_BASE__INST1_SEG4                       0
1493 #define UVD_BASE__INST1_SEG5                       0
1494
1495 #define UVD_BASE__INST2_SEG0                       0
1496 #define UVD_BASE__INST2_SEG1                       0
1497 #define UVD_BASE__INST2_SEG2                       0
1498 #define UVD_BASE__INST2_SEG3                       0
1499 #define UVD_BASE__INST2_SEG4                       0
1500 #define UVD_BASE__INST2_SEG5                       0
1501
1502 #define UVD_BASE__INST3_SEG0                       0
1503 #define UVD_BASE__INST3_SEG1                       0
1504 #define UVD_BASE__INST3_SEG2                       0
1505 #define UVD_BASE__INST3_SEG3                       0
1506 #define UVD_BASE__INST3_SEG4                       0
1507 #define UVD_BASE__INST3_SEG5                       0
1508
1509 #define UVD_BASE__INST4_SEG0                       0
1510 #define UVD_BASE__INST4_SEG1                       0
1511 #define UVD_BASE__INST4_SEG2                       0
1512 #define UVD_BASE__INST4_SEG3                       0
1513 #define UVD_BASE__INST4_SEG4                       0
1514 #define UVD_BASE__INST4_SEG5                       0
1515
1516 #define UVD_BASE__INST5_SEG0                       0
1517 #define UVD_BASE__INST5_SEG1                       0
1518 #define UVD_BASE__INST5_SEG2                       0
1519 #define UVD_BASE__INST5_SEG3                       0
1520 #define UVD_BASE__INST5_SEG4                       0
1521 #define UVD_BASE__INST5_SEG5                       0
1522
1523 #define UVD_BASE__INST6_SEG0                       0
1524 #define UVD_BASE__INST6_SEG1                       0
1525 #define UVD_BASE__INST6_SEG2                       0
1526 #define UVD_BASE__INST6_SEG3                       0
1527 #define UVD_BASE__INST6_SEG4                       0
1528 #define UVD_BASE__INST6_SEG5                       0
1529
1530 #define UVD_BASE__INST7_SEG0                       0
1531 #define UVD_BASE__INST7_SEG1                       0
1532 #define UVD_BASE__INST7_SEG2                       0
1533 #define UVD_BASE__INST7_SEG3                       0
1534 #define UVD_BASE__INST7_SEG4                       0
1535 #define UVD_BASE__INST7_SEG5                       0
1536
1537 #define DBGU_IO_BASE__INST0_SEG0                   0x000001E0
1538 #define DBGU_IO_BASE__INST0_SEG1                   0x000125A0
1539 #define DBGU_IO_BASE__INST0_SEG2                   0x0040B400
1540 #define DBGU_IO_BASE__INST0_SEG3                   0
1541 #define DBGU_IO_BASE__INST0_SEG4                   0
1542 #define DBGU_IO_BASE__INST0_SEG5                   0
1543
1544 #define DBGU_IO_BASE__INST1_SEG0                   0
1545 #define DBGU_IO_BASE__INST1_SEG1                   0
1546 #define DBGU_IO_BASE__INST1_SEG2                   0
1547 #define DBGU_IO_BASE__INST1_SEG3                   0
1548 #define DBGU_IO_BASE__INST1_SEG4                   0
1549 #define DBGU_IO_BASE__INST1_SEG5                   0
1550
1551 #define DBGU_IO_BASE__INST2_SEG0                   0
1552 #define DBGU_IO_BASE__INST2_SEG1                   0
1553 #define DBGU_IO_BASE__INST2_SEG2                   0
1554 #define DBGU_IO_BASE__INST2_SEG3                   0
1555 #define DBGU_IO_BASE__INST2_SEG4                   0
1556 #define DBGU_IO_BASE__INST2_SEG5                   0
1557
1558 #define DBGU_IO_BASE__INST3_SEG0                   0
1559 #define DBGU_IO_BASE__INST3_SEG1                   0
1560 #define DBGU_IO_BASE__INST3_SEG2                   0
1561 #define DBGU_IO_BASE__INST3_SEG3                   0
1562 #define DBGU_IO_BASE__INST3_SEG4                   0
1563 #define DBGU_IO_BASE__INST3_SEG5                   0
1564
1565 #define DBGU_IO_BASE__INST4_SEG0                   0
1566 #define DBGU_IO_BASE__INST4_SEG1                   0
1567 #define DBGU_IO_BASE__INST4_SEG2                   0
1568 #define DBGU_IO_BASE__INST4_SEG3                   0
1569 #define DBGU_IO_BASE__INST4_SEG4                   0
1570 #define DBGU_IO_BASE__INST4_SEG5                   0
1571
1572 #define DBGU_IO_BASE__INST5_SEG0                   0
1573 #define DBGU_IO_BASE__INST5_SEG1                   0
1574 #define DBGU_IO_BASE__INST5_SEG2                   0
1575 #define DBGU_IO_BASE__INST5_SEG3                   0
1576 #define DBGU_IO_BASE__INST5_SEG4                   0
1577 #define DBGU_IO_BASE__INST5_SEG5                   0
1578
1579 #define DBGU_IO_BASE__INST6_SEG0                   0
1580 #define DBGU_IO_BASE__INST6_SEG1                   0
1581 #define DBGU_IO_BASE__INST6_SEG2                   0
1582 #define DBGU_IO_BASE__INST6_SEG3                   0
1583 #define DBGU_IO_BASE__INST6_SEG4                   0
1584 #define DBGU_IO_BASE__INST6_SEG5                   0
1585
1586 #define DBGU_IO_BASE__INST7_SEG0                   0
1587 #define DBGU_IO_BASE__INST7_SEG1                   0
1588 #define DBGU_IO_BASE__INST7_SEG2                   0
1589 #define DBGU_IO_BASE__INST7_SEG3                   0
1590 #define DBGU_IO_BASE__INST7_SEG4                   0
1591 #define DBGU_IO_BASE__INST7_SEG5                   0
1592
1593 #define RSMU_BASE__INST0_SEG0                   0x00012000
1594 #define RSMU_BASE__INST0_SEG1                   0
1595 #define RSMU_BASE__INST0_SEG2                   0
1596 #define RSMU_BASE__INST0_SEG3                   0
1597 #define RSMU_BASE__INST0_SEG4                   0
1598 #define RSMU_BASE__INST0_SEG5                   0
1599
1600 #define RSMU_BASE__INST1_SEG0                   0
1601 #define RSMU_BASE__INST1_SEG1                   0
1602 #define RSMU_BASE__INST1_SEG2                   0
1603 #define RSMU_BASE__INST1_SEG3                   0
1604 #define RSMU_BASE__INST1_SEG4                   0
1605 #define RSMU_BASE__INST1_SEG5                   0
1606
1607 #define RSMU_BASE__INST2_SEG0                   0
1608 #define RSMU_BASE__INST2_SEG1                   0
1609 #define RSMU_BASE__INST2_SEG2                   0
1610 #define RSMU_BASE__INST2_SEG3                   0
1611 #define RSMU_BASE__INST2_SEG4                   0
1612 #define RSMU_BASE__INST2_SEG5                   0
1613
1614 #define RSMU_BASE__INST3_SEG0                   0
1615 #define RSMU_BASE__INST3_SEG1                   0
1616 #define RSMU_BASE__INST3_SEG2                   0
1617 #define RSMU_BASE__INST3_SEG3                   0
1618 #define RSMU_BASE__INST3_SEG4                   0
1619 #define RSMU_BASE__INST3_SEG5                   0
1620
1621 #define RSMU_BASE__INST4_SEG0                   0
1622 #define RSMU_BASE__INST4_SEG1                   0
1623 #define RSMU_BASE__INST4_SEG2                   0
1624 #define RSMU_BASE__INST4_SEG3                   0
1625 #define RSMU_BASE__INST4_SEG4                   0
1626 #define RSMU_BASE__INST4_SEG5                   0
1627
1628 #define RSMU_BASE__INST5_SEG0                   0
1629 #define RSMU_BASE__INST5_SEG1                   0
1630 #define RSMU_BASE__INST5_SEG2                   0
1631 #define RSMU_BASE__INST5_SEG3                   0
1632 #define RSMU_BASE__INST5_SEG4                   0
1633 #define RSMU_BASE__INST5_SEG5                   0
1634
1635 #define RSMU_BASE__INST6_SEG0                   0
1636 #define RSMU_BASE__INST6_SEG1                   0
1637 #define RSMU_BASE__INST6_SEG2                   0
1638 #define RSMU_BASE__INST6_SEG3                   0
1639 #define RSMU_BASE__INST6_SEG4                   0
1640 #define RSMU_BASE__INST6_SEG5                   0
1641
1642 #define RSMU_BASE__INST7_SEG0                   0
1643 #define RSMU_BASE__INST7_SEG1                   0
1644 #define RSMU_BASE__INST7_SEG2                   0
1645 #define RSMU_BASE__INST7_SEG3                   0
1646 #define RSMU_BASE__INST7_SEG4                   0
1647 #define RSMU_BASE__INST7_SEG5                   0
1648
1649
1650 #endif