amd/include/amd_shared.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #ifndef __AMD_SHARED_H__
0024 #define __AMD_SHARED_H__
0025
0026 #include <drm/amd_asic_type.h>
0027
0028
0029 #define AMD_MAX_USEC_TIMEOUT        1000000  /* 1000 ms */
0030
0031 /*
0032  * Chip flags
0033  */
0034 enum amd_chip_flags {
0035     AMD_ASIC_MASK = 0x0000ffffUL,
0036     AMD_FLAGS_MASK  = 0xffff0000UL,
0037     AMD_IS_MOBILITY = 0x00010000UL,
0038     AMD_IS_APU      = 0x00020000UL,
0039     AMD_IS_PX       = 0x00040000UL,
0040     AMD_EXP_HW_SUPPORT = 0x00080000UL,
0041 };
0042
0043 enum amd_apu_flags {
0044     AMD_APU_IS_RAVEN = 0x00000001UL,
0045     AMD_APU_IS_RAVEN2 = 0x00000002UL,
0046     AMD_APU_IS_PICASSO = 0x00000004UL,
0047     AMD_APU_IS_RENOIR = 0x00000008UL,
0048     AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
0049     AMD_APU_IS_VANGOGH = 0x00000020UL,
0050     AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
0051 };
0052
0053 /**
0054 * DOC: IP Blocks
0055 *
0056 * GPUs are composed of IP (intellectual property) blocks. These
0057 * IP blocks provide various functionalities: display, graphics,
0058 * video decode, etc. The IP blocks that comprise a particular GPU
0059 * are listed in the GPU's respective SoC file. amdgpu_device.c
0060 * acquires the list of IP blocks for the GPU in use on initialization.
0061 * It can then operate on this list to perform standard driver operations
0062 * such as: init, fini, suspend, resume, etc.
0063 *
0064 *
0065 * IP block implementations are named using the following convention:
0066 * <functionality>_v<version> (E.g.: gfx_v6_0).
0067 */
0068
0069 /**
0070 * enum amd_ip_block_type - Used to classify IP blocks by functionality.
0071 *
0072 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
0073 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
0074 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
0075 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
0076 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
0077 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
0078 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
0079 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
0080 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
0081 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
0082 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
0083 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
0084 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
0085 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
0086 * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
0087 */
0088 enum amd_ip_block_type {
0089     AMD_IP_BLOCK_TYPE_COMMON,
0090     AMD_IP_BLOCK_TYPE_GMC,
0091     AMD_IP_BLOCK_TYPE_IH,
0092     AMD_IP_BLOCK_TYPE_SMC,
0093     AMD_IP_BLOCK_TYPE_PSP,
0094     AMD_IP_BLOCK_TYPE_DCE,
0095     AMD_IP_BLOCK_TYPE_GFX,
0096     AMD_IP_BLOCK_TYPE_SDMA,
0097     AMD_IP_BLOCK_TYPE_UVD,
0098     AMD_IP_BLOCK_TYPE_VCE,
0099     AMD_IP_BLOCK_TYPE_ACP,
0100     AMD_IP_BLOCK_TYPE_VCN,
0101     AMD_IP_BLOCK_TYPE_MES,
0102     AMD_IP_BLOCK_TYPE_JPEG,
0103     AMD_IP_BLOCK_TYPE_NUM,
0104 };
0105
0106 enum amd_clockgating_state {
0107     AMD_CG_STATE_GATE = 0,
0108     AMD_CG_STATE_UNGATE,
0109 };
0110
0111
0112 enum amd_powergating_state {
0113     AMD_PG_STATE_GATE = 0,
0114     AMD_PG_STATE_UNGATE,
0115 };
0116
0117
0118 /* CG flags */
0119 #define AMD_CG_SUPPORT_GFX_MGCG         (1ULL << 0)
0120 #define AMD_CG_SUPPORT_GFX_MGLS         (1ULL << 1)
0121 #define AMD_CG_SUPPORT_GFX_CGCG         (1ULL << 2)
0122 #define AMD_CG_SUPPORT_GFX_CGLS         (1ULL << 3)
0123 #define AMD_CG_SUPPORT_GFX_CGTS         (1ULL << 4)
0124 #define AMD_CG_SUPPORT_GFX_CGTS_LS      (1ULL << 5)
0125 #define AMD_CG_SUPPORT_GFX_CP_LS        (1ULL << 6)
0126 #define AMD_CG_SUPPORT_GFX_RLC_LS       (1ULL << 7)
0127 #define AMD_CG_SUPPORT_MC_LS            (1ULL << 8)
0128 #define AMD_CG_SUPPORT_MC_MGCG          (1ULL << 9)
0129 #define AMD_CG_SUPPORT_SDMA_LS          (1ULL << 10)
0130 #define AMD_CG_SUPPORT_SDMA_MGCG        (1ULL << 11)
0131 #define AMD_CG_SUPPORT_BIF_LS           (1ULL << 12)
0132 #define AMD_CG_SUPPORT_UVD_MGCG         (1ULL << 13)
0133 #define AMD_CG_SUPPORT_VCE_MGCG         (1ULL << 14)
0134 #define AMD_CG_SUPPORT_HDP_LS           (1ULL << 15)
0135 #define AMD_CG_SUPPORT_HDP_MGCG         (1ULL << 16)
0136 #define AMD_CG_SUPPORT_ROM_MGCG         (1ULL << 17)
0137 #define AMD_CG_SUPPORT_DRM_LS           (1ULL << 18)
0138 #define AMD_CG_SUPPORT_BIF_MGCG         (1ULL << 19)
0139 #define AMD_CG_SUPPORT_GFX_3D_CGCG      (1ULL << 20)
0140 #define AMD_CG_SUPPORT_GFX_3D_CGLS      (1ULL << 21)
0141 #define AMD_CG_SUPPORT_DRM_MGCG         (1ULL << 22)
0142 #define AMD_CG_SUPPORT_DF_MGCG          (1ULL << 23)
0143 #define AMD_CG_SUPPORT_VCN_MGCG         (1ULL << 24)
0144 #define AMD_CG_SUPPORT_HDP_DS           (1ULL << 25)
0145 #define AMD_CG_SUPPORT_HDP_SD           (1ULL << 26)
0146 #define AMD_CG_SUPPORT_IH_CG            (1ULL << 27)
0147 #define AMD_CG_SUPPORT_ATHUB_LS         (1ULL << 28)
0148 #define AMD_CG_SUPPORT_ATHUB_MGCG       (1ULL << 29)
0149 #define AMD_CG_SUPPORT_JPEG_MGCG        (1ULL << 30)
0150 #define AMD_CG_SUPPORT_GFX_FGCG         (1ULL << 31)
0151 #define AMD_CG_SUPPORT_REPEATER_FGCG        (1ULL << 32)
0152 #define AMD_CG_SUPPORT_GFX_PERF_CLK     (1ULL << 33)
0153 /* PG flags */
0154 #define AMD_PG_SUPPORT_GFX_PG           (1 << 0)
0155 #define AMD_PG_SUPPORT_GFX_SMG          (1 << 1)
0156 #define AMD_PG_SUPPORT_GFX_DMG          (1 << 2)
0157 #define AMD_PG_SUPPORT_UVD          (1 << 3)
0158 #define AMD_PG_SUPPORT_VCE          (1 << 4)
0159 #define AMD_PG_SUPPORT_CP           (1 << 5)
0160 #define AMD_PG_SUPPORT_GDS          (1 << 6)
0161 #define AMD_PG_SUPPORT_RLC_SMU_HS       (1 << 7)
0162 #define AMD_PG_SUPPORT_SDMA         (1 << 8)
0163 #define AMD_PG_SUPPORT_ACP          (1 << 9)
0164 #define AMD_PG_SUPPORT_SAMU         (1 << 10)
0165 #define AMD_PG_SUPPORT_GFX_QUICK_MG     (1 << 11)
0166 #define AMD_PG_SUPPORT_GFX_PIPELINE     (1 << 12)
0167 #define AMD_PG_SUPPORT_MMHUB            (1 << 13)
0168 #define AMD_PG_SUPPORT_VCN          (1 << 14)
0169 #define AMD_PG_SUPPORT_VCN_DPG          (1 << 15)
0170 #define AMD_PG_SUPPORT_ATHUB            (1 << 16)
0171 #define AMD_PG_SUPPORT_JPEG         (1 << 17)
0172 #define AMD_PG_SUPPORT_IH_SRAM_PG       (1 << 18)
0173
0174 /**
0175  * enum PP_FEATURE_MASK - Used to mask power play features.
0176  *
0177  * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
0178  * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
0179  * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
0180  * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
0181  * @PP_POWER_CONTAINMENT_MASK: Power containment.
0182  * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
0183  * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
0184  * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
0185  * @PP_ULV_MASK: Ultra low voltage.
0186  * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
0187  * @PP_CLOCK_STRETCH_MASK: Clock stretching.
0188  * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
0189  * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
0190  * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
0191  * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
0192  * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
0193  * @PP_ACG_MASK: Adaptive clock generator.
0194  * @PP_STUTTER_MODE: Stutter mode.
0195  * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
0196  * @PP_GFX_DCS_MASK: GFX Async DCS.
0197  *
0198  * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
0199  * the kernel's command line parameters. This is usually done through a system's
0200  * boot loader (E.g. GRUB). If manually loading the driver, pass
0201  * ppfeaturemask=<mask> as a modprobe parameter.
0202  */
0203 enum PP_FEATURE_MASK {
0204     PP_SCLK_DPM_MASK = 0x1,
0205     PP_MCLK_DPM_MASK = 0x2,
0206     PP_PCIE_DPM_MASK = 0x4,
0207     PP_SCLK_DEEP_SLEEP_MASK = 0x8,
0208     PP_POWER_CONTAINMENT_MASK = 0x10,
0209     PP_UVD_HANDSHAKE_MASK = 0x20,
0210     PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
0211     PP_VBI_TIME_SUPPORT_MASK = 0x80,
0212     PP_ULV_MASK = 0x100,
0213     PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
0214     PP_CLOCK_STRETCH_MASK = 0x400,
0215     PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
0216     PP_SOCCLK_DPM_MASK = 0x1000,
0217     PP_DCEFCLK_DPM_MASK = 0x2000,
0218     PP_OVERDRIVE_MASK = 0x4000,
0219     PP_GFXOFF_MASK = 0x8000,
0220     PP_ACG_MASK = 0x10000,
0221     PP_STUTTER_MODE = 0x20000,
0222     PP_AVFS_MASK = 0x40000,
0223     PP_GFX_DCS_MASK = 0x80000,
0224 };
0225
0226 enum amd_harvest_ip_mask {
0227     AMD_HARVEST_IP_VCN_MASK = 0x1,
0228     AMD_HARVEST_IP_JPEG_MASK = 0x2,
0229     AMD_HARVEST_IP_DMU_MASK = 0x4,
0230 };
0231
0232 enum DC_FEATURE_MASK {
0233     //Default value can be found at "uint amdgpu_dc_feature_mask"
0234     DC_FBC_MASK = (1 << 0), //0x1, disabled by default
0235     DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default
0236     DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default
0237     DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1
0238     DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default
0239     DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default
0240     DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
0241     DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
0242     DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
0243 };
0244
0245 enum DC_DEBUG_MASK {
0246     DC_DISABLE_PIPE_SPLIT = 0x1,
0247     DC_DISABLE_STUTTER = 0x2,
0248     DC_DISABLE_DSC = 0x4,
0249     DC_DISABLE_CLOCK_GATING = 0x8,
0250     DC_DISABLE_PSR = 0x10,
0251     DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
0252     DC_DISABLE_MPO = 0x40,
0253 };
0254
0255 enum amd_dpm_forced_level;
0256
0257 /**
0258  * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
0259  * @name: Name of IP block
0260  * @early_init: sets up early driver state (pre sw_init),
0261  *              does not configure hw - Optional
0262  * @late_init: sets up late driver/hw state (post hw_init) - Optional
0263  * @sw_init: sets up driver state, does not configure hw
0264  * @sw_fini: tears down driver state, does not configure hw
0265  * @early_fini: tears down stuff before dev detached from driver
0266  * @hw_init: sets up the hw state
0267  * @hw_fini: tears down the hw state
0268  * @late_fini: final cleanup
0269  * @suspend: handles IP specific hw/sw changes for suspend
0270  * @resume: handles IP specific hw/sw changes for resume
0271  * @is_idle: returns current IP block idle status
0272  * @wait_for_idle: poll for idle
0273  * @check_soft_reset: check soft reset the IP block
0274  * @pre_soft_reset: pre soft reset the IP block
0275  * @soft_reset: soft reset the IP block
0276  * @post_soft_reset: post soft reset the IP block
0277  * @set_clockgating_state: enable/disable cg for the IP block
0278  * @set_powergating_state: enable/disable pg for the IP block
0279  * @get_clockgating_state: get current clockgating status
0280  *
0281  * These hooks provide an interface for controlling the operational state
0282  * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
0283  * the driver can make chip-wide state changes by walking this list and
0284  * making calls to hooks from each IP block. This list is ordered to ensure
0285  * that the driver initializes the IP blocks in a safe sequence.
0286  */
0287 struct amd_ip_funcs {
0288     char *name;
0289     int (*early_init)(void *handle);
0290     int (*late_init)(void *handle);
0291     int (*sw_init)(void *handle);
0292     int (*sw_fini)(void *handle);
0293     int (*early_fini)(void *handle);
0294     int (*hw_init)(void *handle);
0295     int (*hw_fini)(void *handle);
0296     void (*late_fini)(void *handle);
0297     int (*suspend)(void *handle);
0298     int (*resume)(void *handle);
0299     bool (*is_idle)(void *handle);
0300     int (*wait_for_idle)(void *handle);
0301     bool (*check_soft_reset)(void *handle);
0302     int (*pre_soft_reset)(void *handle);
0303     int (*soft_reset)(void *handle);
0304     int (*post_soft_reset)(void *handle);
0305     int (*set_clockgating_state)(void *handle,
0306                      enum amd_clockgating_state state);
0307     int (*set_powergating_state)(void *handle,
0308                      enum amd_powergating_state state);
0309     void (*get_clockgating_state)(void *handle, u64 *flags);
0310 };
0311
0312
0313 #endif /* __AMD_SHARED_H__ */