amd/include/amd_pcie_helpers.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #ifndef __AMD_PCIE_HELPERS_H__
0024 #define __AMD_PCIE_HELPERS_H__
0025
0026 #include "amd_pcie.h"
0027
0028 static inline bool is_pcie_gen3_supported(uint32_t pcie_link_speed_cap)
0029 {
0030     if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
0031         return true;
0032
0033     return false;
0034 }
0035
0036 static inline bool is_pcie_gen2_supported(uint32_t pcie_link_speed_cap)
0037 {
0038     if (pcie_link_speed_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
0039         return true;
0040
0041     return false;
0042 }
0043
0044 /* Get the new PCIE speed given the ASIC PCIE Cap and the NewState's requested PCIE speed*/
0045 static inline uint16_t get_pcie_gen_support(uint32_t pcie_link_speed_cap,
0046                         uint16_t ns_pcie_gen)
0047 {
0048     uint32_t asic_pcie_link_speed_cap = (pcie_link_speed_cap &
0049         CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK);
0050     uint32_t sys_pcie_link_speed_cap  = (pcie_link_speed_cap &
0051         CAIL_PCIE_LINK_SPEED_SUPPORT_MASK);
0052
0053     switch (asic_pcie_link_speed_cap) {
0054     case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1:
0055         return PP_PCIEGen1;
0056
0057     case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2:
0058         return PP_PCIEGen2;
0059
0060     case CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3:
0061         return PP_PCIEGen3;
0062
0063     default:
0064         if (is_pcie_gen3_supported(sys_pcie_link_speed_cap) &&
0065             (ns_pcie_gen == PP_PCIEGen3)) {
0066             return PP_PCIEGen3;
0067         } else if (is_pcie_gen2_supported(sys_pcie_link_speed_cap) &&
0068             ((ns_pcie_gen == PP_PCIEGen3) || (ns_pcie_gen == PP_PCIEGen2))) {
0069             return PP_PCIEGen2;
0070         }
0071     }
0072
0073     return PP_PCIEGen1;
0074 }
0075
0076 static inline uint16_t get_pcie_lane_support(uint32_t pcie_lane_width_cap,
0077                          uint16_t ns_pcie_lanes)
0078 {
0079     int i, j;
0080     uint16_t new_pcie_lanes = ns_pcie_lanes;
0081     uint16_t pcie_lanes[7] = {1, 2, 4, 8, 12, 16, 32};
0082
0083     switch (pcie_lane_width_cap) {
0084     case 0:
0085         pr_err("No valid PCIE lane width reported\n");
0086         break;
0087     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
0088         new_pcie_lanes = 1;
0089         break;
0090     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
0091         new_pcie_lanes = 2;
0092         break;
0093     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
0094         new_pcie_lanes = 4;
0095         break;
0096     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
0097         new_pcie_lanes = 8;
0098         break;
0099     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
0100         new_pcie_lanes = 12;
0101         break;
0102     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
0103         new_pcie_lanes = 16;
0104         break;
0105     case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
0106         new_pcie_lanes = 32;
0107         break;
0108     default:
0109         for (i = 0; i < 7; i++) {
0110             if (ns_pcie_lanes == pcie_lanes[i]) {
0111                 if (pcie_lane_width_cap & (0x10000 << i)) {
0112                     break;
0113                 } else {
0114                     for (j = i - 1; j >= 0; j--) {
0115                         if (pcie_lane_width_cap & (0x10000 << j)) {
0116                             new_pcie_lanes = pcie_lanes[j];
0117                             break;
0118                         }
0119                     }
0120
0121                     if (j < 0) {
0122                         for (j = i + 1; j < 7; j++) {
0123                             if (pcie_lane_width_cap & (0x10000 << j)) {
0124                                 new_pcie_lanes = pcie_lanes[j];
0125                                 break;
0126                             }
0127                         }
0128                         if (j > 7)
0129                             pr_err("Cannot find a valid PCIE lane width!\n");
0130                     }
0131                 }
0132                 break;
0133             }
0134         }
0135         break;
0136     }
0137
0138     return new_pcie_lanes;
0139 }
0140
0141 #endif