amd/include/amd_pcie.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #ifndef __AMD_PCIE_H__
0024 #define __AMD_PCIE_H__
0025
0026 /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
0027 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
0028 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
0029 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
0030 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4        0x00080000
0031 #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5        0x00100000
0032 #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
0033 #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
0034
0035 /* Following flags shows PCIe link speed supported by ASIC H/W.*/
0036 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
0037 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
0038 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
0039 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4   0x00000008
0040 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5   0x00000010
0041 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
0042 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
0043
0044 /* gen: chipset 1/2, asic 1/2/3 */
0045 #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
0046                       | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
0047                       | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
0048                       | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
0049                       | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
0050
0051 /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
0052 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
0053 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
0054 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
0055 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
0056 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
0057 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
0058 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
0059 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
0060
0061 /* 1/2/4/8/16 lanes */
0062 #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
0063                       | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
0064                       | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
0065                       | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
0066                       | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
0067
0068 #endif