amd/include/aldebaran_ip_offset.h

0001 /*
0002  * Copyright (C) 2020  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef _aldebaran_ip_offset_HEADER
0022 #define _aldebaran_ip_offset_HEADER
0023
0024 #define MAX_INSTANCE                                        7
0025 #define MAX_SEGMENT                                         6
0026
0027 struct IP_BASE_INSTANCE {
0028     unsigned int segment[MAX_SEGMENT];
0029 };
0030
0031 struct IP_BASE {
0032     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
0033 } __maybe_unused;
0034
0035 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
0036                                         { { 0, 0, 0, 0, 0, 0 } },
0037                                         { { 0, 0, 0, 0, 0, 0 } },
0038                                         { { 0, 0, 0, 0, 0, 0 } },
0039                                         { { 0, 0, 0, 0, 0, 0 } },
0040                                         { { 0, 0, 0, 0, 0, 0 } },
0041                                         { { 0, 0, 0, 0, 0, 0 } } } };
0042 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
0043                                         { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
0044                                         { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
0045                                         { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
0046                                         { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
0047                                         { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
0048                                         { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
0049 static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
0050                                         { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
0051                                         { { 0x00000280, 0x02416000, 0, 0, 0, 0 } },
0052                                         { { 0, 0, 0, 0, 0, 0 } },
0053                                         { { 0, 0, 0, 0, 0, 0 } },
0054                                         { { 0, 0, 0, 0, 0, 0 } },
0055                                         { { 0, 0, 0, 0, 0, 0 } } } };
0056 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x07C00000, 0, 0, 0 } },
0057                                         { { 0, 0, 0, 0, 0, 0 } },
0058                                         { { 0, 0, 0, 0, 0, 0 } },
0059                                         { { 0, 0, 0, 0, 0, 0 } },
0060                                         { { 0, 0, 0, 0, 0, 0 } },
0061                                         { { 0, 0, 0, 0, 0, 0 } },
0062                                         { { 0, 0, 0, 0, 0, 0 } } } };
0063 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
0064                                         { { 0, 0, 0, 0, 0, 0 } },
0065                                         { { 0, 0, 0, 0, 0, 0 } },
0066                                         { { 0, 0, 0, 0, 0, 0 } },
0067                                         { { 0, 0, 0, 0, 0, 0 } },
0068                                         { { 0, 0, 0, 0, 0, 0 } },
0069                                         { { 0, 0, 0, 0, 0, 0 } } } };
0070 static const struct IP_BASE GC_BASE = { { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0, 0 } },
0071                                         { { 0, 0, 0, 0, 0, 0 } },
0072                                         { { 0, 0, 0, 0, 0, 0 } },
0073                                         { { 0, 0, 0, 0, 0, 0 } },
0074                                         { { 0, 0, 0, 0, 0, 0 } },
0075                                         { { 0, 0, 0, 0, 0, 0 } },
0076                                         { { 0, 0, 0, 0, 0, 0 } } } };
0077 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
0078                                         { { 0, 0, 0, 0, 0, 0 } },
0079                                         { { 0, 0, 0, 0, 0, 0 } },
0080                                         { { 0, 0, 0, 0, 0, 0 } },
0081                                         { { 0, 0, 0, 0, 0, 0 } },
0082                                         { { 0, 0, 0, 0, 0, 0 } },
0083                                         { { 0, 0, 0, 0, 0, 0 } } } };
0084 static const struct IP_BASE IOAGR0_BASE = { { { { 0x02419000, 0x056C0000, 0, 0, 0, 0 } },
0085                                         { { 0, 0, 0, 0, 0, 0 } },
0086                                         { { 0, 0, 0, 0, 0, 0 } },
0087                                         { { 0, 0, 0, 0, 0, 0 } },
0088                                         { { 0, 0, 0, 0, 0, 0 } },
0089                                         { { 0, 0, 0, 0, 0, 0 } },
0090                                         { { 0, 0, 0, 0, 0, 0 } } } };
0091 static const struct IP_BASE IOAPIC0_BASE = { { { { 0x00A00000, 0x0241F000, 0x050C0000, 0, 0, 0 } },
0092                                         { { 0, 0, 0, 0, 0, 0 } },
0093                                         { { 0, 0, 0, 0, 0, 0 } },
0094                                         { { 0, 0, 0, 0, 0, 0 } },
0095                                         { { 0, 0, 0, 0, 0, 0 } },
0096                                         { { 0, 0, 0, 0, 0, 0 } },
0097                                         { { 0, 0, 0, 0, 0, 0 } } } };
0098 static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },
0099                                         { { 0, 0, 0, 0, 0, 0 } },
0100                                         { { 0, 0, 0, 0, 0, 0 } },
0101                                         { { 0, 0, 0, 0, 0, 0 } },
0102                                         { { 0, 0, 0, 0, 0, 0 } },
0103                                         { { 0, 0, 0, 0, 0, 0 } },
0104                                         { { 0, 0, 0, 0, 0, 0 } } } };
0105 static const struct IP_BASE L1IMUIOAGR0_BASE = { { { { 0x0240CC00, 0x05200000, 0, 0, 0, 0 } },
0106                                         { { 0, 0, 0, 0, 0, 0 } },
0107                                         { { 0, 0, 0, 0, 0, 0 } },
0108                                         { { 0, 0, 0, 0, 0, 0 } },
0109                                         { { 0, 0, 0, 0, 0, 0 } },
0110                                         { { 0, 0, 0, 0, 0, 0 } },
0111                                         { { 0, 0, 0, 0, 0, 0 } } } };
0112 static const struct IP_BASE L1IMUPCIE0_BASE = { { { { 0x0240C800, 0x051C0000, 0, 0, 0, 0 } },
0113                                         { { 0, 0, 0, 0, 0, 0 } },
0114                                         { { 0, 0, 0, 0, 0, 0 } },
0115                                         { { 0, 0, 0, 0, 0, 0 } },
0116                                         { { 0, 0, 0, 0, 0, 0 } },
0117                                         { { 0, 0, 0, 0, 0, 0 } },
0118                                         { { 0, 0, 0, 0, 0, 0 } } } };
0119 static const struct IP_BASE L2IMU0_BASE = { { { { 0x00007DC0, 0x00900000, 0x02407000, 0x04FC0000, 0x055C0000, 0 } },
0120                                         { { 0, 0, 0, 0, 0, 0 } },
0121                                         { { 0, 0, 0, 0, 0, 0 } },
0122                                         { { 0, 0, 0, 0, 0, 0 } },
0123                                         { { 0, 0, 0, 0, 0, 0 } },
0124                                         { { 0, 0, 0, 0, 0, 0 } },
0125                                         { { 0, 0, 0, 0, 0, 0 } } } };
0126 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
0127                                         { { 0, 0, 0, 0, 0, 0 } },
0128                                         { { 0, 0, 0, 0, 0, 0 } },
0129                                         { { 0, 0, 0, 0, 0, 0 } },
0130                                         { { 0, 0, 0, 0, 0, 0 } },
0131                                         { { 0, 0, 0, 0, 0, 0 } },
0132                                         { { 0, 0, 0, 0, 0, 0 } } } };
0133 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
0134                                         { { 0, 0, 0, 0, 0, 0 } },
0135                                         { { 0, 0, 0, 0, 0, 0 } },
0136                                         { { 0, 0, 0, 0, 0, 0 } },
0137                                         { { 0, 0, 0, 0, 0, 0 } },
0138                                         { { 0, 0, 0, 0, 0, 0 } },
0139                                         { { 0, 0, 0, 0, 0, 0 } } } };
0140 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
0141                                         { { 0, 0, 0, 0, 0, 0 } },
0142                                         { { 0, 0, 0, 0, 0, 0 } },
0143                                         { { 0, 0, 0, 0, 0, 0 } },
0144                                         { { 0, 0, 0, 0, 0, 0 } },
0145                                         { { 0, 0, 0, 0, 0, 0 } },
0146                                         { { 0, 0, 0, 0, 0, 0 } } } };
0147 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
0148                                         { { 0, 0, 0, 0, 0, 0 } },
0149                                         { { 0, 0, 0, 0, 0, 0 } },
0150                                         { { 0, 0, 0, 0, 0, 0 } },
0151                                         { { 0, 0, 0, 0, 0, 0 } },
0152                                         { { 0, 0, 0, 0, 0, 0 } },
0153                                         { { 0, 0, 0, 0, 0, 0 } } } };
0154 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
0155                                         { { 0, 0, 0, 0, 0, 0 } },
0156                                         { { 0, 0, 0, 0, 0, 0 } },
0157                                         { { 0, 0, 0, 0, 0, 0 } },
0158                                         { { 0, 0, 0, 0, 0, 0 } },
0159                                         { { 0, 0, 0, 0, 0, 0 } },
0160                                         { { 0, 0, 0, 0, 0, 0 } } } };
0161 static const struct IP_BASE PCIE0_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },
0162                                         { { 0, 0, 0, 0, 0, 0 } },
0163                                         { { 0, 0, 0, 0, 0, 0 } },
0164                                         { { 0, 0, 0, 0, 0, 0 } },
0165                                         { { 0, 0, 0, 0, 0, 0 } },
0166                                         { { 0, 0, 0, 0, 0, 0 } },
0167                                         { { 0, 0, 0, 0, 0, 0 } } } };
0168 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
0169                                         { { 0, 0, 0, 0, 0, 0 } },
0170                                         { { 0, 0, 0, 0, 0, 0 } },
0171                                         { { 0, 0, 0, 0, 0, 0 } },
0172                                         { { 0, 0, 0, 0, 0, 0 } },
0173                                         { { 0, 0, 0, 0, 0, 0 } },
0174                                         { { 0, 0, 0, 0, 0, 0 } } } };
0175 static const struct IP_BASE SDMA1_BASE = { { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
0176                                         { { 0, 0, 0, 0, 0, 0 } },
0177                                         { { 0, 0, 0, 0, 0, 0 } },
0178                                         { { 0, 0, 0, 0, 0, 0 } },
0179                                         { { 0, 0, 0, 0, 0, 0 } },
0180                                         { { 0, 0, 0, 0, 0, 0 } },
0181                                         { { 0, 0, 0, 0, 0, 0 } } } };
0182 static const struct IP_BASE SDMA2_BASE = { { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
0183                                         { { 0, 0, 0, 0, 0, 0 } },
0184                                         { { 0, 0, 0, 0, 0, 0 } },
0185                                         { { 0, 0, 0, 0, 0, 0 } },
0186                                         { { 0, 0, 0, 0, 0, 0 } },
0187                                         { { 0, 0, 0, 0, 0, 0 } },
0188                                         { { 0, 0, 0, 0, 0, 0 } } } };
0189 static const struct IP_BASE SDMA3_BASE = { { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
0190                                         { { 0, 0, 0, 0, 0, 0 } },
0191                                         { { 0, 0, 0, 0, 0, 0 } },
0192                                         { { 0, 0, 0, 0, 0, 0 } },
0193                                         { { 0, 0, 0, 0, 0, 0 } },
0194                                         { { 0, 0, 0, 0, 0, 0 } },
0195                                         { { 0, 0, 0, 0, 0, 0 } } } };
0196 static const struct IP_BASE SDMA4_BASE = { { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
0197                                         { { 0, 0, 0, 0, 0, 0 } },
0198                                         { { 0, 0, 0, 0, 0, 0 } },
0199                                         { { 0, 0, 0, 0, 0, 0 } },
0200                                         { { 0, 0, 0, 0, 0, 0 } },
0201                                         { { 0, 0, 0, 0, 0, 0 } },
0202                                         { { 0, 0, 0, 0, 0, 0 } } } };
0203 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x03440000, 0, 0 } },
0204                                         { { 0, 0, 0, 0, 0, 0 } },
0205                                         { { 0, 0, 0, 0, 0, 0 } },
0206                                         { { 0, 0, 0, 0, 0, 0 } },
0207                                         { { 0, 0, 0, 0, 0, 0 } },
0208                                         { { 0, 0, 0, 0, 0, 0 } },
0209                                         { { 0, 0, 0, 0, 0, 0 } } } };
0210 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
0211                                         { { 0, 0, 0, 0, 0, 0 } },
0212                                         { { 0, 0, 0, 0, 0, 0 } },
0213                                         { { 0, 0, 0, 0, 0, 0 } },
0214                                         { { 0, 0, 0, 0, 0, 0 } },
0215                                         { { 0, 0, 0, 0, 0, 0 } },
0216                                         { { 0, 0, 0, 0, 0, 0 } } } };
0217 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0, 0, 0 } },
0218                                         { { 0x00094000, 0x000D4000, 0x02425C00, 0, 0, 0 } },
0219                                         { { 0x00114000, 0x00154000, 0x02426000, 0, 0, 0 } },
0220                                         { { 0x00194000, 0x001D4000, 0x02426400, 0, 0, 0 } },
0221                                         { { 0, 0, 0, 0, 0, 0 } },
0222                                         { { 0, 0, 0, 0, 0, 0 } },
0223                                         { { 0, 0, 0, 0, 0, 0 } } } };
0224 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
0225                                         { { 0x00007A00, 0x00009000, 0x02445000, 0, 0, 0 } },
0226                                         { { 0, 0, 0, 0, 0, 0 } },
0227                                         { { 0, 0, 0, 0, 0, 0 } },
0228                                         { { 0, 0, 0, 0, 0, 0 } },
0229                                         { { 0, 0, 0, 0, 0, 0 } },
0230                                         { { 0, 0, 0, 0, 0, 0 } } } };
0231 static const struct IP_BASE WAFL0_BASE = { { { { 0x02438000, 0x04880000, 0, 0, 0, 0 } },
0232                                         { { 0, 0, 0, 0, 0, 0 } },
0233                                         { { 0, 0, 0, 0, 0, 0 } },
0234                                         { { 0, 0, 0, 0, 0, 0 } },
0235                                         { { 0, 0, 0, 0, 0, 0 } },
0236                                         { { 0, 0, 0, 0, 0, 0 } },
0237                                         { { 0, 0, 0, 0, 0, 0 } } } };
0238 static const struct IP_BASE WAFL1_BASE = { { { { 0, 0x01300000, 0x02410800, 0, 0, 0 } },
0239                                         { { 0, 0, 0, 0, 0, 0 } },
0240                                         { { 0, 0, 0, 0, 0, 0 } },
0241                                         { { 0, 0, 0, 0, 0, 0 } },
0242                                         { { 0, 0, 0, 0, 0, 0 } },
0243                                         { { 0, 0, 0, 0, 0, 0 } },
0244                                         { { 0, 0, 0, 0, 0, 0 } } } };
0245 static const struct IP_BASE XGMI0_BASE = { { { { 0x02438C00, 0x04680000, 0x04940000, 0, 0, 0 } },
0246                                         { { 0, 0, 0, 0, 0, 0 } },
0247                                         { { 0, 0, 0, 0, 0, 0 } },
0248                                         { { 0, 0, 0, 0, 0, 0 } },
0249                                         { { 0, 0, 0, 0, 0, 0 } },
0250                                         { { 0, 0, 0, 0, 0, 0 } },
0251                                         { { 0, 0, 0, 0, 0, 0 } } } };
0252 static const struct IP_BASE XGMI1_BASE = { { { { 0x02439000, 0x046C0000, 0x04980000, 0, 0, 0 } },
0253                                         { { 0, 0, 0, 0, 0, 0 } },
0254                                         { { 0, 0, 0, 0, 0, 0 } },
0255                                         { { 0, 0, 0, 0, 0, 0 } },
0256                                         { { 0, 0, 0, 0, 0, 0 } },
0257                                         { { 0, 0, 0, 0, 0, 0 } },
0258                                         { { 0, 0, 0, 0, 0, 0 } } } };
0259 static const struct IP_BASE XGMI2_BASE = { { { { 0x04700000, 0x049C0000, 0, 0, 0, 0 } },
0260                                         { { 0x04740000, 0x04A00000, 0, 0, 0, 0 } },
0261                                         { { 0x04780000, 0x04A40000, 0, 0, 0, 0 } },
0262                                         { { 0x047C0000, 0x04A80000, 0, 0, 0, 0 } },
0263                                         { { 0x04800000, 0x04AC0000, 0, 0, 0, 0 } },
0264                                         { { 0x04840000, 0x04B00000, 0, 0, 0, 0 } },
0265                                         { { 0, 0, 0, 0, 0, 0 } } } };
0266
0267
0268 #define ATHUB_BASE__INST0_SEG0                     0x00000C20
0269 #define ATHUB_BASE__INST0_SEG1                     0x02408C00
0270 #define ATHUB_BASE__INST0_SEG2                     0
0271 #define ATHUB_BASE__INST0_SEG3                     0
0272 #define ATHUB_BASE__INST0_SEG4                     0
0273 #define ATHUB_BASE__INST0_SEG5                     0
0274
0275 #define ATHUB_BASE__INST1_SEG0                     0
0276 #define ATHUB_BASE__INST1_SEG1                     0
0277 #define ATHUB_BASE__INST1_SEG2                     0
0278 #define ATHUB_BASE__INST1_SEG3                     0
0279 #define ATHUB_BASE__INST1_SEG4                     0
0280 #define ATHUB_BASE__INST1_SEG5                     0
0281
0282 #define ATHUB_BASE__INST2_SEG0                     0
0283 #define ATHUB_BASE__INST2_SEG1                     0
0284 #define ATHUB_BASE__INST2_SEG2                     0
0285 #define ATHUB_BASE__INST2_SEG3                     0
0286 #define ATHUB_BASE__INST2_SEG4                     0
0287 #define ATHUB_BASE__INST2_SEG5                     0
0288
0289 #define ATHUB_BASE__INST3_SEG0                     0
0290 #define ATHUB_BASE__INST3_SEG1                     0
0291 #define ATHUB_BASE__INST3_SEG2                     0
0292 #define ATHUB_BASE__INST3_SEG3                     0
0293 #define ATHUB_BASE__INST3_SEG4                     0
0294 #define ATHUB_BASE__INST3_SEG5                     0
0295
0296 #define ATHUB_BASE__INST4_SEG0                     0
0297 #define ATHUB_BASE__INST4_SEG1                     0
0298 #define ATHUB_BASE__INST4_SEG2                     0
0299 #define ATHUB_BASE__INST4_SEG3                     0
0300 #define ATHUB_BASE__INST4_SEG4                     0
0301 #define ATHUB_BASE__INST4_SEG5                     0
0302
0303 #define ATHUB_BASE__INST5_SEG0                     0
0304 #define ATHUB_BASE__INST5_SEG1                     0
0305 #define ATHUB_BASE__INST5_SEG2                     0
0306 #define ATHUB_BASE__INST5_SEG3                     0
0307 #define ATHUB_BASE__INST5_SEG4                     0
0308 #define ATHUB_BASE__INST5_SEG5                     0
0309
0310 #define ATHUB_BASE__INST6_SEG0                     0
0311 #define ATHUB_BASE__INST6_SEG1                     0
0312 #define ATHUB_BASE__INST6_SEG2                     0
0313 #define ATHUB_BASE__INST6_SEG3                     0
0314 #define ATHUB_BASE__INST6_SEG4                     0
0315 #define ATHUB_BASE__INST6_SEG5                     0
0316
0317 #define CLK_BASE__INST0_SEG0                       0x00016C00
0318 #define CLK_BASE__INST0_SEG1                       0x02401800
0319 #define CLK_BASE__INST0_SEG2                       0
0320 #define CLK_BASE__INST0_SEG3                       0
0321 #define CLK_BASE__INST0_SEG4                       0
0322 #define CLK_BASE__INST0_SEG5                       0
0323
0324 #define CLK_BASE__INST1_SEG0                       0x00016E00
0325 #define CLK_BASE__INST1_SEG1                       0x02401C00
0326 #define CLK_BASE__INST1_SEG2                       0
0327 #define CLK_BASE__INST1_SEG3                       0
0328 #define CLK_BASE__INST1_SEG4                       0
0329 #define CLK_BASE__INST1_SEG5                       0
0330
0331 #define CLK_BASE__INST2_SEG0                       0x00017000
0332 #define CLK_BASE__INST2_SEG1                       0x02402000
0333 #define CLK_BASE__INST2_SEG2                       0
0334 #define CLK_BASE__INST2_SEG3                       0
0335 #define CLK_BASE__INST2_SEG4                       0
0336 #define CLK_BASE__INST2_SEG5                       0
0337
0338 #define CLK_BASE__INST3_SEG0                       0x00017200
0339 #define CLK_BASE__INST3_SEG1                       0x02402400
0340 #define CLK_BASE__INST3_SEG2                       0
0341 #define CLK_BASE__INST3_SEG3                       0
0342 #define CLK_BASE__INST3_SEG4                       0
0343 #define CLK_BASE__INST3_SEG5                       0
0344
0345 #define CLK_BASE__INST4_SEG0                       0x0001B000
0346 #define CLK_BASE__INST4_SEG1                       0x0242D800
0347 #define CLK_BASE__INST4_SEG2                       0
0348 #define CLK_BASE__INST4_SEG3                       0
0349 #define CLK_BASE__INST4_SEG4                       0
0350 #define CLK_BASE__INST4_SEG5                       0
0351
0352 #define CLK_BASE__INST5_SEG0                       0x0001B200
0353 #define CLK_BASE__INST5_SEG1                       0x0242DC00
0354 #define CLK_BASE__INST5_SEG2                       0
0355 #define CLK_BASE__INST5_SEG3                       0
0356 #define CLK_BASE__INST5_SEG4                       0
0357 #define CLK_BASE__INST5_SEG5                       0
0358
0359 #define CLK_BASE__INST6_SEG0                       0x00017E00
0360 #define CLK_BASE__INST6_SEG1                       0x0240BC00
0361 #define CLK_BASE__INST6_SEG2                       0
0362 #define CLK_BASE__INST6_SEG3                       0
0363 #define CLK_BASE__INST6_SEG4                       0
0364 #define CLK_BASE__INST6_SEG5                       0
0365
0366 #define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
0367 #define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
0368 #define DBGU_IO0_BASE__INST0_SEG2                  0
0369 #define DBGU_IO0_BASE__INST0_SEG3                  0
0370 #define DBGU_IO0_BASE__INST0_SEG4                  0
0371 #define DBGU_IO0_BASE__INST0_SEG5                  0
0372
0373 #define DBGU_IO0_BASE__INST1_SEG0                  0x00000260
0374 #define DBGU_IO0_BASE__INST1_SEG1                  0x02413C00
0375 #define DBGU_IO0_BASE__INST1_SEG2                  0
0376 #define DBGU_IO0_BASE__INST1_SEG3                  0
0377 #define DBGU_IO0_BASE__INST1_SEG4                  0
0378 #define DBGU_IO0_BASE__INST1_SEG5                  0
0379
0380 #define DBGU_IO0_BASE__INST2_SEG0                  0x00000280
0381 #define DBGU_IO0_BASE__INST2_SEG1                  0x02416000
0382 #define DBGU_IO0_BASE__INST2_SEG2                  0
0383 #define DBGU_IO0_BASE__INST2_SEG3                  0
0384 #define DBGU_IO0_BASE__INST2_SEG4                  0
0385 #define DBGU_IO0_BASE__INST2_SEG5                  0
0386
0387 #define DBGU_IO0_BASE__INST3_SEG0                  0
0388 #define DBGU_IO0_BASE__INST3_SEG1                  0
0389 #define DBGU_IO0_BASE__INST3_SEG2                  0
0390 #define DBGU_IO0_BASE__INST3_SEG3                  0
0391 #define DBGU_IO0_BASE__INST3_SEG4                  0
0392 #define DBGU_IO0_BASE__INST3_SEG5                  0
0393
0394 #define DBGU_IO0_BASE__INST4_SEG0                  0
0395 #define DBGU_IO0_BASE__INST4_SEG1                  0
0396 #define DBGU_IO0_BASE__INST4_SEG2                  0
0397 #define DBGU_IO0_BASE__INST4_SEG3                  0
0398 #define DBGU_IO0_BASE__INST4_SEG4                  0
0399 #define DBGU_IO0_BASE__INST4_SEG5                  0
0400
0401 #define DBGU_IO0_BASE__INST5_SEG0                  0
0402 #define DBGU_IO0_BASE__INST5_SEG1                  0
0403 #define DBGU_IO0_BASE__INST5_SEG2                  0
0404 #define DBGU_IO0_BASE__INST5_SEG3                  0
0405 #define DBGU_IO0_BASE__INST5_SEG4                  0
0406 #define DBGU_IO0_BASE__INST5_SEG5                  0
0407
0408 #define DBGU_IO0_BASE__INST6_SEG0                  0
0409 #define DBGU_IO0_BASE__INST6_SEG1                  0
0410 #define DBGU_IO0_BASE__INST6_SEG2                  0
0411 #define DBGU_IO0_BASE__INST6_SEG3                  0
0412 #define DBGU_IO0_BASE__INST6_SEG4                  0
0413 #define DBGU_IO0_BASE__INST6_SEG5                  0
0414
0415 #define DF_BASE__INST0_SEG0                        0x00007000
0416 #define DF_BASE__INST0_SEG1                        0x0240B800
0417 #define DF_BASE__INST0_SEG2                        0x07C00000
0418 #define DF_BASE__INST0_SEG3                        0
0419 #define DF_BASE__INST0_SEG4                        0
0420 #define DF_BASE__INST0_SEG5                        0
0421
0422 #define DF_BASE__INST1_SEG0                        0
0423 #define DF_BASE__INST1_SEG1                        0
0424 #define DF_BASE__INST1_SEG2                        0
0425 #define DF_BASE__INST1_SEG3                        0
0426 #define DF_BASE__INST1_SEG4                        0
0427 #define DF_BASE__INST1_SEG5                        0
0428
0429 #define DF_BASE__INST2_SEG0                        0
0430 #define DF_BASE__INST2_SEG1                        0
0431 #define DF_BASE__INST2_SEG2                        0
0432 #define DF_BASE__INST2_SEG3                        0
0433 #define DF_BASE__INST2_SEG4                        0
0434 #define DF_BASE__INST2_SEG5                        0
0435
0436 #define DF_BASE__INST3_SEG0                        0
0437 #define DF_BASE__INST3_SEG1                        0
0438 #define DF_BASE__INST3_SEG2                        0
0439 #define DF_BASE__INST3_SEG3                        0
0440 #define DF_BASE__INST3_SEG4                        0
0441 #define DF_BASE__INST3_SEG5                        0
0442
0443 #define DF_BASE__INST4_SEG0                        0
0444 #define DF_BASE__INST4_SEG1                        0
0445 #define DF_BASE__INST4_SEG2                        0
0446 #define DF_BASE__INST4_SEG3                        0
0447 #define DF_BASE__INST4_SEG4                        0
0448 #define DF_BASE__INST4_SEG5                        0
0449
0450 #define DF_BASE__INST5_SEG0                        0
0451 #define DF_BASE__INST5_SEG1                        0
0452 #define DF_BASE__INST5_SEG2                        0
0453 #define DF_BASE__INST5_SEG3                        0
0454 #define DF_BASE__INST5_SEG4                        0
0455 #define DF_BASE__INST5_SEG5                        0
0456
0457 #define DF_BASE__INST6_SEG0                        0
0458 #define DF_BASE__INST6_SEG1                        0
0459 #define DF_BASE__INST6_SEG2                        0
0460 #define DF_BASE__INST6_SEG3                        0
0461 #define DF_BASE__INST6_SEG4                        0
0462 #define DF_BASE__INST6_SEG5                        0
0463
0464 #define FUSE_BASE__INST0_SEG0                      0x00017400
0465 #define FUSE_BASE__INST0_SEG1                      0x02401400
0466 #define FUSE_BASE__INST0_SEG2                      0
0467 #define FUSE_BASE__INST0_SEG3                      0
0468 #define FUSE_BASE__INST0_SEG4                      0
0469 #define FUSE_BASE__INST0_SEG5                      0
0470
0471 #define FUSE_BASE__INST1_SEG0                      0
0472 #define FUSE_BASE__INST1_SEG1                      0
0473 #define FUSE_BASE__INST1_SEG2                      0
0474 #define FUSE_BASE__INST1_SEG3                      0
0475 #define FUSE_BASE__INST1_SEG4                      0
0476 #define FUSE_BASE__INST1_SEG5                      0
0477
0478 #define FUSE_BASE__INST2_SEG0                      0
0479 #define FUSE_BASE__INST2_SEG1                      0
0480 #define FUSE_BASE__INST2_SEG2                      0
0481 #define FUSE_BASE__INST2_SEG3                      0
0482 #define FUSE_BASE__INST2_SEG4                      0
0483 #define FUSE_BASE__INST2_SEG5                      0
0484
0485 #define FUSE_BASE__INST3_SEG0                      0
0486 #define FUSE_BASE__INST3_SEG1                      0
0487 #define FUSE_BASE__INST3_SEG2                      0
0488 #define FUSE_BASE__INST3_SEG3                      0
0489 #define FUSE_BASE__INST3_SEG4                      0
0490 #define FUSE_BASE__INST3_SEG5                      0
0491
0492 #define FUSE_BASE__INST4_SEG0                      0
0493 #define FUSE_BASE__INST4_SEG1                      0
0494 #define FUSE_BASE__INST4_SEG2                      0
0495 #define FUSE_BASE__INST4_SEG3                      0
0496 #define FUSE_BASE__INST4_SEG4                      0
0497 #define FUSE_BASE__INST4_SEG5                      0
0498
0499 #define FUSE_BASE__INST5_SEG0                      0
0500 #define FUSE_BASE__INST5_SEG1                      0
0501 #define FUSE_BASE__INST5_SEG2                      0
0502 #define FUSE_BASE__INST5_SEG3                      0
0503 #define FUSE_BASE__INST5_SEG4                      0
0504 #define FUSE_BASE__INST5_SEG5                      0
0505
0506 #define FUSE_BASE__INST6_SEG0                      0
0507 #define FUSE_BASE__INST6_SEG1                      0
0508 #define FUSE_BASE__INST6_SEG2                      0
0509 #define FUSE_BASE__INST6_SEG3                      0
0510 #define FUSE_BASE__INST6_SEG4                      0
0511 #define FUSE_BASE__INST6_SEG5                      0
0512
0513 #define GC_BASE__INST0_SEG0                        0x00002000
0514 #define GC_BASE__INST0_SEG1                        0x0000A000
0515 #define GC_BASE__INST0_SEG2                        0x02402C00
0516 #define GC_BASE__INST0_SEG3                        0
0517 #define GC_BASE__INST0_SEG4                        0
0518 #define GC_BASE__INST0_SEG5                        0
0519
0520 #define GC_BASE__INST1_SEG0                        0
0521 #define GC_BASE__INST1_SEG1                        0
0522 #define GC_BASE__INST1_SEG2                        0
0523 #define GC_BASE__INST1_SEG3                        0
0524 #define GC_BASE__INST1_SEG4                        0
0525 #define GC_BASE__INST1_SEG5                        0
0526
0527 #define GC_BASE__INST2_SEG0                        0
0528 #define GC_BASE__INST2_SEG1                        0
0529 #define GC_BASE__INST2_SEG2                        0
0530 #define GC_BASE__INST2_SEG3                        0
0531 #define GC_BASE__INST2_SEG4                        0
0532 #define GC_BASE__INST2_SEG5                        0
0533
0534 #define GC_BASE__INST3_SEG0                        0
0535 #define GC_BASE__INST3_SEG1                        0
0536 #define GC_BASE__INST3_SEG2                        0
0537 #define GC_BASE__INST3_SEG3                        0
0538 #define GC_BASE__INST3_SEG4                        0
0539 #define GC_BASE__INST3_SEG5                        0
0540
0541 #define GC_BASE__INST4_SEG0                        0
0542 #define GC_BASE__INST4_SEG1                        0
0543 #define GC_BASE__INST4_SEG2                        0
0544 #define GC_BASE__INST4_SEG3                        0
0545 #define GC_BASE__INST4_SEG4                        0
0546 #define GC_BASE__INST4_SEG5                        0
0547
0548 #define GC_BASE__INST5_SEG0                        0
0549 #define GC_BASE__INST5_SEG1                        0
0550 #define GC_BASE__INST5_SEG2                        0
0551 #define GC_BASE__INST5_SEG3                        0
0552 #define GC_BASE__INST5_SEG4                        0
0553 #define GC_BASE__INST5_SEG5                        0
0554
0555 #define GC_BASE__INST6_SEG0                        0
0556 #define GC_BASE__INST6_SEG1                        0
0557 #define GC_BASE__INST6_SEG2                        0
0558 #define GC_BASE__INST6_SEG3                        0
0559 #define GC_BASE__INST6_SEG4                        0
0560 #define GC_BASE__INST6_SEG5                        0
0561
0562 #define HDP_BASE__INST0_SEG0                       0x00000F20
0563 #define HDP_BASE__INST0_SEG1                       0x0240A400
0564 #define HDP_BASE__INST0_SEG2                       0
0565 #define HDP_BASE__INST0_SEG3                       0
0566 #define HDP_BASE__INST0_SEG4                       0
0567 #define HDP_BASE__INST0_SEG5                       0
0568
0569 #define HDP_BASE__INST1_SEG0                       0
0570 #define HDP_BASE__INST1_SEG1                       0
0571 #define HDP_BASE__INST1_SEG2                       0
0572 #define HDP_BASE__INST1_SEG3                       0
0573 #define HDP_BASE__INST1_SEG4                       0
0574 #define HDP_BASE__INST1_SEG5                       0
0575
0576 #define HDP_BASE__INST2_SEG0                       0
0577 #define HDP_BASE__INST2_SEG1                       0
0578 #define HDP_BASE__INST2_SEG2                       0
0579 #define HDP_BASE__INST2_SEG3                       0
0580 #define HDP_BASE__INST2_SEG4                       0
0581 #define HDP_BASE__INST2_SEG5                       0
0582
0583 #define HDP_BASE__INST3_SEG0                       0
0584 #define HDP_BASE__INST3_SEG1                       0
0585 #define HDP_BASE__INST3_SEG2                       0
0586 #define HDP_BASE__INST3_SEG3                       0
0587 #define HDP_BASE__INST3_SEG4                       0
0588 #define HDP_BASE__INST3_SEG5                       0
0589
0590 #define HDP_BASE__INST4_SEG0                       0
0591 #define HDP_BASE__INST4_SEG1                       0
0592 #define HDP_BASE__INST4_SEG2                       0
0593 #define HDP_BASE__INST4_SEG3                       0
0594 #define HDP_BASE__INST4_SEG4                       0
0595 #define HDP_BASE__INST4_SEG5                       0
0596
0597 #define HDP_BASE__INST5_SEG0                       0
0598 #define HDP_BASE__INST5_SEG1                       0
0599 #define HDP_BASE__INST5_SEG2                       0
0600 #define HDP_BASE__INST5_SEG3                       0
0601 #define HDP_BASE__INST5_SEG4                       0
0602 #define HDP_BASE__INST5_SEG5                       0
0603
0604 #define HDP_BASE__INST6_SEG0                       0
0605 #define HDP_BASE__INST6_SEG1                       0
0606 #define HDP_BASE__INST6_SEG2                       0
0607 #define HDP_BASE__INST6_SEG3                       0
0608 #define HDP_BASE__INST6_SEG4                       0
0609 #define HDP_BASE__INST6_SEG5                       0
0610
0611 #define IOAGR0_BASE__INST0_SEG0                    0x02419000
0612 #define IOAGR0_BASE__INST0_SEG1                    0x056C0000
0613 #define IOAGR0_BASE__INST0_SEG2                    0
0614 #define IOAGR0_BASE__INST0_SEG3                    0
0615 #define IOAGR0_BASE__INST0_SEG4                    0
0616 #define IOAGR0_BASE__INST0_SEG5                    0
0617
0618 #define IOAGR0_BASE__INST1_SEG0                    0
0619 #define IOAGR0_BASE__INST1_SEG1                    0
0620 #define IOAGR0_BASE__INST1_SEG2                    0
0621 #define IOAGR0_BASE__INST1_SEG3                    0
0622 #define IOAGR0_BASE__INST1_SEG4                    0
0623 #define IOAGR0_BASE__INST1_SEG5                    0
0624
0625 #define IOAGR0_BASE__INST2_SEG0                    0
0626 #define IOAGR0_BASE__INST2_SEG1                    0
0627 #define IOAGR0_BASE__INST2_SEG2                    0
0628 #define IOAGR0_BASE__INST2_SEG3                    0
0629 #define IOAGR0_BASE__INST2_SEG4                    0
0630 #define IOAGR0_BASE__INST2_SEG5                    0
0631
0632 #define IOAGR0_BASE__INST3_SEG0                    0
0633 #define IOAGR0_BASE__INST3_SEG1                    0
0634 #define IOAGR0_BASE__INST3_SEG2                    0
0635 #define IOAGR0_BASE__INST3_SEG3                    0
0636 #define IOAGR0_BASE__INST3_SEG4                    0
0637 #define IOAGR0_BASE__INST3_SEG5                    0
0638
0639 #define IOAGR0_BASE__INST4_SEG0                    0
0640 #define IOAGR0_BASE__INST4_SEG1                    0
0641 #define IOAGR0_BASE__INST4_SEG2                    0
0642 #define IOAGR0_BASE__INST4_SEG3                    0
0643 #define IOAGR0_BASE__INST4_SEG4                    0
0644 #define IOAGR0_BASE__INST4_SEG5                    0
0645
0646 #define IOAGR0_BASE__INST5_SEG0                    0
0647 #define IOAGR0_BASE__INST5_SEG1                    0
0648 #define IOAGR0_BASE__INST5_SEG2                    0
0649 #define IOAGR0_BASE__INST5_SEG3                    0
0650 #define IOAGR0_BASE__INST5_SEG4                    0
0651 #define IOAGR0_BASE__INST5_SEG5                    0
0652
0653 #define IOAGR0_BASE__INST6_SEG0                    0
0654 #define IOAGR0_BASE__INST6_SEG1                    0
0655 #define IOAGR0_BASE__INST6_SEG2                    0
0656 #define IOAGR0_BASE__INST6_SEG3                    0
0657 #define IOAGR0_BASE__INST6_SEG4                    0
0658 #define IOAGR0_BASE__INST6_SEG5                    0
0659
0660 #define IOAPIC0_BASE__INST0_SEG0                   0x00A00000
0661 #define IOAPIC0_BASE__INST0_SEG1                   0x0241F000
0662 #define IOAPIC0_BASE__INST0_SEG2                   0x050C0000
0663 #define IOAPIC0_BASE__INST0_SEG3                   0
0664 #define IOAPIC0_BASE__INST0_SEG4                   0
0665 #define IOAPIC0_BASE__INST0_SEG5                   0
0666
0667 #define IOAPIC0_BASE__INST1_SEG0                   0
0668 #define IOAPIC0_BASE__INST1_SEG1                   0
0669 #define IOAPIC0_BASE__INST1_SEG2                   0
0670 #define IOAPIC0_BASE__INST1_SEG3                   0
0671 #define IOAPIC0_BASE__INST1_SEG4                   0
0672 #define IOAPIC0_BASE__INST1_SEG5                   0
0673
0674 #define IOAPIC0_BASE__INST2_SEG0                   0
0675 #define IOAPIC0_BASE__INST2_SEG1                   0
0676 #define IOAPIC0_BASE__INST2_SEG2                   0
0677 #define IOAPIC0_BASE__INST2_SEG3                   0
0678 #define IOAPIC0_BASE__INST2_SEG4                   0
0679 #define IOAPIC0_BASE__INST2_SEG5                   0
0680
0681 #define IOAPIC0_BASE__INST3_SEG0                   0
0682 #define IOAPIC0_BASE__INST3_SEG1                   0
0683 #define IOAPIC0_BASE__INST3_SEG2                   0
0684 #define IOAPIC0_BASE__INST3_SEG3                   0
0685 #define IOAPIC0_BASE__INST3_SEG4                   0
0686 #define IOAPIC0_BASE__INST3_SEG5                   0
0687
0688 #define IOAPIC0_BASE__INST4_SEG0                   0
0689 #define IOAPIC0_BASE__INST4_SEG1                   0
0690 #define IOAPIC0_BASE__INST4_SEG2                   0
0691 #define IOAPIC0_BASE__INST4_SEG3                   0
0692 #define IOAPIC0_BASE__INST4_SEG4                   0
0693 #define IOAPIC0_BASE__INST4_SEG5                   0
0694
0695 #define IOAPIC0_BASE__INST5_SEG0                   0
0696 #define IOAPIC0_BASE__INST5_SEG1                   0
0697 #define IOAPIC0_BASE__INST5_SEG2                   0
0698 #define IOAPIC0_BASE__INST5_SEG3                   0
0699 #define IOAPIC0_BASE__INST5_SEG4                   0
0700 #define IOAPIC0_BASE__INST5_SEG5                   0
0701
0702 #define IOAPIC0_BASE__INST6_SEG0                   0
0703 #define IOAPIC0_BASE__INST6_SEG1                   0
0704 #define IOAPIC0_BASE__INST6_SEG2                   0
0705 #define IOAPIC0_BASE__INST6_SEG3                   0
0706 #define IOAPIC0_BASE__INST6_SEG4                   0
0707 #define IOAPIC0_BASE__INST6_SEG5                   0
0708
0709 #define IOHC0_BASE__INST0_SEG0                     0x00010000
0710 #define IOHC0_BASE__INST0_SEG1                     0x02406000
0711 #define IOHC0_BASE__INST0_SEG2                     0x04EC0000
0712 #define IOHC0_BASE__INST0_SEG3                     0
0713 #define IOHC0_BASE__INST0_SEG4                     0
0714 #define IOHC0_BASE__INST0_SEG5                     0
0715
0716 #define IOHC0_BASE__INST1_SEG0                     0
0717 #define IOHC0_BASE__INST1_SEG1                     0
0718 #define IOHC0_BASE__INST1_SEG2                     0
0719 #define IOHC0_BASE__INST1_SEG3                     0
0720 #define IOHC0_BASE__INST1_SEG4                     0
0721 #define IOHC0_BASE__INST1_SEG5                     0
0722
0723 #define IOHC0_BASE__INST2_SEG0                     0
0724 #define IOHC0_BASE__INST2_SEG1                     0
0725 #define IOHC0_BASE__INST2_SEG2                     0
0726 #define IOHC0_BASE__INST2_SEG3                     0
0727 #define IOHC0_BASE__INST2_SEG4                     0
0728 #define IOHC0_BASE__INST2_SEG5                     0
0729
0730 #define IOHC0_BASE__INST3_SEG0                     0
0731 #define IOHC0_BASE__INST3_SEG1                     0
0732 #define IOHC0_BASE__INST3_SEG2                     0
0733 #define IOHC0_BASE__INST3_SEG3                     0
0734 #define IOHC0_BASE__INST3_SEG4                     0
0735 #define IOHC0_BASE__INST3_SEG5                     0
0736
0737 #define IOHC0_BASE__INST4_SEG0                     0
0738 #define IOHC0_BASE__INST4_SEG1                     0
0739 #define IOHC0_BASE__INST4_SEG2                     0
0740 #define IOHC0_BASE__INST4_SEG3                     0
0741 #define IOHC0_BASE__INST4_SEG4                     0
0742 #define IOHC0_BASE__INST4_SEG5                     0
0743
0744 #define IOHC0_BASE__INST5_SEG0                     0
0745 #define IOHC0_BASE__INST5_SEG1                     0
0746 #define IOHC0_BASE__INST5_SEG2                     0
0747 #define IOHC0_BASE__INST5_SEG3                     0
0748 #define IOHC0_BASE__INST5_SEG4                     0
0749 #define IOHC0_BASE__INST5_SEG5                     0
0750
0751 #define IOHC0_BASE__INST6_SEG0                     0
0752 #define IOHC0_BASE__INST6_SEG1                     0
0753 #define IOHC0_BASE__INST6_SEG2                     0
0754 #define IOHC0_BASE__INST6_SEG3                     0
0755 #define IOHC0_BASE__INST6_SEG4                     0
0756 #define IOHC0_BASE__INST6_SEG5                     0
0757
0758 #define L1IMUIOAGR0_BASE__INST0_SEG0               0x0240CC00
0759 #define L1IMUIOAGR0_BASE__INST0_SEG1               0x05200000
0760 #define L1IMUIOAGR0_BASE__INST0_SEG2               0
0761 #define L1IMUIOAGR0_BASE__INST0_SEG3               0
0762 #define L1IMUIOAGR0_BASE__INST0_SEG4               0
0763 #define L1IMUIOAGR0_BASE__INST0_SEG5               0
0764
0765 #define L1IMUIOAGR0_BASE__INST1_SEG0               0
0766 #define L1IMUIOAGR0_BASE__INST1_SEG1               0
0767 #define L1IMUIOAGR0_BASE__INST1_SEG2               0
0768 #define L1IMUIOAGR0_BASE__INST1_SEG3               0
0769 #define L1IMUIOAGR0_BASE__INST1_SEG4               0
0770 #define L1IMUIOAGR0_BASE__INST1_SEG5               0
0771
0772 #define L1IMUIOAGR0_BASE__INST2_SEG0               0
0773 #define L1IMUIOAGR0_BASE__INST2_SEG1               0
0774 #define L1IMUIOAGR0_BASE__INST2_SEG2               0
0775 #define L1IMUIOAGR0_BASE__INST2_SEG3               0
0776 #define L1IMUIOAGR0_BASE__INST2_SEG4               0
0777 #define L1IMUIOAGR0_BASE__INST2_SEG5               0
0778
0779 #define L1IMUIOAGR0_BASE__INST3_SEG0               0
0780 #define L1IMUIOAGR0_BASE__INST3_SEG1               0
0781 #define L1IMUIOAGR0_BASE__INST3_SEG2               0
0782 #define L1IMUIOAGR0_BASE__INST3_SEG3               0
0783 #define L1IMUIOAGR0_BASE__INST3_SEG4               0
0784 #define L1IMUIOAGR0_BASE__INST3_SEG5               0
0785
0786 #define L1IMUIOAGR0_BASE__INST4_SEG0               0
0787 #define L1IMUIOAGR0_BASE__INST4_SEG1               0
0788 #define L1IMUIOAGR0_BASE__INST4_SEG2               0
0789 #define L1IMUIOAGR0_BASE__INST4_SEG3               0
0790 #define L1IMUIOAGR0_BASE__INST4_SEG4               0
0791 #define L1IMUIOAGR0_BASE__INST4_SEG5               0
0792
0793 #define L1IMUIOAGR0_BASE__INST5_SEG0               0
0794 #define L1IMUIOAGR0_BASE__INST5_SEG1               0
0795 #define L1IMUIOAGR0_BASE__INST5_SEG2               0
0796 #define L1IMUIOAGR0_BASE__INST5_SEG3               0
0797 #define L1IMUIOAGR0_BASE__INST5_SEG4               0
0798 #define L1IMUIOAGR0_BASE__INST5_SEG5               0
0799
0800 #define L1IMUIOAGR0_BASE__INST6_SEG0               0
0801 #define L1IMUIOAGR0_BASE__INST6_SEG1               0
0802 #define L1IMUIOAGR0_BASE__INST6_SEG2               0
0803 #define L1IMUIOAGR0_BASE__INST6_SEG3               0
0804 #define L1IMUIOAGR0_BASE__INST6_SEG4               0
0805 #define L1IMUIOAGR0_BASE__INST6_SEG5               0
0806
0807 #define L1IMUPCIE0_BASE__INST0_SEG0                0x0240C800
0808 #define L1IMUPCIE0_BASE__INST0_SEG1                0x051C0000
0809 #define L1IMUPCIE0_BASE__INST0_SEG2                0
0810 #define L1IMUPCIE0_BASE__INST0_SEG3                0
0811 #define L1IMUPCIE0_BASE__INST0_SEG4                0
0812 #define L1IMUPCIE0_BASE__INST0_SEG5                0
0813
0814 #define L1IMUPCIE0_BASE__INST1_SEG0                0
0815 #define L1IMUPCIE0_BASE__INST1_SEG1                0
0816 #define L1IMUPCIE0_BASE__INST1_SEG2                0
0817 #define L1IMUPCIE0_BASE__INST1_SEG3                0
0818 #define L1IMUPCIE0_BASE__INST1_SEG4                0
0819 #define L1IMUPCIE0_BASE__INST1_SEG5                0
0820
0821 #define L1IMUPCIE0_BASE__INST2_SEG0                0
0822 #define L1IMUPCIE0_BASE__INST2_SEG1                0
0823 #define L1IMUPCIE0_BASE__INST2_SEG2                0
0824 #define L1IMUPCIE0_BASE__INST2_SEG3                0
0825 #define L1IMUPCIE0_BASE__INST2_SEG4                0
0826 #define L1IMUPCIE0_BASE__INST2_SEG5                0
0827
0828 #define L1IMUPCIE0_BASE__INST3_SEG0                0
0829 #define L1IMUPCIE0_BASE__INST3_SEG1                0
0830 #define L1IMUPCIE0_BASE__INST3_SEG2                0
0831 #define L1IMUPCIE0_BASE__INST3_SEG3                0
0832 #define L1IMUPCIE0_BASE__INST3_SEG4                0
0833 #define L1IMUPCIE0_BASE__INST3_SEG5                0
0834
0835 #define L1IMUPCIE0_BASE__INST4_SEG0                0
0836 #define L1IMUPCIE0_BASE__INST4_SEG1                0
0837 #define L1IMUPCIE0_BASE__INST4_SEG2                0
0838 #define L1IMUPCIE0_BASE__INST4_SEG3                0
0839 #define L1IMUPCIE0_BASE__INST4_SEG4                0
0840 #define L1IMUPCIE0_BASE__INST4_SEG5                0
0841
0842 #define L1IMUPCIE0_BASE__INST5_SEG0                0
0843 #define L1IMUPCIE0_BASE__INST5_SEG1                0
0844 #define L1IMUPCIE0_BASE__INST5_SEG2                0
0845 #define L1IMUPCIE0_BASE__INST5_SEG3                0
0846 #define L1IMUPCIE0_BASE__INST5_SEG4                0
0847 #define L1IMUPCIE0_BASE__INST5_SEG5                0
0848
0849 #define L1IMUPCIE0_BASE__INST6_SEG0                0
0850 #define L1IMUPCIE0_BASE__INST6_SEG1                0
0851 #define L1IMUPCIE0_BASE__INST6_SEG2                0
0852 #define L1IMUPCIE0_BASE__INST6_SEG3                0
0853 #define L1IMUPCIE0_BASE__INST6_SEG4                0
0854 #define L1IMUPCIE0_BASE__INST6_SEG5                0
0855
0856 #define L2IMU0_BASE__INST0_SEG0                    0x00007DC0
0857 #define L2IMU0_BASE__INST0_SEG1                    0x00900000
0858 #define L2IMU0_BASE__INST0_SEG2                    0x02407000
0859 #define L2IMU0_BASE__INST0_SEG3                    0x04FC0000
0860 #define L2IMU0_BASE__INST0_SEG4                    0x055C0000
0861 #define L2IMU0_BASE__INST0_SEG5                    0
0862
0863 #define L2IMU0_BASE__INST1_SEG0                    0
0864 #define L2IMU0_BASE__INST1_SEG1                    0
0865 #define L2IMU0_BASE__INST1_SEG2                    0
0866 #define L2IMU0_BASE__INST1_SEG3                    0
0867 #define L2IMU0_BASE__INST1_SEG4                    0
0868 #define L2IMU0_BASE__INST1_SEG5                    0
0869
0870 #define L2IMU0_BASE__INST2_SEG0                    0
0871 #define L2IMU0_BASE__INST2_SEG1                    0
0872 #define L2IMU0_BASE__INST2_SEG2                    0
0873 #define L2IMU0_BASE__INST2_SEG3                    0
0874 #define L2IMU0_BASE__INST2_SEG4                    0
0875 #define L2IMU0_BASE__INST2_SEG5                    0
0876
0877 #define L2IMU0_BASE__INST3_SEG0                    0
0878 #define L2IMU0_BASE__INST3_SEG1                    0
0879 #define L2IMU0_BASE__INST3_SEG2                    0
0880 #define L2IMU0_BASE__INST3_SEG3                    0
0881 #define L2IMU0_BASE__INST3_SEG4                    0
0882 #define L2IMU0_BASE__INST3_SEG5                    0
0883
0884 #define L2IMU0_BASE__INST4_SEG0                    0
0885 #define L2IMU0_BASE__INST4_SEG1                    0
0886 #define L2IMU0_BASE__INST4_SEG2                    0
0887 #define L2IMU0_BASE__INST4_SEG3                    0
0888 #define L2IMU0_BASE__INST4_SEG4                    0
0889 #define L2IMU0_BASE__INST4_SEG5                    0
0890
0891 #define L2IMU0_BASE__INST5_SEG0                    0
0892 #define L2IMU0_BASE__INST5_SEG1                    0
0893 #define L2IMU0_BASE__INST5_SEG2                    0
0894 #define L2IMU0_BASE__INST5_SEG3                    0
0895 #define L2IMU0_BASE__INST5_SEG4                    0
0896 #define L2IMU0_BASE__INST5_SEG5                    0
0897
0898 #define L2IMU0_BASE__INST6_SEG0                    0
0899 #define L2IMU0_BASE__INST6_SEG1                    0
0900 #define L2IMU0_BASE__INST6_SEG2                    0
0901 #define L2IMU0_BASE__INST6_SEG3                    0
0902 #define L2IMU0_BASE__INST6_SEG4                    0
0903 #define L2IMU0_BASE__INST6_SEG5                    0
0904
0905 #define MMHUB_BASE__INST0_SEG0                     0x0001A000
0906 #define MMHUB_BASE__INST0_SEG1                     0x02408800
0907 #define MMHUB_BASE__INST0_SEG2                     0
0908 #define MMHUB_BASE__INST0_SEG3                     0
0909 #define MMHUB_BASE__INST0_SEG4                     0
0910 #define MMHUB_BASE__INST0_SEG5                     0
0911
0912 #define MMHUB_BASE__INST1_SEG0                     0
0913 #define MMHUB_BASE__INST1_SEG1                     0
0914 #define MMHUB_BASE__INST1_SEG2                     0
0915 #define MMHUB_BASE__INST1_SEG3                     0
0916 #define MMHUB_BASE__INST1_SEG4                     0
0917 #define MMHUB_BASE__INST1_SEG5                     0
0918
0919 #define MMHUB_BASE__INST2_SEG0                     0
0920 #define MMHUB_BASE__INST2_SEG1                     0
0921 #define MMHUB_BASE__INST2_SEG2                     0
0922 #define MMHUB_BASE__INST2_SEG3                     0
0923 #define MMHUB_BASE__INST2_SEG4                     0
0924 #define MMHUB_BASE__INST2_SEG5                     0
0925
0926 #define MMHUB_BASE__INST3_SEG0                     0
0927 #define MMHUB_BASE__INST3_SEG1                     0
0928 #define MMHUB_BASE__INST3_SEG2                     0
0929 #define MMHUB_BASE__INST3_SEG3                     0
0930 #define MMHUB_BASE__INST3_SEG4                     0
0931 #define MMHUB_BASE__INST3_SEG5                     0
0932
0933 #define MMHUB_BASE__INST4_SEG0                     0
0934 #define MMHUB_BASE__INST4_SEG1                     0
0935 #define MMHUB_BASE__INST4_SEG2                     0
0936 #define MMHUB_BASE__INST4_SEG3                     0
0937 #define MMHUB_BASE__INST4_SEG4                     0
0938 #define MMHUB_BASE__INST4_SEG5                     0
0939
0940 #define MMHUB_BASE__INST5_SEG0                     0
0941 #define MMHUB_BASE__INST5_SEG1                     0
0942 #define MMHUB_BASE__INST5_SEG2                     0
0943 #define MMHUB_BASE__INST5_SEG3                     0
0944 #define MMHUB_BASE__INST5_SEG4                     0
0945 #define MMHUB_BASE__INST5_SEG5                     0
0946
0947 #define MMHUB_BASE__INST6_SEG0                     0
0948 #define MMHUB_BASE__INST6_SEG1                     0
0949 #define MMHUB_BASE__INST6_SEG2                     0
0950 #define MMHUB_BASE__INST6_SEG3                     0
0951 #define MMHUB_BASE__INST6_SEG4                     0
0952 #define MMHUB_BASE__INST6_SEG5                     0
0953
0954 #define MP0_BASE__INST0_SEG0                       0x00016000
0955 #define MP0_BASE__INST0_SEG1                       0x00DC0000
0956 #define MP0_BASE__INST0_SEG2                       0x00E00000
0957 #define MP0_BASE__INST0_SEG3                       0x00E40000
0958 #define MP0_BASE__INST0_SEG4                       0x0243FC00
0959 #define MP0_BASE__INST0_SEG5                       0
0960
0961 #define MP0_BASE__INST1_SEG0                       0
0962 #define MP0_BASE__INST1_SEG1                       0
0963 #define MP0_BASE__INST1_SEG2                       0
0964 #define MP0_BASE__INST1_SEG3                       0
0965 #define MP0_BASE__INST1_SEG4                       0
0966 #define MP0_BASE__INST1_SEG5                       0
0967
0968 #define MP0_BASE__INST2_SEG0                       0
0969 #define MP0_BASE__INST2_SEG1                       0
0970 #define MP0_BASE__INST2_SEG2                       0
0971 #define MP0_BASE__INST2_SEG3                       0
0972 #define MP0_BASE__INST2_SEG4                       0
0973 #define MP0_BASE__INST2_SEG5                       0
0974
0975 #define MP0_BASE__INST3_SEG0                       0
0976 #define MP0_BASE__INST3_SEG1                       0
0977 #define MP0_BASE__INST3_SEG2                       0
0978 #define MP0_BASE__INST3_SEG3                       0
0979 #define MP0_BASE__INST3_SEG4                       0
0980 #define MP0_BASE__INST3_SEG5                       0
0981
0982 #define MP0_BASE__INST4_SEG0                       0
0983 #define MP0_BASE__INST4_SEG1                       0
0984 #define MP0_BASE__INST4_SEG2                       0
0985 #define MP0_BASE__INST4_SEG3                       0
0986 #define MP0_BASE__INST4_SEG4                       0
0987 #define MP0_BASE__INST4_SEG5                       0
0988
0989 #define MP0_BASE__INST5_SEG0                       0
0990 #define MP0_BASE__INST5_SEG1                       0
0991 #define MP0_BASE__INST5_SEG2                       0
0992 #define MP0_BASE__INST5_SEG3                       0
0993 #define MP0_BASE__INST5_SEG4                       0
0994 #define MP0_BASE__INST5_SEG5                       0
0995
0996 #define MP0_BASE__INST6_SEG0                       0
0997 #define MP0_BASE__INST6_SEG1                       0
0998 #define MP0_BASE__INST6_SEG2                       0
0999 #define MP0_BASE__INST6_SEG3                       0
1000 #define MP0_BASE__INST6_SEG4                       0
1001 #define MP0_BASE__INST6_SEG5                       0
1002
1003 #define MP1_BASE__INST0_SEG0                       0x00016000
1004 #define MP1_BASE__INST0_SEG1                       0x00DC0000
1005 #define MP1_BASE__INST0_SEG2                       0x00E00000
1006 #define MP1_BASE__INST0_SEG3                       0x00E40000
1007 #define MP1_BASE__INST0_SEG4                       0x0243FC00
1008 #define MP1_BASE__INST0_SEG5                       0
1009
1010 #define MP1_BASE__INST1_SEG0                       0
1011 #define MP1_BASE__INST1_SEG1                       0
1012 #define MP1_BASE__INST1_SEG2                       0
1013 #define MP1_BASE__INST1_SEG3                       0
1014 #define MP1_BASE__INST1_SEG4                       0
1015 #define MP1_BASE__INST1_SEG5                       0
1016
1017 #define MP1_BASE__INST2_SEG0                       0
1018 #define MP1_BASE__INST2_SEG1                       0
1019 #define MP1_BASE__INST2_SEG2                       0
1020 #define MP1_BASE__INST2_SEG3                       0
1021 #define MP1_BASE__INST2_SEG4                       0
1022 #define MP1_BASE__INST2_SEG5                       0
1023
1024 #define MP1_BASE__INST3_SEG0                       0
1025 #define MP1_BASE__INST3_SEG1                       0
1026 #define MP1_BASE__INST3_SEG2                       0
1027 #define MP1_BASE__INST3_SEG3                       0
1028 #define MP1_BASE__INST3_SEG4                       0
1029 #define MP1_BASE__INST3_SEG5                       0
1030
1031 #define MP1_BASE__INST4_SEG0                       0
1032 #define MP1_BASE__INST4_SEG1                       0
1033 #define MP1_BASE__INST4_SEG2                       0
1034 #define MP1_BASE__INST4_SEG3                       0
1035 #define MP1_BASE__INST4_SEG4                       0
1036 #define MP1_BASE__INST4_SEG5                       0
1037
1038 #define MP1_BASE__INST5_SEG0                       0
1039 #define MP1_BASE__INST5_SEG1                       0
1040 #define MP1_BASE__INST5_SEG2                       0
1041 #define MP1_BASE__INST5_SEG3                       0
1042 #define MP1_BASE__INST5_SEG4                       0
1043 #define MP1_BASE__INST5_SEG5                       0
1044
1045 #define MP1_BASE__INST6_SEG0                       0
1046 #define MP1_BASE__INST6_SEG1                       0
1047 #define MP1_BASE__INST6_SEG2                       0
1048 #define MP1_BASE__INST6_SEG3                       0
1049 #define MP1_BASE__INST6_SEG4                       0
1050 #define MP1_BASE__INST6_SEG5                       0
1051
1052 #define NBIO_BASE__INST0_SEG0                      0x00000000
1053 #define NBIO_BASE__INST0_SEG1                      0x00000014
1054 #define NBIO_BASE__INST0_SEG2                      0x00000D20
1055 #define NBIO_BASE__INST0_SEG3                      0x00010400
1056 #define NBIO_BASE__INST0_SEG4                      0x0241B000
1057 #define NBIO_BASE__INST0_SEG5                      0x04040000
1058
1059 #define NBIO_BASE__INST1_SEG0                      0
1060 #define NBIO_BASE__INST1_SEG1                      0
1061 #define NBIO_BASE__INST1_SEG2                      0
1062 #define NBIO_BASE__INST1_SEG3                      0
1063 #define NBIO_BASE__INST1_SEG4                      0
1064 #define NBIO_BASE__INST1_SEG5                      0
1065
1066 #define NBIO_BASE__INST2_SEG0                      0
1067 #define NBIO_BASE__INST2_SEG1                      0
1068 #define NBIO_BASE__INST2_SEG2                      0
1069 #define NBIO_BASE__INST2_SEG3                      0
1070 #define NBIO_BASE__INST2_SEG4                      0
1071 #define NBIO_BASE__INST2_SEG5                      0
1072
1073 #define NBIO_BASE__INST3_SEG0                      0
1074 #define NBIO_BASE__INST3_SEG1                      0
1075 #define NBIO_BASE__INST3_SEG2                      0
1076 #define NBIO_BASE__INST3_SEG3                      0
1077 #define NBIO_BASE__INST3_SEG4                      0
1078 #define NBIO_BASE__INST3_SEG5                      0
1079
1080 #define NBIO_BASE__INST4_SEG0                      0
1081 #define NBIO_BASE__INST4_SEG1                      0
1082 #define NBIO_BASE__INST4_SEG2                      0
1083 #define NBIO_BASE__INST4_SEG3                      0
1084 #define NBIO_BASE__INST4_SEG4                      0
1085 #define NBIO_BASE__INST4_SEG5                      0
1086
1087 #define NBIO_BASE__INST5_SEG0                      0
1088 #define NBIO_BASE__INST5_SEG1                      0
1089 #define NBIO_BASE__INST5_SEG2                      0
1090 #define NBIO_BASE__INST5_SEG3                      0
1091 #define NBIO_BASE__INST5_SEG4                      0
1092 #define NBIO_BASE__INST5_SEG5                      0
1093
1094 #define NBIO_BASE__INST6_SEG0                      0
1095 #define NBIO_BASE__INST6_SEG1                      0
1096 #define NBIO_BASE__INST6_SEG2                      0
1097 #define NBIO_BASE__INST6_SEG3                      0
1098 #define NBIO_BASE__INST6_SEG4                      0
1099 #define NBIO_BASE__INST6_SEG5                      0
1100
1101 #define OSSSYS_BASE__INST0_SEG0                    0x000010A0
1102 #define OSSSYS_BASE__INST0_SEG1                    0x0240A000
1103 #define OSSSYS_BASE__INST0_SEG2                    0
1104 #define OSSSYS_BASE__INST0_SEG3                    0
1105 #define OSSSYS_BASE__INST0_SEG4                    0
1106 #define OSSSYS_BASE__INST0_SEG5                    0
1107
1108 #define OSSSYS_BASE__INST1_SEG0                    0
1109 #define OSSSYS_BASE__INST1_SEG1                    0
1110 #define OSSSYS_BASE__INST1_SEG2                    0
1111 #define OSSSYS_BASE__INST1_SEG3                    0
1112 #define OSSSYS_BASE__INST1_SEG4                    0
1113 #define OSSSYS_BASE__INST1_SEG5                    0
1114
1115 #define OSSSYS_BASE__INST2_SEG0                    0
1116 #define OSSSYS_BASE__INST2_SEG1                    0
1117 #define OSSSYS_BASE__INST2_SEG2                    0
1118 #define OSSSYS_BASE__INST2_SEG3                    0
1119 #define OSSSYS_BASE__INST2_SEG4                    0
1120 #define OSSSYS_BASE__INST2_SEG5                    0
1121
1122 #define OSSSYS_BASE__INST3_SEG0                    0
1123 #define OSSSYS_BASE__INST3_SEG1                    0
1124 #define OSSSYS_BASE__INST3_SEG2                    0
1125 #define OSSSYS_BASE__INST3_SEG3                    0
1126 #define OSSSYS_BASE__INST3_SEG4                    0
1127 #define OSSSYS_BASE__INST3_SEG5                    0
1128
1129 #define OSSSYS_BASE__INST4_SEG0                    0
1130 #define OSSSYS_BASE__INST4_SEG1                    0
1131 #define OSSSYS_BASE__INST4_SEG2                    0
1132 #define OSSSYS_BASE__INST4_SEG3                    0
1133 #define OSSSYS_BASE__INST4_SEG4                    0
1134 #define OSSSYS_BASE__INST4_SEG5                    0
1135
1136 #define OSSSYS_BASE__INST5_SEG0                    0
1137 #define OSSSYS_BASE__INST5_SEG1                    0
1138 #define OSSSYS_BASE__INST5_SEG2                    0
1139 #define OSSSYS_BASE__INST5_SEG3                    0
1140 #define OSSSYS_BASE__INST5_SEG4                    0
1141 #define OSSSYS_BASE__INST5_SEG5                    0
1142
1143 #define OSSSYS_BASE__INST6_SEG0                    0
1144 #define OSSSYS_BASE__INST6_SEG1                    0
1145 #define OSSSYS_BASE__INST6_SEG2                    0
1146 #define OSSSYS_BASE__INST6_SEG3                    0
1147 #define OSSSYS_BASE__INST6_SEG4                    0
1148 #define OSSSYS_BASE__INST6_SEG5                    0
1149
1150 #define PCIE0_BASE__INST0_SEG0                     0x02411800
1151 #define PCIE0_BASE__INST0_SEG1                     0x04440000
1152 #define PCIE0_BASE__INST0_SEG2                     0
1153 #define PCIE0_BASE__INST0_SEG3                     0
1154 #define PCIE0_BASE__INST0_SEG4                     0
1155 #define PCIE0_BASE__INST0_SEG5                     0
1156
1157 #define PCIE0_BASE__INST1_SEG0                     0
1158 #define PCIE0_BASE__INST1_SEG1                     0
1159 #define PCIE0_BASE__INST1_SEG2                     0
1160 #define PCIE0_BASE__INST1_SEG3                     0
1161 #define PCIE0_BASE__INST1_SEG4                     0
1162 #define PCIE0_BASE__INST1_SEG5                     0
1163
1164 #define PCIE0_BASE__INST2_SEG0                     0
1165 #define PCIE0_BASE__INST2_SEG1                     0
1166 #define PCIE0_BASE__INST2_SEG2                     0
1167 #define PCIE0_BASE__INST2_SEG3                     0
1168 #define PCIE0_BASE__INST2_SEG4                     0
1169 #define PCIE0_BASE__INST2_SEG5                     0
1170
1171 #define PCIE0_BASE__INST3_SEG0                     0
1172 #define PCIE0_BASE__INST3_SEG1                     0
1173 #define PCIE0_BASE__INST3_SEG2                     0
1174 #define PCIE0_BASE__INST3_SEG3                     0
1175 #define PCIE0_BASE__INST3_SEG4                     0
1176 #define PCIE0_BASE__INST3_SEG5                     0
1177
1178 #define PCIE0_BASE__INST4_SEG0                     0
1179 #define PCIE0_BASE__INST4_SEG1                     0
1180 #define PCIE0_BASE__INST4_SEG2                     0
1181 #define PCIE0_BASE__INST4_SEG3                     0
1182 #define PCIE0_BASE__INST4_SEG4                     0
1183 #define PCIE0_BASE__INST4_SEG5                     0
1184
1185 #define PCIE0_BASE__INST5_SEG0                     0
1186 #define PCIE0_BASE__INST5_SEG1                     0
1187 #define PCIE0_BASE__INST5_SEG2                     0
1188 #define PCIE0_BASE__INST5_SEG3                     0
1189 #define PCIE0_BASE__INST5_SEG4                     0
1190 #define PCIE0_BASE__INST5_SEG5                     0
1191
1192 #define PCIE0_BASE__INST6_SEG0                     0
1193 #define PCIE0_BASE__INST6_SEG1                     0
1194 #define PCIE0_BASE__INST6_SEG2                     0
1195 #define PCIE0_BASE__INST6_SEG3                     0
1196 #define PCIE0_BASE__INST6_SEG4                     0
1197 #define PCIE0_BASE__INST6_SEG5                     0
1198
1199 #define SDMA0_BASE__INST0_SEG0                     0x00001260
1200 #define SDMA0_BASE__INST0_SEG1                     0x02445400
1201 #define SDMA0_BASE__INST0_SEG2                     0
1202 #define SDMA0_BASE__INST0_SEG3                     0
1203 #define SDMA0_BASE__INST0_SEG4                     0
1204 #define SDMA0_BASE__INST0_SEG5                     0
1205
1206 #define SDMA0_BASE__INST1_SEG0                     0
1207 #define SDMA0_BASE__INST1_SEG1                     0
1208 #define SDMA0_BASE__INST1_SEG2                     0
1209 #define SDMA0_BASE__INST1_SEG3                     0
1210 #define SDMA0_BASE__INST1_SEG4                     0
1211 #define SDMA0_BASE__INST1_SEG5                     0
1212
1213 #define SDMA0_BASE__INST2_SEG0                     0
1214 #define SDMA0_BASE__INST2_SEG1                     0
1215 #define SDMA0_BASE__INST2_SEG2                     0
1216 #define SDMA0_BASE__INST2_SEG3                     0
1217 #define SDMA0_BASE__INST2_SEG4                     0
1218 #define SDMA0_BASE__INST2_SEG5                     0
1219
1220 #define SDMA0_BASE__INST3_SEG0                     0
1221 #define SDMA0_BASE__INST3_SEG1                     0
1222 #define SDMA0_BASE__INST3_SEG2                     0
1223 #define SDMA0_BASE__INST3_SEG3                     0
1224 #define SDMA0_BASE__INST3_SEG4                     0
1225 #define SDMA0_BASE__INST3_SEG5                     0
1226
1227 #define SDMA0_BASE__INST4_SEG0                     0
1228 #define SDMA0_BASE__INST4_SEG1                     0
1229 #define SDMA0_BASE__INST4_SEG2                     0
1230 #define SDMA0_BASE__INST4_SEG3                     0
1231 #define SDMA0_BASE__INST4_SEG4                     0
1232 #define SDMA0_BASE__INST4_SEG5                     0
1233
1234 #define SDMA0_BASE__INST5_SEG0                     0
1235 #define SDMA0_BASE__INST5_SEG1                     0
1236 #define SDMA0_BASE__INST5_SEG2                     0
1237 #define SDMA0_BASE__INST5_SEG3                     0
1238 #define SDMA0_BASE__INST5_SEG4                     0
1239 #define SDMA0_BASE__INST5_SEG5                     0
1240
1241 #define SDMA0_BASE__INST6_SEG0                     0
1242 #define SDMA0_BASE__INST6_SEG1                     0
1243 #define SDMA0_BASE__INST6_SEG2                     0
1244 #define SDMA0_BASE__INST6_SEG3                     0
1245 #define SDMA0_BASE__INST6_SEG4                     0
1246 #define SDMA0_BASE__INST6_SEG5                     0
1247
1248 #define SDMA1_BASE__INST0_SEG0                     0x00001860
1249 #define SDMA1_BASE__INST0_SEG1                     0x02445800
1250 #define SDMA1_BASE__INST0_SEG2                     0
1251 #define SDMA1_BASE__INST0_SEG3                     0
1252 #define SDMA1_BASE__INST0_SEG4                     0
1253 #define SDMA1_BASE__INST0_SEG5                     0
1254
1255 #define SDMA1_BASE__INST1_SEG0                     0x0001E000
1256 #define SDMA1_BASE__INST1_SEG1                     0x02446400
1257 #define SDMA1_BASE__INST1_SEG2                     0
1258 #define SDMA1_BASE__INST1_SEG3                     0
1259 #define SDMA1_BASE__INST1_SEG4                     0
1260 #define SDMA1_BASE__INST1_SEG5                     0
1261
1262 #define SDMA1_BASE__INST2_SEG0                     0x0001E400
1263 #define SDMA1_BASE__INST2_SEG1                     0x02446800
1264 #define SDMA1_BASE__INST2_SEG2                     0
1265 #define SDMA1_BASE__INST2_SEG3                     0
1266 #define SDMA1_BASE__INST2_SEG4                     0
1267 #define SDMA1_BASE__INST2_SEG5                     0
1268
1269 #define SDMA1_BASE__INST3_SEG0                     0x0001E800
1270 #define SDMA1_BASE__INST3_SEG1                     0x02446C00
1271 #define SDMA1_BASE__INST3_SEG2                     0
1272 #define SDMA1_BASE__INST3_SEG3                     0
1273 #define SDMA1_BASE__INST3_SEG4                     0
1274 #define SDMA1_BASE__INST3_SEG5                     0
1275
1276 #define SDMA1_BASE__INST4_SEG0                     0
1277 #define SDMA1_BASE__INST4_SEG1                     0
1278 #define SDMA1_BASE__INST4_SEG2                     0
1279 #define SDMA1_BASE__INST4_SEG3                     0
1280 #define SDMA1_BASE__INST4_SEG4                     0
1281 #define SDMA1_BASE__INST4_SEG5                     0
1282
1283 #define SDMA1_BASE__INST5_SEG0                     0
1284 #define SDMA1_BASE__INST5_SEG1                     0
1285 #define SDMA1_BASE__INST5_SEG2                     0
1286 #define SDMA1_BASE__INST5_SEG3                     0
1287 #define SDMA1_BASE__INST5_SEG4                     0
1288 #define SDMA1_BASE__INST5_SEG5                     0
1289
1290 #define SDMA1_BASE__INST6_SEG0                     0
1291 #define SDMA1_BASE__INST6_SEG1                     0
1292 #define SDMA1_BASE__INST6_SEG2                     0
1293 #define SDMA1_BASE__INST6_SEG3                     0
1294 #define SDMA1_BASE__INST6_SEG4                     0
1295 #define SDMA1_BASE__INST6_SEG5                     0
1296
1297 #define SMUIO_BASE__INST0_SEG0                     0x00016800
1298 #define SMUIO_BASE__INST0_SEG1                     0x00016A00
1299 #define SMUIO_BASE__INST0_SEG2                     0x02401000
1300 #define SMUIO_BASE__INST0_SEG3                     0x03440000
1301 #define SMUIO_BASE__INST0_SEG4                     0
1302 #define SMUIO_BASE__INST0_SEG5                     0
1303
1304 #define SMUIO_BASE__INST1_SEG0                     0
1305 #define SMUIO_BASE__INST1_SEG1                     0
1306 #define SMUIO_BASE__INST1_SEG2                     0
1307 #define SMUIO_BASE__INST1_SEG3                     0
1308 #define SMUIO_BASE__INST1_SEG4                     0
1309 #define SMUIO_BASE__INST1_SEG5                     0
1310
1311 #define SMUIO_BASE__INST2_SEG0                     0
1312 #define SMUIO_BASE__INST2_SEG1                     0
1313 #define SMUIO_BASE__INST2_SEG2                     0
1314 #define SMUIO_BASE__INST2_SEG3                     0
1315 #define SMUIO_BASE__INST2_SEG4                     0
1316 #define SMUIO_BASE__INST2_SEG5                     0
1317
1318 #define SMUIO_BASE__INST3_SEG0                     0
1319 #define SMUIO_BASE__INST3_SEG1                     0
1320 #define SMUIO_BASE__INST3_SEG2                     0
1321 #define SMUIO_BASE__INST3_SEG3                     0
1322 #define SMUIO_BASE__INST3_SEG4                     0
1323 #define SMUIO_BASE__INST3_SEG5                     0
1324
1325 #define SMUIO_BASE__INST4_SEG0                     0
1326 #define SMUIO_BASE__INST4_SEG1                     0
1327 #define SMUIO_BASE__INST4_SEG2                     0
1328 #define SMUIO_BASE__INST4_SEG3                     0
1329 #define SMUIO_BASE__INST4_SEG4                     0
1330 #define SMUIO_BASE__INST4_SEG5                     0
1331
1332 #define SMUIO_BASE__INST5_SEG0                     0
1333 #define SMUIO_BASE__INST5_SEG1                     0
1334 #define SMUIO_BASE__INST5_SEG2                     0
1335 #define SMUIO_BASE__INST5_SEG3                     0
1336 #define SMUIO_BASE__INST5_SEG4                     0
1337 #define SMUIO_BASE__INST5_SEG5                     0
1338
1339 #define SMUIO_BASE__INST6_SEG0                     0
1340 #define SMUIO_BASE__INST6_SEG1                     0
1341 #define SMUIO_BASE__INST6_SEG2                     0
1342 #define SMUIO_BASE__INST6_SEG3                     0
1343 #define SMUIO_BASE__INST6_SEG4                     0
1344 #define SMUIO_BASE__INST6_SEG5                     0
1345
1346 #define THM_BASE__INST0_SEG0                       0x00016600
1347 #define THM_BASE__INST0_SEG1                       0x02400C00
1348 #define THM_BASE__INST0_SEG2                       0
1349 #define THM_BASE__INST0_SEG3                       0
1350 #define THM_BASE__INST0_SEG4                       0
1351 #define THM_BASE__INST0_SEG5                       0
1352
1353 #define THM_BASE__INST1_SEG0                       0
1354 #define THM_BASE__INST1_SEG1                       0
1355 #define THM_BASE__INST1_SEG2                       0
1356 #define THM_BASE__INST1_SEG3                       0
1357 #define THM_BASE__INST1_SEG4                       0
1358 #define THM_BASE__INST1_SEG5                       0
1359
1360 #define THM_BASE__INST2_SEG0                       0
1361 #define THM_BASE__INST2_SEG1                       0
1362 #define THM_BASE__INST2_SEG2                       0
1363 #define THM_BASE__INST2_SEG3                       0
1364 #define THM_BASE__INST2_SEG4                       0
1365 #define THM_BASE__INST2_SEG5                       0
1366
1367 #define THM_BASE__INST3_SEG0                       0
1368 #define THM_BASE__INST3_SEG1                       0
1369 #define THM_BASE__INST3_SEG2                       0
1370 #define THM_BASE__INST3_SEG3                       0
1371 #define THM_BASE__INST3_SEG4                       0
1372 #define THM_BASE__INST3_SEG5                       0
1373
1374 #define THM_BASE__INST4_SEG0                       0
1375 #define THM_BASE__INST4_SEG1                       0
1376 #define THM_BASE__INST4_SEG2                       0
1377 #define THM_BASE__INST4_SEG3                       0
1378 #define THM_BASE__INST4_SEG4                       0
1379 #define THM_BASE__INST4_SEG5                       0
1380
1381 #define THM_BASE__INST5_SEG0                       0
1382 #define THM_BASE__INST5_SEG1                       0
1383 #define THM_BASE__INST5_SEG2                       0
1384 #define THM_BASE__INST5_SEG3                       0
1385 #define THM_BASE__INST5_SEG4                       0
1386 #define THM_BASE__INST5_SEG5                       0
1387
1388 #define THM_BASE__INST6_SEG0                       0
1389 #define THM_BASE__INST6_SEG1                       0
1390 #define THM_BASE__INST6_SEG2                       0
1391 #define THM_BASE__INST6_SEG3                       0
1392 #define THM_BASE__INST6_SEG4                       0
1393 #define THM_BASE__INST6_SEG5                       0
1394
1395 #define UMC_BASE__INST0_SEG0                       0x00014000
1396 #define UMC_BASE__INST0_SEG1                       0x00054000
1397 #define UMC_BASE__INST0_SEG2                       0x02425800
1398 #define UMC_BASE__INST0_SEG3                       0
1399 #define UMC_BASE__INST0_SEG4                       0
1400 #define UMC_BASE__INST0_SEG5                       0
1401
1402 #define UMC_BASE__INST1_SEG0                       0x00094000
1403 #define UMC_BASE__INST1_SEG1                       0x000D4000
1404 #define UMC_BASE__INST1_SEG2                       0x02425C00
1405 #define UMC_BASE__INST1_SEG3                       0
1406 #define UMC_BASE__INST1_SEG4                       0
1407 #define UMC_BASE__INST1_SEG5                       0
1408
1409 #define UMC_BASE__INST2_SEG0                       0x00114000
1410 #define UMC_BASE__INST2_SEG1                       0x00154000
1411 #define UMC_BASE__INST2_SEG2                       0x02426000
1412 #define UMC_BASE__INST2_SEG3                       0
1413 #define UMC_BASE__INST2_SEG4                       0
1414 #define UMC_BASE__INST2_SEG5                       0
1415
1416 #define UMC_BASE__INST3_SEG0                       0x00194000
1417 #define UMC_BASE__INST3_SEG1                       0x001D4000
1418 #define UMC_BASE__INST3_SEG2                       0x02426400
1419 #define UMC_BASE__INST3_SEG3                       0
1420 #define UMC_BASE__INST3_SEG4                       0
1421 #define UMC_BASE__INST3_SEG5                       0
1422
1423 #define UMC_BASE__INST4_SEG0                       0
1424 #define UMC_BASE__INST4_SEG1                       0
1425 #define UMC_BASE__INST4_SEG2                       0
1426 #define UMC_BASE__INST4_SEG3                       0
1427 #define UMC_BASE__INST4_SEG4                       0
1428 #define UMC_BASE__INST4_SEG5                       0
1429
1430 #define UMC_BASE__INST5_SEG0                       0
1431 #define UMC_BASE__INST5_SEG1                       0
1432 #define UMC_BASE__INST5_SEG2                       0
1433 #define UMC_BASE__INST5_SEG3                       0
1434 #define UMC_BASE__INST5_SEG4                       0
1435 #define UMC_BASE__INST5_SEG5                       0
1436
1437 #define UMC_BASE__INST6_SEG0                       0
1438 #define UMC_BASE__INST6_SEG1                       0
1439 #define UMC_BASE__INST6_SEG2                       0
1440 #define UMC_BASE__INST6_SEG3                       0
1441 #define UMC_BASE__INST6_SEG4                       0
1442 #define UMC_BASE__INST6_SEG5                       0
1443
1444 #define VCN_BASE__INST0_SEG0                       0x00007800
1445 #define VCN_BASE__INST0_SEG1                       0x00007E00
1446 #define VCN_BASE__INST0_SEG2                       0x02403000
1447 #define VCN_BASE__INST0_SEG3                       0
1448 #define VCN_BASE__INST0_SEG4                       0
1449 #define VCN_BASE__INST0_SEG5                       0
1450
1451 #define VCN_BASE__INST1_SEG0                       0x00007A00
1452 #define VCN_BASE__INST1_SEG1                       0x00009000
1453 #define VCN_BASE__INST1_SEG2                       0x02445000
1454 #define VCN_BASE__INST1_SEG3                       0
1455 #define VCN_BASE__INST1_SEG4                       0
1456 #define VCN_BASE__INST1_SEG5                       0
1457
1458 #define VCN_BASE__INST2_SEG0                       0
1459 #define VCN_BASE__INST2_SEG1                       0
1460 #define VCN_BASE__INST2_SEG2                       0
1461 #define VCN_BASE__INST2_SEG3                       0
1462 #define VCN_BASE__INST2_SEG4                       0
1463 #define VCN_BASE__INST2_SEG5                       0
1464
1465 #define VCN_BASE__INST3_SEG0                       0
1466 #define VCN_BASE__INST3_SEG1                       0
1467 #define VCN_BASE__INST3_SEG2                       0
1468 #define VCN_BASE__INST3_SEG3                       0
1469 #define VCN_BASE__INST3_SEG4                       0
1470 #define VCN_BASE__INST3_SEG5                       0
1471
1472 #define VCN_BASE__INST4_SEG0                       0
1473 #define VCN_BASE__INST4_SEG1                       0
1474 #define VCN_BASE__INST4_SEG2                       0
1475 #define VCN_BASE__INST4_SEG3                       0
1476 #define VCN_BASE__INST4_SEG4                       0
1477 #define VCN_BASE__INST4_SEG5                       0
1478
1479 #define VCN_BASE__INST5_SEG0                       0
1480 #define VCN_BASE__INST5_SEG1                       0
1481 #define VCN_BASE__INST5_SEG2                       0
1482 #define VCN_BASE__INST5_SEG3                       0
1483 #define VCN_BASE__INST5_SEG4                       0
1484 #define VCN_BASE__INST5_SEG5                       0
1485
1486 #define VCN_BASE__INST6_SEG0                       0
1487 #define VCN_BASE__INST6_SEG1                       0
1488 #define VCN_BASE__INST6_SEG2                       0
1489 #define VCN_BASE__INST6_SEG3                       0
1490 #define VCN_BASE__INST6_SEG4                       0
1491 #define VCN_BASE__INST6_SEG5                       0
1492
1493 #define WAFL0_BASE__INST0_SEG0                     0x02438000
1494 #define WAFL0_BASE__INST0_SEG1                     0x04880000
1495 #define WAFL0_BASE__INST0_SEG2                     0
1496 #define WAFL0_BASE__INST0_SEG3                     0
1497 #define WAFL0_BASE__INST0_SEG4                     0
1498 #define WAFL0_BASE__INST0_SEG5                     0
1499
1500 #define WAFL0_BASE__INST1_SEG0                     0
1501 #define WAFL0_BASE__INST1_SEG1                     0
1502 #define WAFL0_BASE__INST1_SEG2                     0
1503 #define WAFL0_BASE__INST1_SEG3                     0
1504 #define WAFL0_BASE__INST1_SEG4                     0
1505 #define WAFL0_BASE__INST1_SEG5                     0
1506
1507 #define WAFL0_BASE__INST2_SEG0                     0
1508 #define WAFL0_BASE__INST2_SEG1                     0
1509 #define WAFL0_BASE__INST2_SEG2                     0
1510 #define WAFL0_BASE__INST2_SEG3                     0
1511 #define WAFL0_BASE__INST2_SEG4                     0
1512 #define WAFL0_BASE__INST2_SEG5                     0
1513
1514 #define WAFL0_BASE__INST3_SEG0                     0
1515 #define WAFL0_BASE__INST3_SEG1                     0
1516 #define WAFL0_BASE__INST3_SEG2                     0
1517 #define WAFL0_BASE__INST3_SEG3                     0
1518 #define WAFL0_BASE__INST3_SEG4                     0
1519 #define WAFL0_BASE__INST3_SEG5                     0
1520
1521 #define WAFL0_BASE__INST4_SEG0                     0
1522 #define WAFL0_BASE__INST4_SEG1                     0
1523 #define WAFL0_BASE__INST4_SEG2                     0
1524 #define WAFL0_BASE__INST4_SEG3                     0
1525 #define WAFL0_BASE__INST4_SEG4                     0
1526 #define WAFL0_BASE__INST4_SEG5                     0
1527
1528 #define WAFL0_BASE__INST5_SEG0                     0
1529 #define WAFL0_BASE__INST5_SEG1                     0
1530 #define WAFL0_BASE__INST5_SEG2                     0
1531 #define WAFL0_BASE__INST5_SEG3                     0
1532 #define WAFL0_BASE__INST5_SEG4                     0
1533 #define WAFL0_BASE__INST5_SEG5                     0
1534
1535 #define WAFL0_BASE__INST6_SEG0                     0
1536 #define WAFL0_BASE__INST6_SEG1                     0
1537 #define WAFL0_BASE__INST6_SEG2                     0
1538 #define WAFL0_BASE__INST6_SEG3                     0
1539 #define WAFL0_BASE__INST6_SEG4                     0
1540 #define WAFL0_BASE__INST6_SEG5                     0
1541
1542 #define WAFL1_BASE__INST0_SEG0                     0
1543 #define WAFL1_BASE__INST0_SEG1                     0x01300000
1544 #define WAFL1_BASE__INST0_SEG2                     0x02410800
1545 #define WAFL1_BASE__INST0_SEG3                     0
1546 #define WAFL1_BASE__INST0_SEG4                     0
1547 #define WAFL1_BASE__INST0_SEG5                     0
1548
1549 #define WAFL1_BASE__INST1_SEG0                     0
1550 #define WAFL1_BASE__INST1_SEG1                     0
1551 #define WAFL1_BASE__INST1_SEG2                     0
1552 #define WAFL1_BASE__INST1_SEG3                     0
1553 #define WAFL1_BASE__INST1_SEG4                     0
1554 #define WAFL1_BASE__INST1_SEG5                     0
1555
1556 #define WAFL1_BASE__INST2_SEG0                     0
1557 #define WAFL1_BASE__INST2_SEG1                     0
1558 #define WAFL1_BASE__INST2_SEG2                     0
1559 #define WAFL1_BASE__INST2_SEG3                     0
1560 #define WAFL1_BASE__INST2_SEG4                     0
1561 #define WAFL1_BASE__INST2_SEG5                     0
1562
1563 #define WAFL1_BASE__INST3_SEG0                     0
1564 #define WAFL1_BASE__INST3_SEG1                     0
1565 #define WAFL1_BASE__INST3_SEG2                     0
1566 #define WAFL1_BASE__INST3_SEG3                     0
1567 #define WAFL1_BASE__INST3_SEG4                     0
1568 #define WAFL1_BASE__INST3_SEG5                     0
1569
1570 #define WAFL1_BASE__INST4_SEG0                     0
1571 #define WAFL1_BASE__INST4_SEG1                     0
1572 #define WAFL1_BASE__INST4_SEG2                     0
1573 #define WAFL1_BASE__INST4_SEG3                     0
1574 #define WAFL1_BASE__INST4_SEG4                     0
1575 #define WAFL1_BASE__INST4_SEG5                     0
1576
1577 #define WAFL1_BASE__INST5_SEG0                     0
1578 #define WAFL1_BASE__INST5_SEG1                     0
1579 #define WAFL1_BASE__INST5_SEG2                     0
1580 #define WAFL1_BASE__INST5_SEG3                     0
1581 #define WAFL1_BASE__INST5_SEG4                     0
1582 #define WAFL1_BASE__INST5_SEG5                     0
1583
1584 #define WAFL1_BASE__INST6_SEG0                     0
1585 #define WAFL1_BASE__INST6_SEG1                     0
1586 #define WAFL1_BASE__INST6_SEG2                     0
1587 #define WAFL1_BASE__INST6_SEG3                     0
1588 #define WAFL1_BASE__INST6_SEG4                     0
1589 #define WAFL1_BASE__INST6_SEG5                     0
1590
1591 #define XGMI0_BASE__INST0_SEG0                     0x02438C00
1592 #define XGMI0_BASE__INST0_SEG1                     0x04680000
1593 #define XGMI0_BASE__INST0_SEG2                     0x04940000
1594 #define XGMI0_BASE__INST0_SEG3                     0
1595 #define XGMI0_BASE__INST0_SEG4                     0
1596 #define XGMI0_BASE__INST0_SEG5                     0
1597
1598 #define XGMI0_BASE__INST1_SEG0                     0
1599 #define XGMI0_BASE__INST1_SEG1                     0
1600 #define XGMI0_BASE__INST1_SEG2                     0
1601 #define XGMI0_BASE__INST1_SEG3                     0
1602 #define XGMI0_BASE__INST1_SEG4                     0
1603 #define XGMI0_BASE__INST1_SEG5                     0
1604
1605 #define XGMI0_BASE__INST2_SEG0                     0
1606 #define XGMI0_BASE__INST2_SEG1                     0
1607 #define XGMI0_BASE__INST2_SEG2                     0
1608 #define XGMI0_BASE__INST2_SEG3                     0
1609 #define XGMI0_BASE__INST2_SEG4                     0
1610 #define XGMI0_BASE__INST2_SEG5                     0
1611
1612 #define XGMI0_BASE__INST3_SEG0                     0
1613 #define XGMI0_BASE__INST3_SEG1                     0
1614 #define XGMI0_BASE__INST3_SEG2                     0
1615 #define XGMI0_BASE__INST3_SEG3                     0
1616 #define XGMI0_BASE__INST3_SEG4                     0
1617 #define XGMI0_BASE__INST3_SEG5                     0
1618
1619 #define XGMI0_BASE__INST4_SEG0                     0
1620 #define XGMI0_BASE__INST4_SEG1                     0
1621 #define XGMI0_BASE__INST4_SEG2                     0
1622 #define XGMI0_BASE__INST4_SEG3                     0
1623 #define XGMI0_BASE__INST4_SEG4                     0
1624 #define XGMI0_BASE__INST4_SEG5                     0
1625
1626 #define XGMI0_BASE__INST5_SEG0                     0
1627 #define XGMI0_BASE__INST5_SEG1                     0
1628 #define XGMI0_BASE__INST5_SEG2                     0
1629 #define XGMI0_BASE__INST5_SEG3                     0
1630 #define XGMI0_BASE__INST5_SEG4                     0
1631 #define XGMI0_BASE__INST5_SEG5                     0
1632
1633 #define XGMI0_BASE__INST6_SEG0                     0
1634 #define XGMI0_BASE__INST6_SEG1                     0
1635 #define XGMI0_BASE__INST6_SEG2                     0
1636 #define XGMI0_BASE__INST6_SEG3                     0
1637 #define XGMI0_BASE__INST6_SEG4                     0
1638 #define XGMI0_BASE__INST6_SEG5                     0
1639
1640 #define XGMI1_BASE__INST0_SEG0                     0x02439000
1641 #define XGMI1_BASE__INST0_SEG1                     0x046C0000
1642 #define XGMI1_BASE__INST0_SEG2                     0x04980000
1643 #define XGMI1_BASE__INST0_SEG3                     0
1644 #define XGMI1_BASE__INST0_SEG4                     0
1645 #define XGMI1_BASE__INST0_SEG5                     0
1646
1647 #define XGMI1_BASE__INST1_SEG0                     0
1648 #define XGMI1_BASE__INST1_SEG1                     0
1649 #define XGMI1_BASE__INST1_SEG2                     0
1650 #define XGMI1_BASE__INST1_SEG3                     0
1651 #define XGMI1_BASE__INST1_SEG4                     0
1652 #define XGMI1_BASE__INST1_SEG5                     0
1653
1654 #define XGMI1_BASE__INST2_SEG0                     0
1655 #define XGMI1_BASE__INST2_SEG1                     0
1656 #define XGMI1_BASE__INST2_SEG2                     0
1657 #define XGMI1_BASE__INST2_SEG3                     0
1658 #define XGMI1_BASE__INST2_SEG4                     0
1659 #define XGMI1_BASE__INST2_SEG5                     0
1660
1661 #define XGMI1_BASE__INST3_SEG0                     0
1662 #define XGMI1_BASE__INST3_SEG1                     0
1663 #define XGMI1_BASE__INST3_SEG2                     0
1664 #define XGMI1_BASE__INST3_SEG3                     0
1665 #define XGMI1_BASE__INST3_SEG4                     0
1666 #define XGMI1_BASE__INST3_SEG5                     0
1667
1668 #define XGMI1_BASE__INST4_SEG0                     0
1669 #define XGMI1_BASE__INST4_SEG1                     0
1670 #define XGMI1_BASE__INST4_SEG2                     0
1671 #define XGMI1_BASE__INST4_SEG3                     0
1672 #define XGMI1_BASE__INST4_SEG4                     0
1673 #define XGMI1_BASE__INST4_SEG5                     0
1674
1675 #define XGMI1_BASE__INST5_SEG0                     0
1676 #define XGMI1_BASE__INST5_SEG1                     0
1677 #define XGMI1_BASE__INST5_SEG2                     0
1678 #define XGMI1_BASE__INST5_SEG3                     0
1679 #define XGMI1_BASE__INST5_SEG4                     0
1680 #define XGMI1_BASE__INST5_SEG5                     0
1681
1682 #define XGMI1_BASE__INST6_SEG0                     0
1683 #define XGMI1_BASE__INST6_SEG1                     0
1684 #define XGMI1_BASE__INST6_SEG2                     0
1685 #define XGMI1_BASE__INST6_SEG3                     0
1686 #define XGMI1_BASE__INST6_SEG4                     0
1687 #define XGMI1_BASE__INST6_SEG5                     0
1688
1689 #define XGMI2_BASE__INST0_SEG0                     0x04700000
1690 #define XGMI2_BASE__INST0_SEG1                     0x049C0000
1691 #define XGMI2_BASE__INST0_SEG2                     0
1692 #define XGMI2_BASE__INST0_SEG3                     0
1693 #define XGMI2_BASE__INST0_SEG4                     0
1694 #define XGMI2_BASE__INST0_SEG5                     0
1695
1696 #define XGMI2_BASE__INST1_SEG0                     0x04740000
1697 #define XGMI2_BASE__INST1_SEG1                     0x04A00000
1698 #define XGMI2_BASE__INST1_SEG2                     0
1699 #define XGMI2_BASE__INST1_SEG3                     0
1700 #define XGMI2_BASE__INST1_SEG4                     0
1701 #define XGMI2_BASE__INST1_SEG5                     0
1702
1703 #define XGMI2_BASE__INST2_SEG0                     0x04780000
1704 #define XGMI2_BASE__INST2_SEG1                     0x04A40000
1705 #define XGMI2_BASE__INST2_SEG2                     0
1706 #define XGMI2_BASE__INST2_SEG3                     0
1707 #define XGMI2_BASE__INST2_SEG4                     0
1708 #define XGMI2_BASE__INST2_SEG5                     0
1709
1710 #define XGMI2_BASE__INST3_SEG0                     0x047C0000
1711 #define XGMI2_BASE__INST3_SEG1                     0x04A80000
1712 #define XGMI2_BASE__INST3_SEG2                     0
1713 #define XGMI2_BASE__INST3_SEG3                     0
1714 #define XGMI2_BASE__INST3_SEG4                     0
1715 #define XGMI2_BASE__INST3_SEG5                     0
1716
1717 #define XGMI2_BASE__INST4_SEG0                     0x04800000
1718 #define XGMI2_BASE__INST4_SEG1                     0x04AC0000
1719 #define XGMI2_BASE__INST4_SEG2                     0
1720 #define XGMI2_BASE__INST4_SEG3                     0
1721 #define XGMI2_BASE__INST4_SEG4                     0
1722 #define XGMI2_BASE__INST4_SEG5                     0
1723
1724 #define XGMI2_BASE__INST5_SEG0                     0x04840000
1725 #define XGMI2_BASE__INST5_SEG1                     0x04B00000
1726 #define XGMI2_BASE__INST5_SEG2                     0
1727 #define XGMI2_BASE__INST5_SEG3                     0
1728 #define XGMI2_BASE__INST5_SEG4                     0
1729 #define XGMI2_BASE__INST5_SEG5                     0
1730
1731 #define XGMI2_BASE__INST6_SEG0                     0
1732 #define XGMI2_BASE__INST6_SEG1                     0
1733 #define XGMI2_BASE__INST6_SEG2                     0
1734 #define XGMI2_BASE__INST6_SEG3                     0
1735 #define XGMI2_BASE__INST6_SEG4                     0
1736 #define XGMI2_BASE__INST6_SEG5                     0
1737
1738 #endif