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0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "mod_info_packet.h"
0027 #include "core_types.h"
0028 #include "dc_types.h"
0029 #include "mod_shared.h"
0030 #include "mod_freesync.h"
0031 #include "dc.h"
0032 
0033 enum vsc_packet_revision {
0034     vsc_packet_undefined = 0,
0035     //01h = VSC SDP supports only 3D stereo.
0036     vsc_packet_rev1 = 1,
0037     //02h = 3D stereo + PSR.
0038     vsc_packet_rev2 = 2,
0039     //03h = 3D stereo + PSR2.
0040     vsc_packet_rev3 = 3,
0041     //04h = 3D stereo + PSR/PSR2 + Y-coordinate.
0042     vsc_packet_rev4 = 4,
0043     //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format
0044     vsc_packet_rev5 = 5,
0045 };
0046 
0047 #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
0048 #define HF_VSIF_VERSION 1
0049 
0050 // VTEM Byte Offset
0051 #define VTEM_PB0        0
0052 #define VTEM_PB1        1
0053 #define VTEM_PB2        2
0054 #define VTEM_PB3        3
0055 #define VTEM_PB4        4
0056 #define VTEM_PB5        5
0057 #define VTEM_PB6        6
0058 
0059 #define VTEM_MD0        7
0060 #define VTEM_MD1        8
0061 #define VTEM_MD2        9
0062 #define VTEM_MD3        10
0063 
0064 
0065 // VTEM Byte Masks
0066 //PB0
0067 #define MASK_VTEM_PB0__RESERVED0  0x01
0068 #define MASK_VTEM_PB0__SYNC       0x02
0069 #define MASK_VTEM_PB0__VFR        0x04
0070 #define MASK_VTEM_PB0__AFR        0x08
0071 #define MASK_VTEM_PB0__DS_TYPE    0x30
0072     //0: Periodic pseudo-static EM Data Set
0073     //1: Periodic dynamic EM Data Set
0074     //2: Unique EM Data Set
0075     //3: Reserved
0076 #define MASK_VTEM_PB0__END        0x40
0077 #define MASK_VTEM_PB0__NEW        0x80
0078 
0079 //PB1
0080 #define MASK_VTEM_PB1__RESERVED1 0xFF
0081 
0082 //PB2
0083 #define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
0084     //0: This is a Vendor Specific EM Data Set
0085     //1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
0086     //2: This EM Data Set is defined by CTA-861-G
0087     //3: This EM Data Set is defined by VESA
0088 //PB3
0089 #define MASK_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
0090 //PB4
0091 #define MASK_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
0092 //PB5
0093 #define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
0094 //PB6
0095 #define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
0096 
0097 
0098 
0099 //PB7-27 (20 bytes):
0100 //PB7 = MD0
0101 #define MASK_VTEM_MD0__VRR_EN         0x01
0102 #define MASK_VTEM_MD0__M_CONST        0x02
0103 #define MASK_VTEM_MD0__QMS_EN         0x04
0104 #define MASK_VTEM_MD0__RESERVED2      0x08
0105 #define MASK_VTEM_MD0__FVA_FACTOR_M1  0xF0
0106 
0107 //MD1
0108 #define MASK_VTEM_MD1__BASE_VFRONT    0xFF
0109 
0110 //MD2
0111 #define MASK_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
0112 #define MASK_VTEM_MD2__RB                    0x04
0113 #define MASK_VTEM_MD2__NEXT_TFR              0xF8
0114 
0115 //MD3
0116 #define MASK_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
0117 
0118 enum ColorimetryRGBDP {
0119     ColorimetryRGB_DP_sRGB               = 0,
0120     ColorimetryRGB_DP_AdobeRGB           = 3,
0121     ColorimetryRGB_DP_P3                 = 4,
0122     ColorimetryRGB_DP_CustomColorProfile = 5,
0123     ColorimetryRGB_DP_ITU_R_BT2020RGB    = 6,
0124 };
0125 enum ColorimetryYCCDP {
0126     ColorimetryYCC_DP_ITU601        = 0,
0127     ColorimetryYCC_DP_ITU709        = 1,
0128     ColorimetryYCC_DP_AdobeYCC      = 5,
0129     ColorimetryYCC_DP_ITU2020YCC    = 6,
0130     ColorimetryYCC_DP_ITU2020YCbCr  = 7,
0131 };
0132 
0133 void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
0134         struct dc_info_packet *info_packet,
0135         enum dc_color_space cs)
0136 {
0137     unsigned int vsc_packet_revision = vsc_packet_undefined;
0138     unsigned int i;
0139     unsigned int pixelEncoding = 0;
0140     unsigned int colorimetryFormat = 0;
0141     bool stereo3dSupport = false;
0142 
0143     if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) {
0144         vsc_packet_revision = vsc_packet_rev1;
0145         stereo3dSupport = true;
0146     }
0147 
0148     /* VSC packet set to 4 for PSR-SU, or 2 for PSR1 */
0149     if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
0150         vsc_packet_revision = vsc_packet_rev4;
0151     else if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
0152         vsc_packet_revision = vsc_packet_rev2;
0153 
0154     /* Update to revision 5 for extended colorimetry support */
0155     if (stream->use_vsc_sdp_for_colorimetry)
0156         vsc_packet_revision = vsc_packet_rev5;
0157 
0158     /* VSC packet not needed based on the features
0159      * supported by this DP display
0160      */
0161     if (vsc_packet_revision == vsc_packet_undefined)
0162         return;
0163 
0164     if (vsc_packet_revision == vsc_packet_rev4) {
0165         /* Secondary-data Packet ID = 0*/
0166         info_packet->hb0 = 0x00;
0167         /* 07h - Packet Type Value indicating Video
0168          * Stream Configuration packet
0169          */
0170         info_packet->hb1 = 0x07;
0171         /* 04h = VSC SDP supporting 3D stereo + PSR/PSR2 + Y-coordinate
0172          * (applies to eDP v1.4 or higher).
0173          */
0174         info_packet->hb2 = 0x04;
0175         /* 0Eh = VSC SDP supporting 3D stereo + PSR2
0176          * (HB2 = 04h), with Y-coordinate of first scan
0177          * line of the SU region
0178          */
0179         info_packet->hb3 = 0x0E;
0180 
0181         for (i = 0; i < 28; i++)
0182             info_packet->sb[i] = 0;
0183 
0184         info_packet->valid = true;
0185     }
0186 
0187     if (vsc_packet_revision == vsc_packet_rev2) {
0188         /* Secondary-data Packet ID = 0*/
0189         info_packet->hb0 = 0x00;
0190         /* 07h - Packet Type Value indicating Video
0191          * Stream Configuration packet
0192          */
0193         info_packet->hb1 = 0x07;
0194         /* 02h = VSC SDP supporting 3D stereo and PSR
0195          * (applies to eDP v1.3 or higher).
0196          */
0197         info_packet->hb2 = 0x02;
0198         /* 08h = VSC packet supporting 3D stereo + PSR
0199          * (HB2 = 02h).
0200          */
0201         info_packet->hb3 = 0x08;
0202 
0203         for (i = 0; i < 28; i++)
0204             info_packet->sb[i] = 0;
0205 
0206         info_packet->valid = true;
0207     }
0208 
0209     if (vsc_packet_revision == vsc_packet_rev1) {
0210 
0211         info_packet->hb0 = 0x00;    // Secondary-data Packet ID = 0
0212         info_packet->hb1 = 0x07;    // 07h = Packet Type Value indicating Video Stream Configuration packet
0213         info_packet->hb2 = 0x01;    // 01h = Revision number. VSC SDP supporting 3D stereo only
0214         info_packet->hb3 = 0x01;    // 01h = VSC SDP supporting 3D stereo only (HB2 = 01h).
0215 
0216         info_packet->valid = true;
0217     }
0218 
0219     if (stereo3dSupport) {
0220         /* ==============================================================================================================|
0221          * A. STEREO 3D
0222          * ==============================================================================================================|
0223          * VSC Payload (1 byte) From DP1.2 spec
0224          *
0225          * Bits 3:0 (Stereo Interface Method Code)  |  Bits 7:4 (Stereo Interface Method Specific Parameter)
0226          * -----------------------------------------------------------------------------------------------------
0227          * 0 = Non Stereo Video                     |  Must be set to 0x0
0228          * -----------------------------------------------------------------------------------------------------
0229          * 1 = Frame/Field Sequential               |  0x0: L + R view indication based on MISC1 bit 2:1
0230          *                                          |  0x1: Right when Stereo Signal = 1
0231          *                                          |  0x2: Left when Stereo Signal = 1
0232          *                                          |  (others reserved)
0233          * -----------------------------------------------------------------------------------------------------
0234          * 2 = Stacked Frame                        |  0x0: Left view is on top and right view on bottom
0235          *                                          |  (others reserved)
0236          * -----------------------------------------------------------------------------------------------------
0237          * 3 = Pixel Interleaved                    |  0x0: horiz interleaved, right view pixels on even lines
0238          *                                          |  0x1: horiz interleaved, right view pixels on odd lines
0239          *                                          |  0x2: checker board, start with left view pixel
0240          *                                          |  0x3: vertical interleaved, start with left view pixels
0241          *                                          |  0x4: vertical interleaved, start with right view pixels
0242          *                                          |  (others reserved)
0243          * -----------------------------------------------------------------------------------------------------
0244          * 4 = Side-by-side                         |  0x0: left half represents left eye view
0245          *                                          |  0x1: left half represents right eye view
0246          */
0247         switch (stream->timing.timing_3d_format) {
0248         case TIMING_3D_FORMAT_HW_FRAME_PACKING:
0249         case TIMING_3D_FORMAT_SW_FRAME_PACKING:
0250         case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
0251         case TIMING_3D_FORMAT_TB_SW_PACKED:
0252             info_packet->sb[0] = 0x02; // Stacked Frame, Left view is on top and right view on bottom.
0253             break;
0254         case TIMING_3D_FORMAT_DP_HDMI_INBAND_FA:
0255         case TIMING_3D_FORMAT_INBAND_FA:
0256             info_packet->sb[0] = 0x01; // Frame/Field Sequential, L + R view indication based on MISC1 bit 2:1
0257             break;
0258         case TIMING_3D_FORMAT_SIDE_BY_SIDE:
0259         case TIMING_3D_FORMAT_SBS_SW_PACKED:
0260             info_packet->sb[0] = 0x04; // Side-by-side
0261             break;
0262         default:
0263             info_packet->sb[0] = 0x00; // No Stereo Video, Shall be cleared to 0x0.
0264             break;
0265         }
0266 
0267     }
0268 
0269     /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication.
0270      *   Added in DP1.3, a DP Source device is allowed to indicate the pixel encoding/colorimetry
0271      *   format to the DP Sink device with VSC SDP only when the DP Sink device supports it
0272      *   (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the DPRX_FEATURE_ENUMERATION_LIST
0273      *   register (DPCD Address 02210h, bit 3) is set to 1).
0274      *   (Requires VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit set to 1 in DPCD 02210h. This
0275      *   DPCD register is exposed in the new Extended Receiver Capability field for DPCD Rev. 1.4
0276      *   (and higher). When MISC1. bit 6. is Set to 1, a Source device uses a VSC SDP to indicate
0277      *   the Pixel Encoding/Colorimetry Format and that a Sink device must ignore MISC1, bit 7, and
0278      *   MISC0, bits 7:1 (MISC1, bit 7. and MISC0, bits 7:1 become "don't care").)
0279      */
0280     if (vsc_packet_revision == vsc_packet_rev5) {
0281         /* Secondary-data Packet ID = 0 */
0282         info_packet->hb0 = 0x00;
0283         /* 07h - Packet Type Value indicating Video Stream Configuration packet */
0284         info_packet->hb1 = 0x07;
0285         /* 05h = VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/Colorimetry Format indication. */
0286         info_packet->hb2 = 0x05;
0287         /* 13h = VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/Colorimetry Format indication (HB2 = 05h). */
0288         info_packet->hb3 = 0x13;
0289 
0290         info_packet->valid = true;
0291 
0292         /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs
0293          * Data Bytes DB 18~16
0294          * Bits 3:0 (Colorimetry Format)        |  Bits 7:4 (Pixel Encoding)
0295          * ----------------------------------------------------------------------------------------------------
0296          * 0x0 = sRGB                           |  0 = RGB
0297          * 0x1 = RGB Wide Gamut Fixed Point
0298          * 0x2 = RGB Wide Gamut Floating Point
0299          * 0x3 = AdobeRGB
0300          * 0x4 = DCI-P3
0301          * 0x5 = CustomColorProfile
0302          * (others reserved)
0303          * ----------------------------------------------------------------------------------------------------
0304          * 0x0 = ITU-R BT.601                   |  1 = YCbCr444
0305          * 0x1 = ITU-R BT.709
0306          * 0x2 = xvYCC601
0307          * 0x3 = xvYCC709
0308          * 0x4 = sYCC601
0309          * 0x5 = AdobeYCC601
0310          * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
0311          * 0x7 = ITU-R BT.2020 Y'C'bC'r
0312          * (others reserved)
0313          * ----------------------------------------------------------------------------------------------------
0314          * 0x0 = ITU-R BT.601                   |  2 = YCbCr422
0315          * 0x1 = ITU-R BT.709
0316          * 0x2 = xvYCC601
0317          * 0x3 = xvYCC709
0318          * 0x4 = sYCC601
0319          * 0x5 = AdobeYCC601
0320          * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
0321          * 0x7 = ITU-R BT.2020 Y'C'bC'r
0322          * (others reserved)
0323          * ----------------------------------------------------------------------------------------------------
0324          * 0x0 = ITU-R BT.601                   |  3 = YCbCr420
0325          * 0x1 = ITU-R BT.709
0326          * 0x2 = xvYCC601
0327          * 0x3 = xvYCC709
0328          * 0x4 = sYCC601
0329          * 0x5 = AdobeYCC601
0330          * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc
0331          * 0x7 = ITU-R BT.2020 Y'C'bC'r
0332          * (others reserved)
0333          * ----------------------------------------------------------------------------------------------------
0334          * 0x0 =DICOM Part14 Grayscale          |  4 = Yonly
0335          * Display Function
0336          * (others reserved)
0337          */
0338 
0339         /* Set Pixel Encoding */
0340         switch (stream->timing.pixel_encoding) {
0341         case PIXEL_ENCODING_RGB:
0342             pixelEncoding = 0x0;  /* RGB = 0h */
0343             break;
0344         case PIXEL_ENCODING_YCBCR444:
0345             pixelEncoding = 0x1;  /* YCbCr444 = 1h */
0346             break;
0347         case PIXEL_ENCODING_YCBCR422:
0348             pixelEncoding = 0x2;  /* YCbCr422 = 2h */
0349             break;
0350         case PIXEL_ENCODING_YCBCR420:
0351             pixelEncoding = 0x3;  /* YCbCr420 = 3h */
0352             break;
0353         default:
0354             pixelEncoding = 0x0;  /* default RGB = 0h */
0355             break;
0356         }
0357 
0358         /* Set Colorimetry format based on pixel encoding */
0359         switch (stream->timing.pixel_encoding) {
0360         case PIXEL_ENCODING_RGB:
0361             if ((cs == COLOR_SPACE_SRGB) ||
0362                     (cs == COLOR_SPACE_SRGB_LIMITED))
0363                 colorimetryFormat = ColorimetryRGB_DP_sRGB;
0364             else if (cs == COLOR_SPACE_ADOBERGB)
0365                 colorimetryFormat = ColorimetryRGB_DP_AdobeRGB;
0366             else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) ||
0367                     (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
0368                 colorimetryFormat = ColorimetryRGB_DP_ITU_R_BT2020RGB;
0369             break;
0370 
0371         case PIXEL_ENCODING_YCBCR444:
0372         case PIXEL_ENCODING_YCBCR422:
0373         case PIXEL_ENCODING_YCBCR420:
0374             /* Note: xvYCC probably not supported correctly here on DP since colorspace translation
0375              * loses distinction between BT601 vs xvYCC601 in translation
0376              */
0377             if (cs == COLOR_SPACE_YCBCR601)
0378                 colorimetryFormat = ColorimetryYCC_DP_ITU601;
0379             else if (cs == COLOR_SPACE_YCBCR709)
0380                 colorimetryFormat = ColorimetryYCC_DP_ITU709;
0381             else if (cs == COLOR_SPACE_ADOBERGB)
0382                 colorimetryFormat = ColorimetryYCC_DP_AdobeYCC;
0383             else if (cs == COLOR_SPACE_2020_YCBCR)
0384                 colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr;
0385             break;
0386 
0387         default:
0388             colorimetryFormat = ColorimetryRGB_DP_sRGB;
0389             break;
0390         }
0391 
0392         info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat;
0393 
0394         /* Set color depth */
0395         switch (stream->timing.display_color_depth) {
0396         case COLOR_DEPTH_666:
0397             /* NOTE: This is actually not valid for YCbCr pixel encoding to have 6 bpc
0398              *       as of DP1.4 spec, but value of 0 probably reserved here for potential future use.
0399              */
0400             info_packet->sb[17] = 0;
0401             break;
0402         case COLOR_DEPTH_888:
0403             info_packet->sb[17] = 1;
0404             break;
0405         case COLOR_DEPTH_101010:
0406             info_packet->sb[17] = 2;
0407             break;
0408         case COLOR_DEPTH_121212:
0409             info_packet->sb[17] = 3;
0410             break;
0411         /*case COLOR_DEPTH_141414: -- NO SUCH FORMAT IN DP SPEC */
0412         case COLOR_DEPTH_161616:
0413             info_packet->sb[17] = 4;
0414             break;
0415         default:
0416             info_packet->sb[17] = 0;
0417             break;
0418         }
0419 
0420         /* all YCbCr are always limited range */
0421         if ((cs == COLOR_SPACE_SRGB_LIMITED) ||
0422                 (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE) ||
0423                 (pixelEncoding != 0x0)) {
0424             info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */
0425         }
0426 
0427         /* Content Type (Bits 2:0)
0428          *  0 = Not defined.
0429          *  1 = Graphics.
0430          *  2 = Photo.
0431          *  3 = Video.
0432          *  4 = Game.
0433          */
0434         info_packet->sb[18] = 0;
0435     }
0436 }
0437 
0438 /**
0439  *  mod_build_hf_vsif_infopacket - Prepare HDMI Vendor Specific info frame.
0440  *                                 Follows HDMI Spec to build up Vendor Specific info frame
0441  *
0442  *  @stream:      contains data we may need to construct VSIF (i.e. timing_3d_format, etc.)
0443  *  @info_packet: output structure where to store VSIF
0444  */
0445 void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream,
0446         struct dc_info_packet *info_packet)
0447 {
0448         unsigned int length = 5;
0449         bool hdmi_vic_mode = false;
0450         uint8_t checksum = 0;
0451         uint32_t i = 0;
0452         enum dc_timing_3d_format format;
0453 
0454         info_packet->valid = false;
0455         format = stream->timing.timing_3d_format;
0456         if (stream->view_format == VIEW_3D_FORMAT_NONE)
0457             format = TIMING_3D_FORMAT_NONE;
0458 
0459         if (stream->timing.hdmi_vic != 0
0460                 && stream->timing.h_total >= 3840
0461                 && stream->timing.v_total >= 2160
0462                 && format == TIMING_3D_FORMAT_NONE)
0463             hdmi_vic_mode = true;
0464 
0465         if ((format == TIMING_3D_FORMAT_NONE) && !hdmi_vic_mode)
0466             return;
0467 
0468         info_packet->sb[1] = 0x03;
0469         info_packet->sb[2] = 0x0C;
0470         info_packet->sb[3] = 0x00;
0471 
0472         if (format != TIMING_3D_FORMAT_NONE)
0473             info_packet->sb[4] = (2 << 5);
0474 
0475         else if (hdmi_vic_mode)
0476             info_packet->sb[4] = (1 << 5);
0477 
0478         switch (format) {
0479         case TIMING_3D_FORMAT_HW_FRAME_PACKING:
0480         case TIMING_3D_FORMAT_SW_FRAME_PACKING:
0481             info_packet->sb[5] = (0x0 << 4);
0482             break;
0483 
0484         case TIMING_3D_FORMAT_SIDE_BY_SIDE:
0485         case TIMING_3D_FORMAT_SBS_SW_PACKED:
0486             info_packet->sb[5] = (0x8 << 4);
0487             length = 6;
0488             break;
0489 
0490         case TIMING_3D_FORMAT_TOP_AND_BOTTOM:
0491         case TIMING_3D_FORMAT_TB_SW_PACKED:
0492             info_packet->sb[5] = (0x6 << 4);
0493             break;
0494 
0495         default:
0496             break;
0497         }
0498 
0499         if (hdmi_vic_mode)
0500             info_packet->sb[5] = stream->timing.hdmi_vic;
0501 
0502         info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR;
0503         info_packet->hb1 = 0x01;
0504         info_packet->hb2 = (uint8_t) (length);
0505 
0506         checksum += info_packet->hb0;
0507         checksum += info_packet->hb1;
0508         checksum += info_packet->hb2;
0509 
0510         for (i = 1; i <= length; i++)
0511             checksum += info_packet->sb[i];
0512 
0513         info_packet->sb[0] = (uint8_t) (0x100 - checksum);
0514 
0515         info_packet->valid = true;
0516 }
0517
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