dmub/src/dmub_srv.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "../dmub_srv.h"
0027 #include "dmub_dcn20.h"
0028 #include "dmub_dcn21.h"
0029 #include "dmub_cmd.h"
0030 #include "dmub_dcn30.h"
0031 #include "dmub_dcn301.h"
0032 #include "dmub_dcn302.h"
0033 #include "dmub_dcn303.h"
0034 #include "dmub_dcn31.h"
0035 #include "dmub_dcn315.h"
0036 #include "dmub_dcn316.h"
0037 #include "dmub_dcn32.h"
0038 #include "os_types.h"
0039 /*
0040  * Note: the DMUB service is standalone. No additional headers should be
0041  * added below or above this line unless they reside within the DMUB
0042  * folder.
0043  */
0044
0045 /* Alignment for framebuffer memory. */
0046 #define DMUB_FB_ALIGNMENT (1024 * 1024)
0047
0048 /* Stack size. */
0049 #define DMUB_STACK_SIZE (128 * 1024)
0050
0051 /* Context size. */
0052 #define DMUB_CONTEXT_SIZE (512 * 1024)
0053
0054 /* Mailbox size : Ring buffers are required for both inbox and outbox */
0055 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
0056
0057 /* Default state size if meta is absent. */
0058 #define DMUB_FW_STATE_SIZE (64 * 1024)
0059
0060 /* Default tracebuffer size if meta is absent. */
0061 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024)
0062
0063
0064 /* Default scratch mem size. */
0065 #define DMUB_SCRATCH_MEM_SIZE (256)
0066
0067 /* Number of windows in use. */
0068 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL)
0069 /* Base addresses. */
0070
0071 #define DMUB_CW0_BASE (0x60000000)
0072 #define DMUB_CW1_BASE (0x61000000)
0073 #define DMUB_CW3_BASE (0x63000000)
0074 #define DMUB_CW4_BASE (0x64000000)
0075 #define DMUB_CW5_BASE (0x65000000)
0076 #define DMUB_CW6_BASE (0x66000000)
0077
0078 #define DMUB_REGION5_BASE (0xA0000000)
0079
0080 static inline uint32_t dmub_align(uint32_t val, uint32_t factor)
0081 {
0082     return (val + factor - 1) / factor * factor;
0083 }
0084
0085 void dmub_flush_buffer_mem(const struct dmub_fb *fb)
0086 {
0087     const uint8_t *base = (const uint8_t *)fb->cpu_addr;
0088     uint8_t buf[64];
0089     uint32_t pos, end;
0090
0091     /**
0092      * Read 64-byte chunks since we don't want to store a
0093      * large temporary buffer for this purpose.
0094      */
0095     end = fb->size / sizeof(buf) * sizeof(buf);
0096
0097     for (pos = 0; pos < end; pos += sizeof(buf))
0098         dmub_memcpy(buf, base + pos, sizeof(buf));
0099
0100     /* Read anything leftover into the buffer. */
0101     if (end < fb->size)
0102         dmub_memcpy(buf, base + pos, fb->size - end);
0103 }
0104
0105 static const struct dmub_fw_meta_info *
0106 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset)
0107 {
0108     const union dmub_fw_meta *meta;
0109
0110     if (!blob || !blob_size)
0111         return NULL;
0112
0113     if (blob_size < sizeof(union dmub_fw_meta) + meta_offset)
0114         return NULL;
0115
0116     meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset -
0117                         sizeof(union dmub_fw_meta));
0118
0119     if (meta->info.magic_value != DMUB_FW_META_MAGIC)
0120         return NULL;
0121
0122     return &meta->info;
0123 }
0124
0125 static const struct dmub_fw_meta_info *
0126 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params)
0127 {
0128     const struct dmub_fw_meta_info *info = NULL;
0129
0130     if (params->fw_bss_data && params->bss_data_size) {
0131         /* Legacy metadata region. */
0132         info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data,
0133                                params->bss_data_size,
0134                                DMUB_FW_META_OFFSET);
0135     } else if (params->fw_inst_const && params->inst_const_size) {
0136         /* Combined metadata region - can be aligned to 16-bytes. */
0137         uint32_t i;
0138
0139         for (i = 0; i < 16; ++i) {
0140             info = dmub_get_fw_meta_info_from_blob(
0141                 params->fw_inst_const, params->inst_const_size, i);
0142
0143             if (info)
0144                 break;
0145         }
0146     }
0147
0148     return info;
0149 }
0150
0151 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
0152 {
0153     struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs;
0154
0155     switch (asic) {
0156     case DMUB_ASIC_DCN20:
0157     case DMUB_ASIC_DCN21:
0158     case DMUB_ASIC_DCN30:
0159     case DMUB_ASIC_DCN301:
0160     case DMUB_ASIC_DCN302:
0161     case DMUB_ASIC_DCN303:
0162         dmub->regs = &dmub_srv_dcn20_regs;
0163
0164         funcs->reset = dmub_dcn20_reset;
0165         funcs->reset_release = dmub_dcn20_reset_release;
0166         funcs->backdoor_load = dmub_dcn20_backdoor_load;
0167         funcs->setup_windows = dmub_dcn20_setup_windows;
0168         funcs->setup_mailbox = dmub_dcn20_setup_mailbox;
0169         funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr;
0170         funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr;
0171         funcs->is_supported = dmub_dcn20_is_supported;
0172         funcs->is_hw_init = dmub_dcn20_is_hw_init;
0173         funcs->set_gpint = dmub_dcn20_set_gpint;
0174         funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
0175         funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
0176         funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
0177         funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
0178         funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
0179         funcs->get_current_time = dmub_dcn20_get_current_time;
0180
0181         // Out mailbox register access functions for RN and above
0182         funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
0183         funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
0184         funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
0185
0186         //outbox0 call stacks
0187         funcs->setup_outbox0 = dmub_dcn20_setup_outbox0;
0188         funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
0189         funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
0190
0191         funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
0192
0193         if (asic == DMUB_ASIC_DCN21) {
0194             dmub->regs = &dmub_srv_dcn21_regs;
0195
0196             funcs->is_phy_init = dmub_dcn21_is_phy_init;
0197         }
0198         if (asic == DMUB_ASIC_DCN30) {
0199             dmub->regs = &dmub_srv_dcn30_regs;
0200
0201             funcs->backdoor_load = dmub_dcn30_backdoor_load;
0202             funcs->setup_windows = dmub_dcn30_setup_windows;
0203         }
0204         if (asic == DMUB_ASIC_DCN301) {
0205             dmub->regs = &dmub_srv_dcn301_regs;
0206
0207             funcs->backdoor_load = dmub_dcn30_backdoor_load;
0208             funcs->setup_windows = dmub_dcn30_setup_windows;
0209         }
0210         if (asic == DMUB_ASIC_DCN302) {
0211             dmub->regs = &dmub_srv_dcn302_regs;
0212
0213             funcs->backdoor_load = dmub_dcn30_backdoor_load;
0214             funcs->setup_windows = dmub_dcn30_setup_windows;
0215         }
0216         if (asic == DMUB_ASIC_DCN303) {
0217             dmub->regs = &dmub_srv_dcn303_regs;
0218
0219             funcs->backdoor_load = dmub_dcn30_backdoor_load;
0220             funcs->setup_windows = dmub_dcn30_setup_windows;
0221         }
0222         break;
0223
0224     case DMUB_ASIC_DCN31:
0225     case DMUB_ASIC_DCN31B:
0226     case DMUB_ASIC_DCN314:
0227     case DMUB_ASIC_DCN315:
0228     case DMUB_ASIC_DCN316:
0229         if (asic == DMUB_ASIC_DCN315)
0230             dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
0231         else if (asic == DMUB_ASIC_DCN316)
0232             dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
0233         else
0234             dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
0235         funcs->reset = dmub_dcn31_reset;
0236         funcs->reset_release = dmub_dcn31_reset_release;
0237         funcs->backdoor_load = dmub_dcn31_backdoor_load;
0238         funcs->setup_windows = dmub_dcn31_setup_windows;
0239         funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
0240         funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
0241         funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
0242         funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
0243         funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
0244         funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
0245         funcs->is_supported = dmub_dcn31_is_supported;
0246         funcs->is_hw_init = dmub_dcn31_is_hw_init;
0247         funcs->set_gpint = dmub_dcn31_set_gpint;
0248         funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
0249         funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
0250         funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout;
0251         funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
0252         funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
0253         funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
0254         //outbox0 call stacks
0255         funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
0256         funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
0257         funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
0258
0259         funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data;
0260         funcs->should_detect = dmub_dcn31_should_detect;
0261         funcs->get_current_time = dmub_dcn31_get_current_time;
0262
0263         break;
0264
0265     case DMUB_ASIC_DCN32:
0266     case DMUB_ASIC_DCN321:
0267         dmub->regs_dcn32 = &dmub_srv_dcn32_regs;
0268         funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory;
0269         funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd;
0270         funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register;
0271         funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register;
0272         funcs->reset = dmub_dcn32_reset;
0273         funcs->reset_release = dmub_dcn32_reset_release;
0274         funcs->backdoor_load = dmub_dcn32_backdoor_load;
0275         funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode;
0276         funcs->setup_windows = dmub_dcn32_setup_windows;
0277         funcs->setup_mailbox = dmub_dcn32_setup_mailbox;
0278         funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr;
0279         funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr;
0280         funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox;
0281         funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr;
0282         funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr;
0283         funcs->is_supported = dmub_dcn32_is_supported;
0284         funcs->is_hw_init = dmub_dcn32_is_hw_init;
0285         funcs->set_gpint = dmub_dcn32_set_gpint;
0286         funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked;
0287         funcs->get_gpint_response = dmub_dcn32_get_gpint_response;
0288         funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout;
0289         funcs->get_fw_status = dmub_dcn32_get_fw_boot_status;
0290         funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options;
0291         funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence;
0292
0293         /* outbox0 call stacks */
0294         funcs->setup_outbox0 = dmub_dcn32_setup_outbox0;
0295         funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr;
0296         funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr;
0297         funcs->get_current_time = dmub_dcn32_get_current_time;
0298         funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data;
0299
0300         break;
0301
0302     default:
0303         return false;
0304     }
0305
0306     return true;
0307 }
0308
0309 enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
0310                  const struct dmub_srv_create_params *params)
0311 {
0312     enum dmub_status status = DMUB_STATUS_OK;
0313
0314     dmub_memset(dmub, 0, sizeof(*dmub));
0315
0316     dmub->funcs = params->funcs;
0317     dmub->user_ctx = params->user_ctx;
0318     dmub->asic = params->asic;
0319     dmub->fw_version = params->fw_version;
0320     dmub->is_virtual = params->is_virtual;
0321
0322     /* Setup asic dependent hardware funcs. */
0323     if (!dmub_srv_hw_setup(dmub, params->asic)) {
0324         status = DMUB_STATUS_INVALID;
0325         goto cleanup;
0326     }
0327
0328     /* Override (some) hardware funcs based on user params. */
0329     if (params->hw_funcs) {
0330         if (params->hw_funcs->emul_get_inbox1_rptr)
0331             dmub->hw_funcs.emul_get_inbox1_rptr =
0332                 params->hw_funcs->emul_get_inbox1_rptr;
0333
0334         if (params->hw_funcs->emul_set_inbox1_wptr)
0335             dmub->hw_funcs.emul_set_inbox1_wptr =
0336                 params->hw_funcs->emul_set_inbox1_wptr;
0337
0338         if (params->hw_funcs->is_supported)
0339             dmub->hw_funcs.is_supported =
0340                 params->hw_funcs->is_supported;
0341     }
0342
0343     /* Sanity checks for required hw func pointers. */
0344     if (!dmub->hw_funcs.get_inbox1_rptr ||
0345         !dmub->hw_funcs.set_inbox1_wptr) {
0346         status = DMUB_STATUS_INVALID;
0347         goto cleanup;
0348     }
0349
0350 cleanup:
0351     if (status == DMUB_STATUS_OK)
0352         dmub->sw_init = true;
0353     else
0354         dmub_srv_destroy(dmub);
0355
0356     return status;
0357 }
0358
0359 void dmub_srv_destroy(struct dmub_srv *dmub)
0360 {
0361     dmub_memset(dmub, 0, sizeof(*dmub));
0362 }
0363
0364 enum dmub_status
0365 dmub_srv_calc_region_info(struct dmub_srv *dmub,
0366               const struct dmub_srv_region_params *params,
0367               struct dmub_srv_region_info *out)
0368 {
0369     struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST];
0370     struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK];
0371     struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA];
0372     struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS];
0373     struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX];
0374     struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF];
0375     struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE];
0376     struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM];
0377     const struct dmub_fw_meta_info *fw_info;
0378     uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
0379     uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
0380     uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE;
0381
0382     if (!dmub->sw_init)
0383         return DMUB_STATUS_INVALID;
0384
0385     memset(out, 0, sizeof(*out));
0386
0387     out->num_regions = DMUB_NUM_WINDOWS;
0388
0389     inst->base = 0x0;
0390     inst->top = inst->base + params->inst_const_size;
0391
0392     data->base = dmub_align(inst->top, 256);
0393     data->top = data->base + params->bss_data_size;
0394
0395     /*
0396      * All cache windows below should be aligned to the size
0397      * of the DMCUB cache line, 64 bytes.
0398      */
0399
0400     stack->base = dmub_align(data->top, 256);
0401     stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE;
0402
0403     bios->base = dmub_align(stack->top, 256);
0404     bios->top = bios->base + params->vbios_size;
0405
0406     mail->base = dmub_align(bios->top, 256);
0407     mail->top = mail->base + DMUB_MAILBOX_SIZE;
0408
0409     fw_info = dmub_get_fw_meta_info(params);
0410
0411     if (fw_info) {
0412         fw_state_size = fw_info->fw_region_size;
0413         trace_buffer_size = fw_info->trace_buffer_size;
0414
0415         /**
0416          * If DM didn't fill in a version, then fill it in based on
0417          * the firmware meta now that we have it.
0418          *
0419          * TODO: Make it easier for driver to extract this out to
0420          * pass during creation.
0421          */
0422         if (dmub->fw_version == 0)
0423             dmub->fw_version = fw_info->fw_version;
0424     }
0425
0426     trace_buff->base = dmub_align(mail->top, 256);
0427     trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);
0428
0429     fw_state->base = dmub_align(trace_buff->top, 256);
0430     fw_state->top = fw_state->base + dmub_align(fw_state_size, 64);
0431
0432     scratch_mem->base = dmub_align(fw_state->top, 256);
0433     scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64);
0434
0435     out->fb_size = dmub_align(scratch_mem->top, 4096);
0436
0437     return DMUB_STATUS_OK;
0438 }
0439
0440 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub,
0441                        const struct dmub_srv_fb_params *params,
0442                        struct dmub_srv_fb_info *out)
0443 {
0444     uint8_t *cpu_base;
0445     uint64_t gpu_base;
0446     uint32_t i;
0447
0448     if (!dmub->sw_init)
0449         return DMUB_STATUS_INVALID;
0450
0451     memset(out, 0, sizeof(*out));
0452
0453     if (params->region_info->num_regions != DMUB_NUM_WINDOWS)
0454         return DMUB_STATUS_INVALID;
0455
0456     cpu_base = (uint8_t *)params->cpu_addr;
0457     gpu_base = params->gpu_addr;
0458
0459     for (i = 0; i < DMUB_NUM_WINDOWS; ++i) {
0460         const struct dmub_region *reg =
0461             &params->region_info->regions[i];
0462
0463         out->fb[i].cpu_addr = cpu_base + reg->base;
0464         out->fb[i].gpu_addr = gpu_base + reg->base;
0465         out->fb[i].size = reg->top - reg->base;
0466     }
0467
0468     out->num_fb = DMUB_NUM_WINDOWS;
0469
0470     return DMUB_STATUS_OK;
0471 }
0472
0473 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,
0474                      bool *is_supported)
0475 {
0476     *is_supported = false;
0477
0478     if (!dmub->sw_init)
0479         return DMUB_STATUS_INVALID;
0480
0481     if (dmub->hw_funcs.is_supported)
0482         *is_supported = dmub->hw_funcs.is_supported(dmub);
0483
0484     return DMUB_STATUS_OK;
0485 }
0486
0487 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)
0488 {
0489     *is_hw_init = false;
0490
0491     if (!dmub->sw_init)
0492         return DMUB_STATUS_INVALID;
0493
0494     if (!dmub->hw_init)
0495         return DMUB_STATUS_OK;
0496
0497     if (dmub->hw_funcs.is_hw_init)
0498         *is_hw_init = dmub->hw_funcs.is_hw_init(dmub);
0499
0500     return DMUB_STATUS_OK;
0501 }
0502
0503 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
0504                   const struct dmub_srv_hw_params *params)
0505 {
0506     struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST];
0507     struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK];
0508     struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA];
0509     struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS];
0510     struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX];
0511     struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF];
0512     struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE];
0513     struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM];
0514
0515     struct dmub_rb_init_params rb_params, outbox0_rb_params;
0516     struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
0517     struct dmub_region inbox1, outbox1, outbox0;
0518
0519     if (!dmub->sw_init)
0520         return DMUB_STATUS_INVALID;
0521
0522     if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb ||
0523         !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) {
0524         ASSERT(0);
0525         return DMUB_STATUS_INVALID;
0526     }
0527
0528     dmub->fb_base = params->fb_base;
0529     dmub->fb_offset = params->fb_offset;
0530     dmub->psp_version = params->psp_version;
0531
0532     if (dmub->hw_funcs.reset)
0533         dmub->hw_funcs.reset(dmub);
0534
0535     cw0.offset.quad_part = inst_fb->gpu_addr;
0536     cw0.region.base = DMUB_CW0_BASE;
0537     cw0.region.top = cw0.region.base + inst_fb->size - 1;
0538
0539     cw1.offset.quad_part = stack_fb->gpu_addr;
0540     cw1.region.base = DMUB_CW1_BASE;
0541     cw1.region.top = cw1.region.base + stack_fb->size - 1;
0542
0543     if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory)
0544         dmub->hw_funcs.configure_dmub_in_system_memory(dmub);
0545
0546     if (params->load_inst_const && dmub->hw_funcs.backdoor_load) {
0547         /**
0548          * Read back all the instruction memory so we don't hang the
0549          * DMCUB when backdoor loading if the write from x86 hasn't been
0550          * flushed yet. This only occurs in backdoor loading.
0551          */
0552         dmub_flush_buffer_mem(inst_fb);
0553
0554         if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
0555             dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);
0556         else
0557             dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1);
0558     }
0559
0560     cw2.offset.quad_part = data_fb->gpu_addr;
0561     cw2.region.base = DMUB_CW0_BASE + inst_fb->size;
0562     cw2.region.top = cw2.region.base + data_fb->size;
0563
0564     cw3.offset.quad_part = bios_fb->gpu_addr;
0565     cw3.region.base = DMUB_CW3_BASE;
0566     cw3.region.top = cw3.region.base + bios_fb->size;
0567
0568     cw4.offset.quad_part = mail_fb->gpu_addr;
0569     cw4.region.base = DMUB_CW4_BASE;
0570     cw4.region.top = cw4.region.base + mail_fb->size;
0571
0572     /**
0573      * Doubled the mailbox region to accomodate inbox and outbox.
0574      * Note: Currently, currently total mailbox size is 16KB. It is split
0575      * equally into 8KB between inbox and outbox. If this config is
0576      * changed, then uncached base address configuration of outbox1
0577      * has to be updated in funcs->setup_out_mailbox.
0578      */
0579     inbox1.base = cw4.region.base;
0580     inbox1.top = cw4.region.base + DMUB_RB_SIZE;
0581     outbox1.base = inbox1.top;
0582     outbox1.top = cw4.region.top;
0583
0584     cw5.offset.quad_part = tracebuff_fb->gpu_addr;
0585     cw5.region.base = DMUB_CW5_BASE;
0586     cw5.region.top = cw5.region.base + tracebuff_fb->size;
0587
0588     outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET;
0589     outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET;
0590
0591     cw6.offset.quad_part = fw_state_fb->gpu_addr;
0592     cw6.region.base = DMUB_CW6_BASE;
0593     cw6.region.top = cw6.region.base + fw_state_fb->size;
0594
0595     dmub->fw_state = fw_state_fb->cpu_addr;
0596
0597     dmub->scratch_mem_fb = *scratch_mem_fb;
0598
0599     if (dmub->hw_funcs.setup_windows)
0600         dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6);
0601
0602     if (dmub->hw_funcs.setup_outbox0)
0603         dmub->hw_funcs.setup_outbox0(dmub, &outbox0);
0604
0605     if (dmub->hw_funcs.setup_mailbox)
0606         dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
0607     if (dmub->hw_funcs.setup_out_mailbox)
0608         dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
0609
0610     dmub_memset(&rb_params, 0, sizeof(rb_params));
0611     rb_params.ctx = dmub;
0612     rb_params.base_address = mail_fb->cpu_addr;
0613     rb_params.capacity = DMUB_RB_SIZE;
0614     dmub_rb_init(&dmub->inbox1_rb, &rb_params);
0615
0616     // Initialize outbox1 ring buffer
0617     rb_params.ctx = dmub;
0618     rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
0619     rb_params.capacity = DMUB_RB_SIZE;
0620     dmub_rb_init(&dmub->outbox1_rb, &rb_params);
0621
0622     dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params));
0623     outbox0_rb_params.ctx = dmub;
0624     outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET);
0625     outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64);
0626     dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params);
0627
0628     /* Report to DMUB what features are supported by current driver */
0629     if (dmub->hw_funcs.enable_dmub_boot_options)
0630         dmub->hw_funcs.enable_dmub_boot_options(dmub, params);
0631
0632     if (dmub->hw_funcs.skip_dmub_panel_power_sequence)
0633         dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub,
0634             params->skip_panel_power_sequence);
0635
0636     if (dmub->hw_funcs.reset_release)
0637         dmub->hw_funcs.reset_release(dmub);
0638
0639     dmub->hw_init = true;
0640
0641     return DMUB_STATUS_OK;
0642 }
0643
0644 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)
0645 {
0646     if (!dmub->sw_init)
0647         return DMUB_STATUS_INVALID;
0648
0649     if (dmub->hw_funcs.reset)
0650         dmub->hw_funcs.reset(dmub);
0651
0652     dmub->hw_init = false;
0653
0654     return DMUB_STATUS_OK;
0655 }
0656
0657 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub,
0658                     const union dmub_rb_cmd *cmd)
0659 {
0660     if (!dmub->hw_init)
0661         return DMUB_STATUS_INVALID;
0662
0663     if (dmub_rb_push_front(&dmub->inbox1_rb, cmd))
0664         return DMUB_STATUS_OK;
0665
0666     return DMUB_STATUS_QUEUE_FULL;
0667 }
0668
0669 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
0670 {
0671     struct dmub_rb flush_rb;
0672
0673     if (!dmub->hw_init)
0674         return DMUB_STATUS_INVALID;
0675
0676     /**
0677      * Read back all the queued commands to ensure that they've
0678      * been flushed to framebuffer memory. Otherwise DMCUB might
0679      * read back stale, fully invalid or partially invalid data.
0680      */
0681     flush_rb = dmub->inbox1_rb;
0682     flush_rb.rptr = dmub->inbox1_last_wptr;
0683     dmub_rb_flush_pending(&flush_rb);
0684
0685     dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
0686
0687     dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt;
0688
0689     return DMUB_STATUS_OK;
0690 }
0691
0692 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
0693                          uint32_t timeout_us)
0694 {
0695     uint32_t i;
0696
0697     if (!dmub->hw_init)
0698         return DMUB_STATUS_INVALID;
0699
0700     for (i = 0; i <= timeout_us; i += 100) {
0701         union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
0702
0703         if (status.bits.dal_fw && status.bits.mailbox_rdy)
0704             return DMUB_STATUS_OK;
0705
0706         udelay(100);
0707     }
0708
0709     return DMUB_STATUS_TIMEOUT;
0710 }
0711
0712 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,
0713                         uint32_t timeout_us)
0714 {
0715     uint32_t i = 0;
0716
0717     if (!dmub->hw_init)
0718         return DMUB_STATUS_INVALID;
0719
0720     if (!dmub->hw_funcs.is_phy_init)
0721         return DMUB_STATUS_OK;
0722
0723     for (i = 0; i <= timeout_us; i += 10) {
0724         if (dmub->hw_funcs.is_phy_init(dmub))
0725             return DMUB_STATUS_OK;
0726
0727         udelay(10);
0728     }
0729
0730     return DMUB_STATUS_TIMEOUT;
0731 }
0732
0733 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,
0734                     uint32_t timeout_us)
0735 {
0736     uint32_t i, rptr;
0737
0738     if (!dmub->hw_init)
0739         return DMUB_STATUS_INVALID;
0740
0741     for (i = 0; i <= timeout_us; ++i) {
0742         rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
0743
0744         if (rptr > dmub->inbox1_rb.capacity)
0745             return DMUB_STATUS_HW_FAILURE;
0746
0747         dmub->inbox1_rb.rptr = rptr;
0748
0749         if (dmub_rb_empty(&dmub->inbox1_rb))
0750             return DMUB_STATUS_OK;
0751
0752         udelay(1);
0753     }
0754
0755     return DMUB_STATUS_TIMEOUT;
0756 }
0757
0758 enum dmub_status
0759 dmub_srv_send_gpint_command(struct dmub_srv *dmub,
0760                 enum dmub_gpint_command command_code,
0761                 uint16_t param, uint32_t timeout_us)
0762 {
0763     union dmub_gpint_data_register reg;
0764     uint32_t i;
0765
0766     if (!dmub->sw_init)
0767         return DMUB_STATUS_INVALID;
0768
0769     if (!dmub->hw_funcs.set_gpint)
0770         return DMUB_STATUS_INVALID;
0771
0772     if (!dmub->hw_funcs.is_gpint_acked)
0773         return DMUB_STATUS_INVALID;
0774
0775     reg.bits.status = 1;
0776     reg.bits.command_code = command_code;
0777     reg.bits.param = param;
0778
0779     dmub->hw_funcs.set_gpint(dmub, reg);
0780
0781     for (i = 0; i < timeout_us; ++i) {
0782         udelay(1);
0783
0784         if (dmub->hw_funcs.is_gpint_acked(dmub, reg))
0785             return DMUB_STATUS_OK;
0786     }
0787
0788     return DMUB_STATUS_TIMEOUT;
0789 }
0790
0791 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
0792                          uint32_t *response)
0793 {
0794     *response = 0;
0795
0796     if (!dmub->sw_init)
0797         return DMUB_STATUS_INVALID;
0798
0799     if (!dmub->hw_funcs.get_gpint_response)
0800         return DMUB_STATUS_INVALID;
0801
0802     *response = dmub->hw_funcs.get_gpint_response(dmub);
0803
0804     return DMUB_STATUS_OK;
0805 }
0806
0807 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,
0808                          uint32_t *dataout)
0809 {
0810     *dataout = 0;
0811
0812     if (!dmub->sw_init)
0813         return DMUB_STATUS_INVALID;
0814
0815     if (!dmub->hw_funcs.get_gpint_dataout)
0816         return DMUB_STATUS_INVALID;
0817
0818     *dataout = dmub->hw_funcs.get_gpint_dataout(dmub);
0819
0820     return DMUB_STATUS_OK;
0821 }
0822
0823 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
0824                          union dmub_fw_boot_status *status)
0825 {
0826     status->all = 0;
0827
0828     if (!dmub->sw_init)
0829         return DMUB_STATUS_INVALID;
0830
0831     if (dmub->hw_funcs.get_fw_status)
0832         *status = dmub->hw_funcs.get_fw_status(dmub);
0833
0834     return DMUB_STATUS_OK;
0835 }
0836
0837 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub,
0838                           union dmub_rb_cmd *cmd)
0839 {
0840     enum dmub_status status = DMUB_STATUS_OK;
0841
0842     // Queue command
0843     status = dmub_srv_cmd_queue(dmub, cmd);
0844
0845     if (status != DMUB_STATUS_OK)
0846         return status;
0847
0848     // Execute command
0849     status = dmub_srv_cmd_execute(dmub);
0850
0851     if (status != DMUB_STATUS_OK)
0852         return status;
0853
0854     // Wait for DMUB to process command
0855     status = dmub_srv_wait_for_idle(dmub, 100000);
0856
0857     if (status != DMUB_STATUS_OK)
0858         return status;
0859
0860     // Copy data back from ring buffer into command
0861     dmub_rb_get_return_data(&dmub->inbox1_rb, cmd);
0862
0863     return status;
0864 }
0865
0866 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb,
0867                  void *entry)
0868 {
0869     const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
0870     uint64_t *dst = (uint64_t *)entry;
0871     uint8_t i;
0872     uint8_t loop_count;
0873
0874     if (rb->rptr == rb->wrpt)
0875         return false;
0876
0877     loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t);
0878     // copying data
0879     for (i = 0; i < loop_count; i++)
0880         *dst++ = *src++;
0881
0882     rb->rptr += sizeof(struct dmcub_trace_buf_entry);
0883
0884     rb->rptr %= rb->capacity;
0885
0886     return true;
0887 }
0888
0889 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)
0890 {
0891     dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub);
0892
0893     return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
0894 }
0895
0896 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
0897 {
0898     if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data)
0899         return false;
0900     dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
0901     return true;
0902 }
0903
0904 bool dmub_srv_should_detect(struct dmub_srv *dmub)
0905 {
0906     if (!dmub->hw_init || !dmub->hw_funcs.should_detect)
0907         return false;
0908
0909     return dmub->hw_funcs.should_detect(dmub);
0910 }
0911
0912 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)
0913 {
0914     if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register)
0915         return DMUB_STATUS_INVALID;
0916
0917     dmub->hw_funcs.clear_inbox0_ack_register(dmub);
0918     return DMUB_STATUS_OK;
0919 }
0920
0921 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)
0922 {
0923     uint32_t i = 0;
0924     uint32_t ack = 0;
0925
0926     if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register)
0927         return DMUB_STATUS_INVALID;
0928
0929     for (i = 0; i <= timeout_us; i++) {
0930         ack = dmub->hw_funcs.read_inbox0_ack_register(dmub);
0931         if (ack)
0932             return DMUB_STATUS_OK;
0933     }
0934     return DMUB_STATUS_TIMEOUT;
0935 }
0936
0937 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,
0938         union dmub_inbox0_data_register data)
0939 {
0940     if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd)
0941         return DMUB_STATUS_INVALID;
0942
0943     dmub->hw_funcs.send_inbox0_cmd(dmub, data);
0944     return DMUB_STATUS_OK;
0945 }