dmub/src/dmub_dcn315.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef _DMUB_DCN315_H_
0027 #define _DMUB_DCN315_H_
0028
0029 #include "dmub_dcn31.h"
0030
0031 #define DMUB_DCN315_FIELDS() \
0032     DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
0033     DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
0034     DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
0035     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
0036     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
0037     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
0038     DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
0039     DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
0040     DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
0041     DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
0042     DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
0043     DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
0044     DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
0045     DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
0046     DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
0047     DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
0048     DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
0049     DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
0050     DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
0051     DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
0052     DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
0053     DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
0054     DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
0055     DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
0056     DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
0057     DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
0058     DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
0059     DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
0060     DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
0061     DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
0062     DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
0063     DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT2_INT_EN) \
0064     DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT2_INT_ACK)
0065
0066 extern const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs;
0067
0068 #endif /* _DMUB_DCN315_H_ */