dmub/src/dmub_dcn315.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "../dmub_srv.h"
0027 #include "dmub_reg.h"
0028 #include "dmub_dcn315.h"
0029
0030 #include "dcn/dcn_3_1_5_offset.h"
0031 #include "dcn/dcn_3_1_5_sh_mask.h"
0032
0033 #define DCN_BASE__INST0_SEG0                       0x00000012
0034 #define DCN_BASE__INST0_SEG1                       0x000000C0
0035 #define DCN_BASE__INST0_SEG2                       0x000034C0
0036 #define DCN_BASE__INST0_SEG3                       0x00009000
0037 #define DCN_BASE__INST0_SEG4                       0x02403C00
0038 #define DCN_BASE__INST0_SEG5                       0
0039
0040 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
0041 #define CTX dmub
0042 #define REGS dmub->regs_dcn31
0043 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
0044
0045 /* Registers. */
0046
0047 const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs = {
0048 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
0049     {
0050         DMUB_DCN31_REGS()
0051         DMCUB_INTERNAL_REGS()
0052     },
0053 #undef DMUB_SR
0054
0055 #define DMUB_SF(reg, field) FD_MASK(reg, field),
0056     { DMUB_DCN315_FIELDS() },
0057 #undef DMUB_SF
0058
0059 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
0060     { DMUB_DCN315_FIELDS() },
0061 #undef DMUB_SF
0062 };