dmub/src/dmub_dcn31.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef _DMUB_DCN31_H_
0027 #define _DMUB_DCN31_H_
0028
0029 #include "dmub_dcn20.h"
0030
0031 struct dmub_srv;
0032
0033 /* DCN31 register definitions. */
0034
0035 #define DMUB_DCN31_REGS() \
0036     DMUB_SR(DMCUB_CNTL) \
0037     DMUB_SR(DMCUB_CNTL2) \
0038     DMUB_SR(DMCUB_SEC_CNTL) \
0039     DMUB_SR(DMCUB_INBOX0_SIZE) \
0040     DMUB_SR(DMCUB_INBOX0_RPTR) \
0041     DMUB_SR(DMCUB_INBOX0_WPTR) \
0042     DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
0043     DMUB_SR(DMCUB_INBOX1_SIZE) \
0044     DMUB_SR(DMCUB_INBOX1_RPTR) \
0045     DMUB_SR(DMCUB_INBOX1_WPTR) \
0046     DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
0047     DMUB_SR(DMCUB_OUTBOX0_SIZE) \
0048     DMUB_SR(DMCUB_OUTBOX0_RPTR) \
0049     DMUB_SR(DMCUB_OUTBOX0_WPTR) \
0050     DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
0051     DMUB_SR(DMCUB_OUTBOX1_SIZE) \
0052     DMUB_SR(DMCUB_OUTBOX1_RPTR) \
0053     DMUB_SR(DMCUB_OUTBOX1_WPTR) \
0054     DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
0055     DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
0056     DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
0057     DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
0058     DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
0059     DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
0060     DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
0061     DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
0062     DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
0063     DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
0064     DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
0065     DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
0066     DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
0067     DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
0068     DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
0069     DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
0070     DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
0071     DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
0072     DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
0073     DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
0074     DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
0075     DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
0076     DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
0077     DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
0078     DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
0079     DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
0080     DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
0081     DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
0082     DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
0083     DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
0084     DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
0085     DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
0086     DMUB_SR(DMCUB_REGION4_OFFSET) \
0087     DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
0088     DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
0089     DMUB_SR(DMCUB_REGION5_OFFSET) \
0090     DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
0091     DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
0092     DMUB_SR(DMCUB_SCRATCH0) \
0093     DMUB_SR(DMCUB_SCRATCH1) \
0094     DMUB_SR(DMCUB_SCRATCH2) \
0095     DMUB_SR(DMCUB_SCRATCH3) \
0096     DMUB_SR(DMCUB_SCRATCH4) \
0097     DMUB_SR(DMCUB_SCRATCH5) \
0098     DMUB_SR(DMCUB_SCRATCH6) \
0099     DMUB_SR(DMCUB_SCRATCH7) \
0100     DMUB_SR(DMCUB_SCRATCH8) \
0101     DMUB_SR(DMCUB_SCRATCH9) \
0102     DMUB_SR(DMCUB_SCRATCH10) \
0103     DMUB_SR(DMCUB_SCRATCH11) \
0104     DMUB_SR(DMCUB_SCRATCH12) \
0105     DMUB_SR(DMCUB_SCRATCH13) \
0106     DMUB_SR(DMCUB_SCRATCH14) \
0107     DMUB_SR(DMCUB_SCRATCH15) \
0108     DMUB_SR(DMCUB_GPINT_DATAIN1) \
0109     DMUB_SR(DMCUB_GPINT_DATAOUT) \
0110     DMUB_SR(CC_DC_PIPE_DIS) \
0111     DMUB_SR(MMHUBBUB_SOFT_RESET) \
0112     DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
0113     DMUB_SR(DCN_VM_FB_OFFSET) \
0114     DMUB_SR(DMCUB_TIMER_CURRENT) \
0115     DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
0116     DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
0117     DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
0118     DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
0119     DMUB_SR(DMCUB_INTERRUPT_ACK)
0120
0121 #define DMUB_DCN31_FIELDS() \
0122     DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
0123     DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
0124     DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
0125     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
0126     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
0127     DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
0128     DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
0129     DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
0130     DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
0131     DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
0132     DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
0133     DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
0134     DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
0135     DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
0136     DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
0137     DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
0138     DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
0139     DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
0140     DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
0141     DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
0142     DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
0143     DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
0144     DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
0145     DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
0146     DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
0147     DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
0148     DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
0149     DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
0150     DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
0151     DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
0152     DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
0153     DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
0154     DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
0155     DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS)
0156
0157 struct dmub_srv_dcn31_reg_offset {
0158 #define DMUB_SR(reg) uint32_t reg;
0159     DMUB_DCN31_REGS()
0160     DMCUB_INTERNAL_REGS()
0161 #undef DMUB_SR
0162 };
0163
0164 struct dmub_srv_dcn31_reg_shift {
0165 #define DMUB_SF(reg, field) uint8_t reg##__##field;
0166     DMUB_DCN31_FIELDS()
0167 #undef DMUB_SF
0168 };
0169
0170 struct dmub_srv_dcn31_reg_mask {
0171 #define DMUB_SF(reg, field) uint32_t reg##__##field;
0172     DMUB_DCN31_FIELDS()
0173 #undef DMUB_SF
0174 };
0175
0176 struct dmub_srv_dcn31_regs {
0177     const struct dmub_srv_dcn31_reg_offset offset;
0178     const struct dmub_srv_dcn31_reg_mask mask;
0179     const struct dmub_srv_dcn31_reg_shift shift;
0180 };
0181
0182 extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs;
0183
0184 /* Hardware functions. */
0185
0186
0187 void dmub_dcn31_init(struct dmub_srv *dmub);
0188
0189 void dmub_dcn31_reset(struct dmub_srv *dmub);
0190
0191 void dmub_dcn31_reset_release(struct dmub_srv *dmub);
0192
0193 void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
0194                   const struct dmub_window *cw0,
0195                   const struct dmub_window *cw1);
0196
0197 void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
0198                   const struct dmub_window *cw2,
0199                   const struct dmub_window *cw3,
0200                   const struct dmub_window *cw4,
0201                   const struct dmub_window *cw5,
0202                   const struct dmub_window *cw6);
0203
0204 void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
0205                   const struct dmub_region *inbox1);
0206
0207 uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);
0208
0209 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
0210
0211 void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
0212                   const struct dmub_region *outbox1);
0213
0214 uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);
0215
0216 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
0217
0218 bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);
0219
0220 bool dmub_dcn31_is_supported(struct dmub_srv *dmub);
0221
0222 void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
0223               union dmub_gpint_data_register reg);
0224
0225 bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
0226                    union dmub_gpint_data_register reg);
0227
0228 uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);
0229
0230 uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);
0231
0232 void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
0233
0234 void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
0235
0236 union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);
0237
0238 void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
0239                   const struct dmub_region *outbox0);
0240
0241 uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);
0242
0243 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
0244
0245 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);
0246
0247 void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
0248
0249 bool dmub_dcn31_should_detect(struct dmub_srv *dmub);
0250
0251 #endif /* _DMUB_DCN31_H_ */