dmub/src/dmub_dcn20.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "../dmub_srv.h"
0027 #include "dmub_reg.h"
0028 #include "dmub_dcn20.h"
0029
0030 #include "dcn/dcn_2_0_0_offset.h"
0031 #include "dcn/dcn_2_0_0_sh_mask.h"
0032 #include "soc15_hw_ip.h"
0033 #include "vega10_ip_offset.h"
0034
0035 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
0036 #define CTX dmub
0037 #define REGS dmub->regs
0038
0039 /* Registers. */
0040
0041 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
0042 #define DMUB_SR(reg) REG_OFFSET(reg),
0043     {
0044         DMUB_COMMON_REGS()
0045         DMCUB_INTERNAL_REGS()
0046     },
0047 #undef DMUB_SR
0048
0049 #define DMUB_SF(reg, field) FD_MASK(reg, field),
0050     { DMUB_COMMON_FIELDS() },
0051 #undef DMUB_SF
0052
0053 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
0054     { DMUB_COMMON_FIELDS() },
0055 #undef DMUB_SF
0056 };
0057
0058 /* Shared functions. */
0059
0060 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
0061                       uint64_t *fb_base,
0062                       uint64_t *fb_offset)
0063 {
0064     uint32_t tmp;
0065
0066     if (dmub->fb_base || dmub->fb_offset) {
0067         *fb_base = dmub->fb_base;
0068         *fb_offset = dmub->fb_offset;
0069         return;
0070     }
0071
0072     REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
0073     *fb_base = (uint64_t)tmp << 24;
0074
0075     REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
0076     *fb_offset = (uint64_t)tmp << 24;
0077 }
0078
0079 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
0080                          uint64_t fb_base,
0081                          uint64_t fb_offset,
0082                          union dmub_addr *addr_out)
0083 {
0084     addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
0085 }
0086
0087 bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
0088 {
0089     /* Cached inbox is not supported in this fw version range */
0090     return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
0091          dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
0092 }
0093
0094 void dmub_dcn20_reset(struct dmub_srv *dmub)
0095 {
0096     union dmub_gpint_data_register cmd;
0097     const uint32_t timeout = 30;
0098     uint32_t in_reset, scratch, i;
0099
0100     REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
0101
0102     if (in_reset == 0) {
0103         cmd.bits.status = 1;
0104         cmd.bits.command_code = DMUB_GPINT__STOP_FW;
0105         cmd.bits.param = 0;
0106
0107         dmub->hw_funcs.set_gpint(dmub, cmd);
0108
0109         /**
0110          * Timeout covers both the ACK and the wait
0111          * for remaining work to finish.
0112          *
0113          * This is mostly bound by the PHY disable sequence.
0114          * Each register check will be greater than 1us, so
0115          * don't bother using udelay.
0116          */
0117
0118         for (i = 0; i < timeout; ++i) {
0119             if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
0120                 break;
0121         }
0122
0123         for (i = 0; i < timeout; ++i) {
0124             scratch = dmub->hw_funcs.get_gpint_response(dmub);
0125             if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
0126                 break;
0127         }
0128
0129         /* Clear the GPINT command manually so we don't reset again. */
0130         cmd.all = 0;
0131         dmub->hw_funcs.set_gpint(dmub, cmd);
0132
0133         /* Force reset in case we timed out, DMCUB is likely hung. */
0134     }
0135
0136     REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
0137     REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
0138     REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
0139     REG_WRITE(DMCUB_INBOX1_RPTR, 0);
0140     REG_WRITE(DMCUB_INBOX1_WPTR, 0);
0141     REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
0142     REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
0143     REG_WRITE(DMCUB_SCRATCH0, 0);
0144 }
0145
0146 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
0147 {
0148     REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
0149     REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
0150     REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
0151     REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
0152 }
0153
0154 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
0155                   const struct dmub_window *cw0,
0156                   const struct dmub_window *cw1)
0157 {
0158     union dmub_addr offset;
0159     uint64_t fb_base, fb_offset;
0160
0161     dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
0162
0163     REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
0164     REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
0165              DMCUB_MEM_WRITE_SPACE, 0x3);
0166
0167     dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
0168
0169     REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
0170     REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
0171     REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
0172     REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
0173           DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
0174           DMCUB_REGION3_CW0_ENABLE, 1);
0175
0176     dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
0177
0178     REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
0179     REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
0180     REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
0181     REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
0182           DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
0183           DMCUB_REGION3_CW1_ENABLE, 1);
0184
0185     REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
0186              0x20);
0187 }
0188
0189 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
0190                   const struct dmub_window *cw2,
0191                   const struct dmub_window *cw3,
0192                   const struct dmub_window *cw4,
0193                   const struct dmub_window *cw5,
0194                   const struct dmub_window *cw6)
0195 {
0196     union dmub_addr offset;
0197     uint64_t fb_base, fb_offset;
0198
0199     dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
0200
0201     if (cw2->region.base != cw2->region.top) {
0202         dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
0203                       &offset);
0204
0205         REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
0206         REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
0207         REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
0208         REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
0209               DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
0210               DMCUB_REGION3_CW2_ENABLE, 1);
0211     } else {
0212         REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
0213         REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
0214         REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
0215         REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
0216     }
0217
0218     dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
0219
0220     REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
0221     REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
0222     REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
0223     REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
0224           DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
0225           DMCUB_REGION3_CW3_ENABLE, 1);
0226
0227     /* TODO: Move this to CW4. */
0228     dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
0229
0230     /* New firmware can support CW4. */
0231     if (dmub_dcn20_use_cached_inbox(dmub)) {
0232         REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
0233         REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
0234         REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
0235         REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
0236               DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
0237               DMCUB_REGION3_CW4_ENABLE, 1);
0238     } else {
0239         REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
0240         REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
0241         REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
0242               DMCUB_REGION4_TOP_ADDRESS,
0243               cw4->region.top - cw4->region.base - 1,
0244               DMCUB_REGION4_ENABLE, 1);
0245     }
0246
0247     dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
0248
0249     REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
0250     REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
0251     REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
0252     REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
0253           DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
0254           DMCUB_REGION3_CW5_ENABLE, 1);
0255
0256     REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
0257     REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
0258     REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
0259           DMCUB_REGION5_TOP_ADDRESS,
0260           cw5->region.top - cw5->region.base - 1,
0261           DMCUB_REGION5_ENABLE, 1);
0262
0263     dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
0264
0265     REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
0266     REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
0267     REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
0268     REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
0269           DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
0270           DMCUB_REGION3_CW6_ENABLE, 1);
0271 }
0272
0273 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
0274                   const struct dmub_region *inbox1)
0275 {
0276     /* New firmware can support CW4 for the inbox. */
0277     if (dmub_dcn20_use_cached_inbox(dmub))
0278         REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
0279     else
0280         REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
0281
0282     REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
0283 }
0284
0285 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
0286 {
0287     return REG_READ(DMCUB_INBOX1_RPTR);
0288 }
0289
0290 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
0291 {
0292     REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
0293 }
0294
0295 void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
0296                   const struct dmub_region *outbox1)
0297 {
0298     /* New firmware can support CW4 for the outbox. */
0299     if (dmub_dcn20_use_cached_inbox(dmub))
0300         REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
0301     else
0302         REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
0303
0304     REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
0305 }
0306
0307 uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
0308 {
0309     /**
0310      * outbox1 wptr register is accessed without locks (dal & dc)
0311      * and to be called only by dmub_srv_stat_get_notification()
0312      */
0313     return REG_READ(DMCUB_OUTBOX1_WPTR);
0314 }
0315
0316 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
0317 {
0318     /**
0319      * outbox1 rptr register is accessed without locks (dal & dc)
0320      * and to be called only by dmub_srv_stat_get_notification()
0321      */
0322     REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
0323 }
0324
0325 void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
0326                   const struct dmub_region *outbox0)
0327 {
0328     REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
0329
0330     REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
0331 }
0332
0333 uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
0334 {
0335     return REG_READ(DMCUB_OUTBOX0_WPTR);
0336 }
0337
0338 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
0339 {
0340     REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
0341 }
0342
0343 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
0344 {
0345     uint32_t is_hw_init;
0346
0347     REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
0348
0349     return is_hw_init != 0;
0350 }
0351
0352 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
0353 {
0354     uint32_t supported = 0;
0355
0356     REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
0357
0358     return supported;
0359 }
0360
0361 void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
0362               union dmub_gpint_data_register reg)
0363 {
0364     REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
0365 }
0366
0367 bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
0368                    union dmub_gpint_data_register reg)
0369 {
0370     union dmub_gpint_data_register test;
0371
0372     reg.bits.status = 0;
0373     test.all = REG_READ(DMCUB_GPINT_DATAIN1);
0374
0375     return test.all == reg.all;
0376 }
0377
0378 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
0379 {
0380     return REG_READ(DMCUB_SCRATCH7);
0381 }
0382
0383 union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
0384 {
0385     union dmub_fw_boot_status status;
0386
0387     status.all = REG_READ(DMCUB_SCRATCH0);
0388     return status;
0389 }
0390
0391 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
0392 {
0393     union dmub_fw_boot_options boot_options = {0};
0394
0395     REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
0396 }
0397
0398 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
0399 {
0400     union dmub_fw_boot_options boot_options;
0401     boot_options.all = REG_READ(DMCUB_SCRATCH14);
0402     boot_options.bits.skip_phy_init_panel_sequence = skip;
0403     REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
0404 }
0405
0406 uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
0407 {
0408     return REG_READ(DMCUB_TIMER_CURRENT);
0409 }
0410
0411 void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
0412 {
0413     uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
0414     uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
0415
0416     if (!dmub || !diag_data)
0417         return;
0418
0419     memset(diag_data, 0, sizeof(*diag_data));
0420
0421     diag_data->dmcub_version = dmub->fw_version;
0422
0423     diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
0424     diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
0425     diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
0426     diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
0427     diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
0428     diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
0429     diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
0430     diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
0431     diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
0432     diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
0433     diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
0434     diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
0435     diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
0436     diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
0437     diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
0438     diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
0439
0440     diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
0441     diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
0442     diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
0443
0444     diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
0445     diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
0446     diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
0447
0448     diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
0449     diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
0450     diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
0451
0452     REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
0453     diag_data->is_dmcub_enabled = is_dmub_enabled;
0454
0455     REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
0456     diag_data->is_dmcub_soft_reset = is_soft_reset;
0457
0458     REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
0459     diag_data->is_dmcub_secure_reset = is_sec_reset;
0460
0461     REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
0462     diag_data->is_traceport_en  = is_traceport_enabled;
0463
0464     REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
0465     diag_data->is_cw0_enabled = is_cw0_enabled;
0466
0467     REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
0468     diag_data->is_cw6_enabled = is_cw6_enabled;
0469 }