dmub/inc/dmub_subvp_state.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DMUB_SUBVP_STATE_H
0027 #define DMUB_SUBVP_STATE_H
0028
0029 #include "dmub_cmd.h"
0030
0031 #define DMUB_SUBVP_INST0 0
0032 #define DMUB_SUBVP_INST1 1
0033 #define SUBVP_MAX_WATERMARK 0xFFFF
0034
0035 struct dmub_subvp_hubp_state {
0036     uint32_t CURSOR0_0_CURSOR_POSITION;
0037     uint32_t CURSOR0_0_CURSOR_HOT_SPOT;
0038     uint32_t CURSOR0_0_CURSOR_DST_OFFSET;
0039     uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
0040     uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
0041     uint32_t CURSOR0_0_CURSOR_SIZE;
0042     uint32_t CURSOR0_0_CURSOR_CONTROL;
0043     uint32_t HUBPREQ0_CURSOR_SETTINGS;
0044     uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
0045     uint32_t HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE;
0046     uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
0047     uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS;
0048     uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS;
0049     uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
0050     uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
0051     uint32_t HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C;
0052     uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
0053     uint32_t HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
0054 };
0055
0056 enum subvp_error_code {
0057     DMUB_SUBVP_INVALID_STATE,
0058     DMUB_SUBVP_INVALID_TRANSITION,
0059 };
0060
0061 enum subvp_state {
0062     DMUB_SUBVP_DISABLED,
0063     DMUB_SUBVP_IDLE,
0064     DMUB_SUBVP_TRY_ACQUIRE_LOCKS,
0065     DMUB_SUBVP_WAIT_FOR_LOCKS,
0066     DMUB_SUBVP_PRECONFIGURE,
0067     DMUB_SUBVP_PREPARE,
0068     DMUB_SUBVP_ENABLE,
0069     DMUB_SUBVP_SWITCHING,
0070     DMUB_SUBVP_END,
0071     DMUB_SUBVP_RESTORE,
0072 };
0073
0074 /* Defines information for SUBVP to handle vertical interrupts. */
0075 struct dmub_subvp_vertical_interrupt_event {
0076     /**
0077      * @inst: Hardware instance of vertical interrupt.
0078      */
0079     uint8_t otg_inst;
0080
0081     /**
0082      * @pad: Align structure to 4 byte boundary.
0083      */
0084     uint8_t pad[3];
0085
0086     enum subvp_state curr_state;
0087 };
0088
0089 struct dmub_subvp_vertical_interrupt_state {
0090     /**
0091      * @events: Event list.
0092      */
0093     struct dmub_subvp_vertical_interrupt_event events[DMUB_MAX_STREAMS];
0094 };
0095
0096 struct dmub_subvp_vline_interrupt_event {
0097
0098     uint8_t hubp_inst;
0099     uint8_t pad[3];
0100 };
0101
0102 struct dmub_subvp_vline_interrupt_state {
0103     struct dmub_subvp_vline_interrupt_event events[DMUB_MAX_PLANES];
0104 };
0105
0106 struct dmub_subvp_interrupt_ctx {
0107     struct dmub_subvp_vertical_interrupt_state vertical_int;
0108     struct dmub_subvp_vline_interrupt_state vline_int;
0109 };
0110
0111 struct dmub_subvp_pipe_state {
0112     uint32_t pix_clk_100hz;
0113     uint16_t main_vblank_start;
0114     uint16_t main_vblank_end;
0115     uint16_t mall_region_lines;
0116     uint16_t prefetch_lines;
0117     uint16_t prefetch_to_mall_start_lines;
0118     uint16_t processing_delay_lines;
0119     uint8_t main_pipe_index;
0120     uint8_t phantom_pipe_index;
0121     uint16_t htotal; // htotal for main / phantom pipe
0122     uint16_t vtotal;
0123     uint16_t optc_underflow_count;
0124     uint16_t hubp_underflow_count;
0125     uint8_t pad[2];
0126 };
0127
0128 /**
0129  * struct dmub_subvp_vblank_drr_info - Store DRR state when handling
0130  * SubVP + VBLANK with DRR multi-display case.
0131  *
0132  * The info stored in this struct is only valid if drr_in_use = 1.
0133  */
0134 struct dmub_subvp_vblank_drr_info {
0135     uint8_t drr_in_use;
0136     uint8_t drr_window_size_ms; // DRR window size -- indicates largest VMIN/VMAX adjustment per frame
0137     uint16_t min_vtotal_supported;  // Min VTOTAL that supports switching in VBLANK
0138     uint16_t max_vtotal_supported;  // Max VTOTAL that can still support SubVP static scheduling requirements
0139     uint16_t prev_vmin;     // Store VMIN value before MCLK switch (used to restore after MCLK end)
0140     uint16_t prev_vmax;     // Store VMAX value before MCLK switch (used to restore after MCLK end)
0141     uint8_t use_ramping;        // Use ramping or not
0142     uint8_t pad[1];
0143 };
0144
0145 struct dmub_subvp_vblank_pipe_info {
0146     uint32_t pix_clk_100hz;
0147     uint16_t vblank_start;
0148     uint16_t vblank_end;
0149     uint16_t vstartup_start;
0150     uint16_t vtotal;
0151     uint16_t htotal;
0152     uint8_t pipe_index;
0153     uint8_t pad[1];
0154     struct dmub_subvp_vblank_drr_info drr_info; // DRR considered as part of SubVP + VBLANK case
0155 };
0156
0157 enum subvp_switch_type {
0158     DMUB_SUBVP_ONLY, // Used for SubVP only, and SubVP + VACTIVE
0159     DMUB_SUBVP_AND_SUBVP, // 2 SubVP displays
0160     DMUB_SUBVP_AND_VBLANK,
0161     DMUB_SUBVP_AND_FPO,
0162 };
0163
0164 /* SubVP state. */
0165 struct dmub_subvp_state {
0166     struct dmub_subvp_pipe_state pipe_state[DMUB_MAX_SUBVP_STREAMS];
0167     struct dmub_subvp_interrupt_ctx int_ctx;
0168     struct dmub_subvp_vblank_pipe_info vblank_info;
0169     enum subvp_state state; // current state
0170     enum subvp_switch_type switch_type; // enum take up 4 bytes (?)
0171     uint8_t mclk_pending;
0172     uint8_t num_subvp_streams;
0173     uint8_t vertical_int_margin_us;
0174     uint8_t pstate_allow_width_us;
0175     uint32_t subvp_mclk_switch_count;
0176     uint32_t subvp_wait_lock_count;
0177     uint32_t driver_wait_lock_count;
0178     uint32_t subvp_vblank_frame_count;
0179     uint16_t watermark_a_cache;
0180     uint8_t pad[2];
0181 };
0182
0183 #endif /* _DMUB_SUBVP_STATE_H_ */