irq/dcn32/irq_service_dcn32.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "include/logger_interface.h"
0028 #include "../dce110/irq_service_dce110.h"
0029
0030 #include "dcn/dcn_3_2_0_offset.h"
0031 #include "dcn/dcn_3_2_0_sh_mask.h"
0032
0033 #include "irq_service_dcn32.h"
0034
0035 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0036
0037 #define DCN_BASE__INST0_SEG2                       0x000034C0
0038
0039 static enum dc_irq_source to_dal_irq_source_dcn32(
0040         struct irq_service *irq_service,
0041         uint32_t src_id,
0042         uint32_t ext_id)
0043 {
0044     switch (src_id) {
0045     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0046         return DC_IRQ_SOURCE_VBLANK1;
0047     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0048         return DC_IRQ_SOURCE_VBLANK2;
0049     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0050         return DC_IRQ_SOURCE_VBLANK3;
0051     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0052         return DC_IRQ_SOURCE_VBLANK4;
0053     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0054         return DC_IRQ_SOURCE_VBLANK5;
0055     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0056         return DC_IRQ_SOURCE_VBLANK6;
0057     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0058         return DC_IRQ_SOURCE_DC1_VLINE0;
0059     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0060         return DC_IRQ_SOURCE_DC2_VLINE0;
0061     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0062         return DC_IRQ_SOURCE_DC3_VLINE0;
0063     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0064         return DC_IRQ_SOURCE_DC4_VLINE0;
0065     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0066         return DC_IRQ_SOURCE_DC5_VLINE0;
0067     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0068         return DC_IRQ_SOURCE_DC6_VLINE0;
0069     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0070         return DC_IRQ_SOURCE_PFLIP1;
0071     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0072         return DC_IRQ_SOURCE_PFLIP2;
0073     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0074         return DC_IRQ_SOURCE_PFLIP3;
0075     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0076         return DC_IRQ_SOURCE_PFLIP4;
0077     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0078         return DC_IRQ_SOURCE_PFLIP5;
0079     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0080         return DC_IRQ_SOURCE_PFLIP6;
0081     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0082         return DC_IRQ_SOURCE_VUPDATE1;
0083     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0084         return DC_IRQ_SOURCE_VUPDATE2;
0085     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0086         return DC_IRQ_SOURCE_VUPDATE3;
0087     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0088         return DC_IRQ_SOURCE_VUPDATE4;
0089     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0090         return DC_IRQ_SOURCE_VUPDATE5;
0091     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0092         return DC_IRQ_SOURCE_VUPDATE6;
0093     case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
0094         return DC_IRQ_SOURCE_DMCUB_OUTBOX;
0095     case DCN_1_0__SRCID__DC_HPD1_INT:
0096         /* generic src_id for all HPD and HPDRX interrupts */
0097         switch (ext_id) {
0098         case DCN_1_0__CTXID__DC_HPD1_INT:
0099             return DC_IRQ_SOURCE_HPD1;
0100         case DCN_1_0__CTXID__DC_HPD2_INT:
0101             return DC_IRQ_SOURCE_HPD2;
0102         case DCN_1_0__CTXID__DC_HPD3_INT:
0103             return DC_IRQ_SOURCE_HPD3;
0104         case DCN_1_0__CTXID__DC_HPD4_INT:
0105             return DC_IRQ_SOURCE_HPD4;
0106         case DCN_1_0__CTXID__DC_HPD5_INT:
0107             return DC_IRQ_SOURCE_HPD5;
0108         case DCN_1_0__CTXID__DC_HPD6_INT:
0109             return DC_IRQ_SOURCE_HPD6;
0110         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0111             return DC_IRQ_SOURCE_HPD1RX;
0112         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0113             return DC_IRQ_SOURCE_HPD2RX;
0114         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0115             return DC_IRQ_SOURCE_HPD3RX;
0116         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0117             return DC_IRQ_SOURCE_HPD4RX;
0118         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0119             return DC_IRQ_SOURCE_HPD5RX;
0120         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0121             return DC_IRQ_SOURCE_HPD6RX;
0122         default:
0123             return DC_IRQ_SOURCE_INVALID;
0124         }
0125         break;
0126
0127     default:
0128         return DC_IRQ_SOURCE_INVALID;
0129     }
0130 }
0131
0132 static bool hpd_ack(
0133     struct irq_service *irq_service,
0134     const struct irq_source_info *info)
0135 {
0136     uint32_t addr = info->status_reg;
0137     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0138     uint32_t current_status =
0139         get_reg_field_value(
0140             value,
0141             HPD0_DC_HPD_INT_STATUS,
0142             DC_HPD_SENSE_DELAYED);
0143
0144     dal_irq_service_ack_generic(irq_service, info);
0145
0146     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0147
0148     set_reg_field_value(
0149         value,
0150         current_status ? 0 : 1,
0151         HPD0_DC_HPD_INT_CONTROL,
0152         DC_HPD_INT_POLARITY);
0153
0154     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0155
0156     return true;
0157 }
0158
0159 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0160     .set = NULL,
0161     .ack = hpd_ack
0162 };
0163
0164 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0165     .set = NULL,
0166     .ack = NULL
0167 };
0168
0169 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0170     .set = NULL,
0171     .ack = NULL
0172 };
0173
0174 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0175     .set = NULL,
0176     .ack = NULL
0177 };
0178
0179 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0180     .set = NULL,
0181     .ack = NULL
0182 };
0183
0184 static const struct irq_source_info_funcs outbox_irq_info_funcs = {
0185     .set = NULL,
0186     .ack = NULL
0187 };
0188
0189 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0190     .set = NULL,
0191     .ack = NULL
0192 };
0193
0194 #undef BASE_INNER
0195 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0196
0197 /* compile time expand base address. */
0198 #define BASE(seg) \
0199     BASE_INNER(seg)
0200
0201 #define SRI(reg_name, block, id)\
0202     BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0203             reg ## block ## id ## _ ## reg_name
0204
0205 #define SRI_DMUB(reg_name)\
0206     BASE(reg ## reg_name ## _BASE_IDX) + \
0207             reg ## reg_name
0208
0209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0210     .enable_reg = SRI(reg1, block, reg_num),\
0211     .enable_mask = \
0212         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0213     .enable_value = {\
0214         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0215         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0216     },\
0217     .ack_reg = SRI(reg2, block, reg_num),\
0218     .ack_mask = \
0219         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0220     .ack_value = \
0221         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0222
0223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0224     .enable_reg = SRI_DMUB(reg1),\
0225     .enable_mask = \
0226         reg1 ## __ ## mask1 ## _MASK,\
0227     .enable_value = {\
0228         reg1 ## __ ## mask1 ## _MASK,\
0229         ~reg1 ## __ ## mask1 ## _MASK \
0230     },\
0231     .ack_reg = SRI_DMUB(reg2),\
0232     .ack_mask = \
0233         reg2 ## __ ## mask2 ## _MASK,\
0234     .ack_value = \
0235         reg2 ## __ ## mask2 ## _MASK \
0236
0237 #define hpd_int_entry(reg_num)\
0238     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0239         IRQ_REG_ENTRY(HPD, reg_num,\
0240             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0241             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0242         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0243         .funcs = &hpd_irq_info_funcs\
0244     }
0245
0246 #define hpd_rx_int_entry(reg_num)\
0247     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0248         IRQ_REG_ENTRY(HPD, reg_num,\
0249             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0250             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0251         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0252         .funcs = &hpd_rx_irq_info_funcs\
0253     }
0254 #define pflip_int_entry(reg_num)\
0255     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0256         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0257             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0258             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0259         .funcs = &pflip_irq_info_funcs\
0260     }
0261
0262 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0263  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0264  */
0265 #define vupdate_no_lock_int_entry(reg_num)\
0266     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0267         IRQ_REG_ENTRY(OTG, reg_num,\
0268             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0269             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0270         .funcs = &vupdate_no_lock_irq_info_funcs\
0271     }
0272
0273 #define vblank_int_entry(reg_num)\
0274     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0275         IRQ_REG_ENTRY(OTG, reg_num,\
0276             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0277             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0278         .funcs = &vblank_irq_info_funcs\
0279 }
0280
0281 #define vline0_int_entry(reg_num)\
0282     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0283         IRQ_REG_ENTRY(OTG, reg_num,\
0284             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0285             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0286         .funcs = &vline0_irq_info_funcs\
0287     }
0288 #define dmub_outbox_int_entry()\
0289     [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
0290         IRQ_REG_ENTRY_DMUB(\
0291             DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
0292             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
0293         .funcs = &outbox_irq_info_funcs\
0294     }
0295
0296 #define dummy_irq_entry() \
0297     {\
0298         .funcs = &dummy_irq_info_funcs\
0299     }
0300
0301 #define i2c_int_entry(reg_num) \
0302     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0303
0304 #define dp_sink_int_entry(reg_num) \
0305     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0306
0307 #define gpio_pad_int_entry(reg_num) \
0308     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0309
0310 #define dc_underflow_int_entry(reg_num) \
0311     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0312
0313 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0314     .set = dal_irq_service_dummy_set,
0315     .ack = dal_irq_service_dummy_ack
0316 };
0317
0318 static const struct irq_source_info
0319 irq_source_info_dcn32[DAL_IRQ_SOURCES_NUMBER] = {
0320     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0321     hpd_int_entry(0),
0322     hpd_int_entry(1),
0323     hpd_int_entry(2),
0324     hpd_int_entry(3),
0325     hpd_int_entry(4),
0326     hpd_rx_int_entry(0),
0327     hpd_rx_int_entry(1),
0328     hpd_rx_int_entry(2),
0329     hpd_rx_int_entry(3),
0330     hpd_rx_int_entry(4),
0331     i2c_int_entry(1),
0332     i2c_int_entry(2),
0333     i2c_int_entry(3),
0334     i2c_int_entry(4),
0335     i2c_int_entry(5),
0336     i2c_int_entry(6),
0337     dp_sink_int_entry(1),
0338     dp_sink_int_entry(2),
0339     dp_sink_int_entry(3),
0340     dp_sink_int_entry(4),
0341     dp_sink_int_entry(5),
0342     dp_sink_int_entry(6),
0343     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0344     pflip_int_entry(0),
0345     pflip_int_entry(1),
0346     pflip_int_entry(2),
0347     pflip_int_entry(3),
0348     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0349     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0350     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0351     gpio_pad_int_entry(0),
0352     gpio_pad_int_entry(1),
0353     gpio_pad_int_entry(2),
0354     gpio_pad_int_entry(3),
0355     gpio_pad_int_entry(4),
0356     gpio_pad_int_entry(5),
0357     gpio_pad_int_entry(6),
0358     gpio_pad_int_entry(7),
0359     gpio_pad_int_entry(8),
0360     gpio_pad_int_entry(9),
0361     gpio_pad_int_entry(10),
0362     gpio_pad_int_entry(11),
0363     gpio_pad_int_entry(12),
0364     gpio_pad_int_entry(13),
0365     gpio_pad_int_entry(14),
0366     gpio_pad_int_entry(15),
0367     gpio_pad_int_entry(16),
0368     gpio_pad_int_entry(17),
0369     gpio_pad_int_entry(18),
0370     gpio_pad_int_entry(19),
0371     gpio_pad_int_entry(20),
0372     gpio_pad_int_entry(21),
0373     gpio_pad_int_entry(22),
0374     gpio_pad_int_entry(23),
0375     gpio_pad_int_entry(24),
0376     gpio_pad_int_entry(25),
0377     gpio_pad_int_entry(26),
0378     gpio_pad_int_entry(27),
0379     gpio_pad_int_entry(28),
0380     gpio_pad_int_entry(29),
0381     gpio_pad_int_entry(30),
0382     dc_underflow_int_entry(1),
0383     dc_underflow_int_entry(2),
0384     dc_underflow_int_entry(3),
0385     dc_underflow_int_entry(4),
0386     dc_underflow_int_entry(5),
0387     dc_underflow_int_entry(6),
0388     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0389     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0390     vupdate_no_lock_int_entry(0),
0391     vupdate_no_lock_int_entry(1),
0392     vupdate_no_lock_int_entry(2),
0393     vupdate_no_lock_int_entry(3),
0394     vblank_int_entry(0),
0395     vblank_int_entry(1),
0396     vblank_int_entry(2),
0397     vblank_int_entry(3),
0398     vline0_int_entry(0),
0399     vline0_int_entry(1),
0400     vline0_int_entry(2),
0401     vline0_int_entry(3),
0402     [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
0403     [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
0404     dmub_outbox_int_entry(),
0405 };
0406
0407 static const struct irq_service_funcs irq_service_funcs_dcn32 = {
0408         .to_dal_irq_source = to_dal_irq_source_dcn32
0409 };
0410
0411 static void dcn32_irq_construct(
0412     struct irq_service *irq_service,
0413     struct irq_service_init_data *init_data)
0414 {
0415     dal_irq_service_construct(irq_service, init_data);
0416
0417     irq_service->info = irq_source_info_dcn32;
0418     irq_service->funcs = &irq_service_funcs_dcn32;
0419 }
0420
0421 struct irq_service *dal_irq_service_dcn32_create(
0422     struct irq_service_init_data *init_data)
0423 {
0424     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0425                           GFP_KERNEL);
0426
0427     if (!irq_service)
0428         return NULL;
0429
0430     dcn32_irq_construct(irq_service, init_data);
0431     return irq_service;
0432 }