irq/dcn315/irq_service_dcn315.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "include/logger_interface.h"
0028 #include "../dce110/irq_service_dce110.h"
0029
0030
0031 #include "dcn/dcn_3_1_5_offset.h"
0032 #include "dcn/dcn_3_1_5_sh_mask.h"
0033
0034 #include "irq_service_dcn315.h"
0035
0036 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0037
0038 #define DCN_BASE__INST0_SEG0                       0x00000012
0039 #define DCN_BASE__INST0_SEG1                       0x000000C0
0040 #define DCN_BASE__INST0_SEG2                       0x000034C0
0041 #define DCN_BASE__INST0_SEG3                       0x00009000
0042 #define DCN_BASE__INST0_SEG4                       0x02403C00
0043 #define DCN_BASE__INST0_SEG5                       0
0044
0045 static enum dc_irq_source to_dal_irq_source_dcn315(
0046         struct irq_service *irq_service,
0047         uint32_t src_id,
0048         uint32_t ext_id)
0049 {
0050     switch (src_id) {
0051     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0052         return DC_IRQ_SOURCE_VBLANK1;
0053     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0054         return DC_IRQ_SOURCE_VBLANK2;
0055     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0056         return DC_IRQ_SOURCE_VBLANK3;
0057     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0058         return DC_IRQ_SOURCE_VBLANK4;
0059     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0060         return DC_IRQ_SOURCE_VBLANK5;
0061     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0062         return DC_IRQ_SOURCE_VBLANK6;
0063     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0064         return DC_IRQ_SOURCE_DC1_VLINE0;
0065     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0066         return DC_IRQ_SOURCE_DC2_VLINE0;
0067     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0068         return DC_IRQ_SOURCE_DC3_VLINE0;
0069     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0070         return DC_IRQ_SOURCE_DC4_VLINE0;
0071     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0072         return DC_IRQ_SOURCE_DC5_VLINE0;
0073     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0074         return DC_IRQ_SOURCE_DC6_VLINE0;
0075     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0076         return DC_IRQ_SOURCE_PFLIP1;
0077     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0078         return DC_IRQ_SOURCE_PFLIP2;
0079     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0080         return DC_IRQ_SOURCE_PFLIP3;
0081     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0082         return DC_IRQ_SOURCE_PFLIP4;
0083     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0084         return DC_IRQ_SOURCE_PFLIP5;
0085     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0086         return DC_IRQ_SOURCE_PFLIP6;
0087     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0088         return DC_IRQ_SOURCE_VUPDATE1;
0089     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0090         return DC_IRQ_SOURCE_VUPDATE2;
0091     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0092         return DC_IRQ_SOURCE_VUPDATE3;
0093     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0094         return DC_IRQ_SOURCE_VUPDATE4;
0095     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0096         return DC_IRQ_SOURCE_VUPDATE5;
0097     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0098         return DC_IRQ_SOURCE_VUPDATE6;
0099     case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
0100         return DC_IRQ_SOURCE_DMCUB_OUTBOX;
0101     case DCN_1_0__SRCID__DC_HPD1_INT:
0102         /* generic src_id for all HPD and HPDRX interrupts */
0103         switch (ext_id) {
0104         case DCN_1_0__CTXID__DC_HPD1_INT:
0105             return DC_IRQ_SOURCE_HPD1;
0106         case DCN_1_0__CTXID__DC_HPD2_INT:
0107             return DC_IRQ_SOURCE_HPD2;
0108         case DCN_1_0__CTXID__DC_HPD3_INT:
0109             return DC_IRQ_SOURCE_HPD3;
0110         case DCN_1_0__CTXID__DC_HPD4_INT:
0111             return DC_IRQ_SOURCE_HPD4;
0112         case DCN_1_0__CTXID__DC_HPD5_INT:
0113             return DC_IRQ_SOURCE_HPD5;
0114         case DCN_1_0__CTXID__DC_HPD6_INT:
0115             return DC_IRQ_SOURCE_HPD6;
0116         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0117             return DC_IRQ_SOURCE_HPD1RX;
0118         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0119             return DC_IRQ_SOURCE_HPD2RX;
0120         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0121             return DC_IRQ_SOURCE_HPD3RX;
0122         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0123             return DC_IRQ_SOURCE_HPD4RX;
0124         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0125             return DC_IRQ_SOURCE_HPD5RX;
0126         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0127             return DC_IRQ_SOURCE_HPD6RX;
0128         default:
0129             return DC_IRQ_SOURCE_INVALID;
0130         }
0131         break;
0132
0133     default:
0134         return DC_IRQ_SOURCE_INVALID;
0135     }
0136 }
0137
0138 static bool hpd_ack(
0139     struct irq_service *irq_service,
0140     const struct irq_source_info *info)
0141 {
0142     uint32_t addr = info->status_reg;
0143     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0144     uint32_t current_status =
0145         get_reg_field_value(
0146             value,
0147             HPD0_DC_HPD_INT_STATUS,
0148             DC_HPD_SENSE_DELAYED);
0149
0150     dal_irq_service_ack_generic(irq_service, info);
0151
0152     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0153
0154     set_reg_field_value(
0155         value,
0156         current_status ? 0 : 1,
0157         HPD0_DC_HPD_INT_CONTROL,
0158         DC_HPD_INT_POLARITY);
0159
0160     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0161
0162     return true;
0163 }
0164
0165 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0166     .set = NULL,
0167     .ack = hpd_ack
0168 };
0169
0170 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0171     .set = NULL,
0172     .ack = NULL
0173 };
0174
0175 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0176     .set = NULL,
0177     .ack = NULL
0178 };
0179
0180 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0181     .set = NULL,
0182     .ack = NULL
0183 };
0184
0185 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0186     .set = NULL,
0187     .ack = NULL
0188 };
0189
0190 static const struct irq_source_info_funcs outbox_irq_info_funcs = {
0191     .set = NULL,
0192     .ack = NULL
0193 };
0194
0195 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0196     .set = NULL,
0197     .ack = NULL
0198 };
0199
0200 #undef BASE_INNER
0201 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0202
0203 /* compile time expand base address. */
0204 #define BASE(seg) \
0205     BASE_INNER(seg)
0206
0207 #define SRI(reg_name, block, id)\
0208     BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0209             reg ## block ## id ## _ ## reg_name
0210
0211 #define SRI_DMUB(reg_name)\
0212     BASE(reg ## reg_name ## _BASE_IDX) + \
0213             reg ## reg_name
0214
0215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0216     .enable_reg = SRI(reg1, block, reg_num),\
0217     .enable_mask = \
0218         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0219     .enable_value = {\
0220         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0221         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0222     },\
0223     .ack_reg = SRI(reg2, block, reg_num),\
0224     .ack_mask = \
0225         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0226     .ack_value = \
0227         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0228
0229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0230     .enable_reg = SRI_DMUB(reg1),\
0231     .enable_mask = \
0232         reg1 ## __ ## mask1 ## _MASK,\
0233     .enable_value = {\
0234         reg1 ## __ ## mask1 ## _MASK,\
0235         ~reg1 ## __ ## mask1 ## _MASK \
0236     },\
0237     .ack_reg = SRI_DMUB(reg2),\
0238     .ack_mask = \
0239         reg2 ## __ ## mask2 ## _MASK,\
0240     .ack_value = \
0241         reg2 ## __ ## mask2 ## _MASK \
0242
0243 #define hpd_int_entry(reg_num)\
0244     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0245         IRQ_REG_ENTRY(HPD, reg_num,\
0246             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0247             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0248         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0249         .funcs = &hpd_irq_info_funcs\
0250     }
0251
0252 #define hpd_rx_int_entry(reg_num)\
0253     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0254         IRQ_REG_ENTRY(HPD, reg_num,\
0255             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0256             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0257         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0258         .funcs = &hpd_rx_irq_info_funcs\
0259     }
0260 #define pflip_int_entry(reg_num)\
0261     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0262         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0263             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0264             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0265         .funcs = &pflip_irq_info_funcs\
0266     }
0267
0268 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0269  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0270  */
0271 #define vupdate_no_lock_int_entry(reg_num)\
0272     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0273         IRQ_REG_ENTRY(OTG, reg_num,\
0274             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0275             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0276         .funcs = &vupdate_no_lock_irq_info_funcs\
0277     }
0278
0279 #define vblank_int_entry(reg_num)\
0280     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0281         IRQ_REG_ENTRY(OTG, reg_num,\
0282             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0283             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0284         .funcs = &vblank_irq_info_funcs\
0285     }
0286
0287 #define vline0_int_entry(reg_num)\
0288     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0289         IRQ_REG_ENTRY(OTG, reg_num,\
0290             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0291             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0292         .funcs = &vline0_irq_info_funcs\
0293     }
0294 #define dmub_outbox_int_entry()\
0295     [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
0296         IRQ_REG_ENTRY_DMUB(\
0297             DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
0298             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
0299         .funcs = &outbox_irq_info_funcs\
0300     }
0301
0302 #define dummy_irq_entry() \
0303     {\
0304         .funcs = &dummy_irq_info_funcs\
0305     }
0306
0307 #define i2c_int_entry(reg_num) \
0308     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0309
0310 #define dp_sink_int_entry(reg_num) \
0311     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0312
0313 #define gpio_pad_int_entry(reg_num) \
0314     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0315
0316 #define dc_underflow_int_entry(reg_num) \
0317     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0318
0319 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0320     .set = dal_irq_service_dummy_set,
0321     .ack = dal_irq_service_dummy_ack
0322 };
0323
0324 static const struct irq_source_info
0325 irq_source_info_dcn315[DAL_IRQ_SOURCES_NUMBER] = {
0326     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0327     hpd_int_entry(0),
0328     hpd_int_entry(1),
0329     hpd_int_entry(2),
0330     hpd_int_entry(3),
0331     hpd_int_entry(4),
0332     hpd_rx_int_entry(0),
0333     hpd_rx_int_entry(1),
0334     hpd_rx_int_entry(2),
0335     hpd_rx_int_entry(3),
0336     hpd_rx_int_entry(4),
0337     i2c_int_entry(1),
0338     i2c_int_entry(2),
0339     i2c_int_entry(3),
0340     i2c_int_entry(4),
0341     i2c_int_entry(5),
0342     i2c_int_entry(6),
0343     dp_sink_int_entry(1),
0344     dp_sink_int_entry(2),
0345     dp_sink_int_entry(3),
0346     dp_sink_int_entry(4),
0347     dp_sink_int_entry(5),
0348     dp_sink_int_entry(6),
0349     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0350     pflip_int_entry(0),
0351     pflip_int_entry(1),
0352     pflip_int_entry(2),
0353     pflip_int_entry(3),
0354     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0355     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0356     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0357     gpio_pad_int_entry(0),
0358     gpio_pad_int_entry(1),
0359     gpio_pad_int_entry(2),
0360     gpio_pad_int_entry(3),
0361     gpio_pad_int_entry(4),
0362     gpio_pad_int_entry(5),
0363     gpio_pad_int_entry(6),
0364     gpio_pad_int_entry(7),
0365     gpio_pad_int_entry(8),
0366     gpio_pad_int_entry(9),
0367     gpio_pad_int_entry(10),
0368     gpio_pad_int_entry(11),
0369     gpio_pad_int_entry(12),
0370     gpio_pad_int_entry(13),
0371     gpio_pad_int_entry(14),
0372     gpio_pad_int_entry(15),
0373     gpio_pad_int_entry(16),
0374     gpio_pad_int_entry(17),
0375     gpio_pad_int_entry(18),
0376     gpio_pad_int_entry(19),
0377     gpio_pad_int_entry(20),
0378     gpio_pad_int_entry(21),
0379     gpio_pad_int_entry(22),
0380     gpio_pad_int_entry(23),
0381     gpio_pad_int_entry(24),
0382     gpio_pad_int_entry(25),
0383     gpio_pad_int_entry(26),
0384     gpio_pad_int_entry(27),
0385     gpio_pad_int_entry(28),
0386     gpio_pad_int_entry(29),
0387     gpio_pad_int_entry(30),
0388     dc_underflow_int_entry(1),
0389     dc_underflow_int_entry(2),
0390     dc_underflow_int_entry(3),
0391     dc_underflow_int_entry(4),
0392     dc_underflow_int_entry(5),
0393     dc_underflow_int_entry(6),
0394     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0395     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0396     vupdate_no_lock_int_entry(0),
0397     vupdate_no_lock_int_entry(1),
0398     vupdate_no_lock_int_entry(2),
0399     vupdate_no_lock_int_entry(3),
0400     vblank_int_entry(0),
0401     vblank_int_entry(1),
0402     vblank_int_entry(2),
0403     vblank_int_entry(3),
0404     vline0_int_entry(0),
0405     vline0_int_entry(1),
0406     vline0_int_entry(2),
0407     vline0_int_entry(3),
0408     [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
0409     [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
0410     dmub_outbox_int_entry(),
0411 };
0412
0413 static const struct irq_service_funcs irq_service_funcs_dcn315 = {
0414         .to_dal_irq_source = to_dal_irq_source_dcn315
0415 };
0416
0417 static void dcn315_irq_construct(
0418     struct irq_service *irq_service,
0419     struct irq_service_init_data *init_data)
0420 {
0421     dal_irq_service_construct(irq_service, init_data);
0422
0423     irq_service->info = irq_source_info_dcn315;
0424     irq_service->funcs = &irq_service_funcs_dcn315;
0425 }
0426
0427 struct irq_service *dal_irq_service_dcn315_create(
0428     struct irq_service_init_data *init_data)
0429 {
0430     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0431                           GFP_KERNEL);
0432
0433     if (!irq_service)
0434         return NULL;
0435
0436     dcn315_irq_construct(irq_service, init_data);
0437     return irq_service;
0438 }