irq/dcn314/irq_service_dcn314.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #include "dm_services.h"
0028 #include "include/logger_interface.h"
0029 #include "../dce110/irq_service_dce110.h"
0030
0031
0032 #include "dcn/dcn_3_1_4_offset.h"
0033 #include "dcn/dcn_3_1_4_sh_mask.h"
0034
0035 #include "irq_service_dcn314.h"
0036
0037 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0038
0039 #define DCN_BASE__INST0_SEG2                       0x000034C0
0040
0041 static enum dc_irq_source to_dal_irq_source_dcn314(
0042         struct irq_service *irq_service,
0043         uint32_t src_id,
0044         uint32_t ext_id)
0045 {
0046     switch (src_id) {
0047     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0048         return DC_IRQ_SOURCE_VBLANK1;
0049     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0050         return DC_IRQ_SOURCE_VBLANK2;
0051     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0052         return DC_IRQ_SOURCE_VBLANK3;
0053     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0054         return DC_IRQ_SOURCE_VBLANK4;
0055     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0056         return DC_IRQ_SOURCE_VBLANK5;
0057     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0058         return DC_IRQ_SOURCE_VBLANK6;
0059     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0060         return DC_IRQ_SOURCE_DC1_VLINE0;
0061     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0062         return DC_IRQ_SOURCE_DC2_VLINE0;
0063     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0064         return DC_IRQ_SOURCE_DC3_VLINE0;
0065     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0066         return DC_IRQ_SOURCE_DC4_VLINE0;
0067     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0068         return DC_IRQ_SOURCE_DC5_VLINE0;
0069     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0070         return DC_IRQ_SOURCE_DC6_VLINE0;
0071     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0072         return DC_IRQ_SOURCE_PFLIP1;
0073     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0074         return DC_IRQ_SOURCE_PFLIP2;
0075     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0076         return DC_IRQ_SOURCE_PFLIP3;
0077     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0078         return DC_IRQ_SOURCE_PFLIP4;
0079     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0080         return DC_IRQ_SOURCE_PFLIP5;
0081     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0082         return DC_IRQ_SOURCE_PFLIP6;
0083     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0084         return DC_IRQ_SOURCE_VUPDATE1;
0085     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0086         return DC_IRQ_SOURCE_VUPDATE2;
0087     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0088         return DC_IRQ_SOURCE_VUPDATE3;
0089     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0090         return DC_IRQ_SOURCE_VUPDATE4;
0091     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0092         return DC_IRQ_SOURCE_VUPDATE5;
0093     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0094         return DC_IRQ_SOURCE_VUPDATE6;
0095     case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
0096         return DC_IRQ_SOURCE_DMCUB_OUTBOX;
0097     case DCN_1_0__SRCID__DC_HPD1_INT:
0098         /* generic src_id for all HPD and HPDRX interrupts */
0099         switch (ext_id) {
0100         case DCN_1_0__CTXID__DC_HPD1_INT:
0101             return DC_IRQ_SOURCE_HPD1;
0102         case DCN_1_0__CTXID__DC_HPD2_INT:
0103             return DC_IRQ_SOURCE_HPD2;
0104         case DCN_1_0__CTXID__DC_HPD3_INT:
0105             return DC_IRQ_SOURCE_HPD3;
0106         case DCN_1_0__CTXID__DC_HPD4_INT:
0107             return DC_IRQ_SOURCE_HPD4;
0108         case DCN_1_0__CTXID__DC_HPD5_INT:
0109             return DC_IRQ_SOURCE_HPD5;
0110         case DCN_1_0__CTXID__DC_HPD6_INT:
0111             return DC_IRQ_SOURCE_HPD6;
0112         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0113             return DC_IRQ_SOURCE_HPD1RX;
0114         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0115             return DC_IRQ_SOURCE_HPD2RX;
0116         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0117             return DC_IRQ_SOURCE_HPD3RX;
0118         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0119             return DC_IRQ_SOURCE_HPD4RX;
0120         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0121             return DC_IRQ_SOURCE_HPD5RX;
0122         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0123             return DC_IRQ_SOURCE_HPD6RX;
0124         default:
0125             return DC_IRQ_SOURCE_INVALID;
0126         }
0127         break;
0128
0129     default:
0130         return DC_IRQ_SOURCE_INVALID;
0131     }
0132 }
0133
0134 static bool hpd_ack(
0135     struct irq_service *irq_service,
0136     const struct irq_source_info *info)
0137 {
0138     uint32_t addr = info->status_reg;
0139     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0140     uint32_t current_status =
0141         get_reg_field_value(
0142             value,
0143             HPD0_DC_HPD_INT_STATUS,
0144             DC_HPD_SENSE_DELAYED);
0145
0146     dal_irq_service_ack_generic(irq_service, info);
0147
0148     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0149
0150     set_reg_field_value(
0151         value,
0152         current_status ? 0 : 1,
0153         HPD0_DC_HPD_INT_CONTROL,
0154         DC_HPD_INT_POLARITY);
0155
0156     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0157
0158     return true;
0159 }
0160
0161 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0162     .set = NULL,
0163     .ack = hpd_ack
0164 };
0165
0166 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0167     .set = NULL,
0168     .ack = NULL
0169 };
0170
0171 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0172     .set = NULL,
0173     .ack = NULL
0174 };
0175
0176 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0177     .set = NULL,
0178     .ack = NULL
0179 };
0180
0181 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0182     .set = NULL,
0183     .ack = NULL
0184 };
0185
0186 static const struct irq_source_info_funcs outbox_irq_info_funcs = {
0187     .set = NULL,
0188     .ack = NULL
0189 };
0190
0191 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0192     .set = NULL,
0193     .ack = NULL
0194 };
0195
0196 #undef BASE_INNER
0197 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0198
0199 /* compile time expand base address. */
0200 #define BASE(seg) \
0201     BASE_INNER(seg)
0202
0203 #define SRI(reg_name, block, id)\
0204     (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0205             reg ## block ## id ## _ ## reg_name)
0206
0207 #define SRI_DMUB(reg_name)\
0208     (BASE(reg ## reg_name ## _BASE_IDX) + \
0209             reg ## reg_name)
0210
0211 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0212     .enable_reg = SRI(reg1, block, reg_num),\
0213     .enable_mask = \
0214         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0215     .enable_value = {\
0216         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0217         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0218     },\
0219     .ack_reg = SRI(reg2, block, reg_num),\
0220     .ack_mask = \
0221         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0222     .ack_value = \
0223         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0224
0225 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0226     .enable_reg = SRI_DMUB(reg1),\
0227     .enable_mask = \
0228         reg1 ## __ ## mask1 ## _MASK,\
0229     .enable_value = {\
0230         reg1 ## __ ## mask1 ## _MASK,\
0231         ~reg1 ## __ ## mask1 ## _MASK \
0232     },\
0233     .ack_reg = SRI_DMUB(reg2),\
0234     .ack_mask = \
0235         reg2 ## __ ## mask2 ## _MASK,\
0236     .ack_value = \
0237         reg2 ## __ ## mask2 ## _MASK \
0238
0239 #define hpd_int_entry(reg_num)\
0240     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0241         IRQ_REG_ENTRY(HPD, reg_num,\
0242             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0243             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0244         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0245         .funcs = &hpd_irq_info_funcs\
0246     }
0247
0248 #define hpd_rx_int_entry(reg_num)\
0249     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0250         IRQ_REG_ENTRY(HPD, reg_num,\
0251             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0252             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0253         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0254         .funcs = &hpd_rx_irq_info_funcs\
0255     }
0256 #define pflip_int_entry(reg_num)\
0257     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0258         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0259             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0260             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0261         .funcs = &pflip_irq_info_funcs\
0262     }
0263
0264 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0265  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0266  */
0267 #define vupdate_no_lock_int_entry(reg_num)\
0268     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0269         IRQ_REG_ENTRY(OTG, reg_num,\
0270             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0271             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0272         .funcs = &vupdate_no_lock_irq_info_funcs\
0273     }
0274
0275 #define vblank_int_entry(reg_num)\
0276     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0277         IRQ_REG_ENTRY(OTG, reg_num,\
0278             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0279             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0280         .funcs = &vblank_irq_info_funcs\
0281     }
0282
0283 #define vline0_int_entry(reg_num)\
0284     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0285         IRQ_REG_ENTRY(OTG, reg_num,\
0286             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0287             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0288         .funcs = &vline0_irq_info_funcs\
0289     }
0290 #define dmub_outbox_int_entry()\
0291     [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
0292         IRQ_REG_ENTRY_DMUB(\
0293             DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
0294             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
0295         .funcs = &outbox_irq_info_funcs\
0296     }
0297
0298 #define dummy_irq_entry() \
0299     {\
0300         .funcs = &dummy_irq_info_funcs\
0301     }
0302
0303 #define i2c_int_entry(reg_num) \
0304     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0305
0306 #define dp_sink_int_entry(reg_num) \
0307     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0308
0309 #define gpio_pad_int_entry(reg_num) \
0310     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0311
0312 #define dc_underflow_int_entry(reg_num) \
0313     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0314
0315 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0316     .set = dal_irq_service_dummy_set,
0317     .ack = dal_irq_service_dummy_ack
0318 };
0319
0320 static const struct irq_source_info
0321 irq_source_info_dcn314[DAL_IRQ_SOURCES_NUMBER] = {
0322     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0323     hpd_int_entry(0),
0324     hpd_int_entry(1),
0325     hpd_int_entry(2),
0326     hpd_int_entry(3),
0327     hpd_int_entry(4),
0328     hpd_rx_int_entry(0),
0329     hpd_rx_int_entry(1),
0330     hpd_rx_int_entry(2),
0331     hpd_rx_int_entry(3),
0332     hpd_rx_int_entry(4),
0333     i2c_int_entry(1),
0334     i2c_int_entry(2),
0335     i2c_int_entry(3),
0336     i2c_int_entry(4),
0337     i2c_int_entry(5),
0338     i2c_int_entry(6),
0339     dp_sink_int_entry(1),
0340     dp_sink_int_entry(2),
0341     dp_sink_int_entry(3),
0342     dp_sink_int_entry(4),
0343     dp_sink_int_entry(5),
0344     dp_sink_int_entry(6),
0345     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0346     pflip_int_entry(0),
0347     pflip_int_entry(1),
0348     pflip_int_entry(2),
0349     pflip_int_entry(3),
0350     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0351     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0352     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0353     gpio_pad_int_entry(0),
0354     gpio_pad_int_entry(1),
0355     gpio_pad_int_entry(2),
0356     gpio_pad_int_entry(3),
0357     gpio_pad_int_entry(4),
0358     gpio_pad_int_entry(5),
0359     gpio_pad_int_entry(6),
0360     gpio_pad_int_entry(7),
0361     gpio_pad_int_entry(8),
0362     gpio_pad_int_entry(9),
0363     gpio_pad_int_entry(10),
0364     gpio_pad_int_entry(11),
0365     gpio_pad_int_entry(12),
0366     gpio_pad_int_entry(13),
0367     gpio_pad_int_entry(14),
0368     gpio_pad_int_entry(15),
0369     gpio_pad_int_entry(16),
0370     gpio_pad_int_entry(17),
0371     gpio_pad_int_entry(18),
0372     gpio_pad_int_entry(19),
0373     gpio_pad_int_entry(20),
0374     gpio_pad_int_entry(21),
0375     gpio_pad_int_entry(22),
0376     gpio_pad_int_entry(23),
0377     gpio_pad_int_entry(24),
0378     gpio_pad_int_entry(25),
0379     gpio_pad_int_entry(26),
0380     gpio_pad_int_entry(27),
0381     gpio_pad_int_entry(28),
0382     gpio_pad_int_entry(29),
0383     gpio_pad_int_entry(30),
0384     dc_underflow_int_entry(1),
0385     dc_underflow_int_entry(2),
0386     dc_underflow_int_entry(3),
0387     dc_underflow_int_entry(4),
0388     dc_underflow_int_entry(5),
0389     dc_underflow_int_entry(6),
0390     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0391     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0392     vupdate_no_lock_int_entry(0),
0393     vupdate_no_lock_int_entry(1),
0394     vupdate_no_lock_int_entry(2),
0395     vupdate_no_lock_int_entry(3),
0396     vblank_int_entry(0),
0397     vblank_int_entry(1),
0398     vblank_int_entry(2),
0399     vblank_int_entry(3),
0400     vline0_int_entry(0),
0401     vline0_int_entry(1),
0402     vline0_int_entry(2),
0403     vline0_int_entry(3),
0404     [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
0405     [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
0406     dmub_outbox_int_entry(),
0407 };
0408
0409 static const struct irq_service_funcs irq_service_funcs_dcn314 = {
0410         .to_dal_irq_source = to_dal_irq_source_dcn314
0411 };
0412
0413 static void dcn314_irq_construct(
0414     struct irq_service *irq_service,
0415     struct irq_service_init_data *init_data)
0416 {
0417     dal_irq_service_construct(irq_service, init_data);
0418
0419     irq_service->info = irq_source_info_dcn314;
0420     irq_service->funcs = &irq_service_funcs_dcn314;
0421 }
0422
0423 struct irq_service *dal_irq_service_dcn314_create(
0424     struct irq_service_init_data *init_data)
0425 {
0426     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0427                           GFP_KERNEL);
0428
0429     if (!irq_service)
0430         return NULL;
0431
0432     dcn314_irq_construct(irq_service, init_data);
0433     return irq_service;
0434 }