irq/dcn31/irq_service_dcn31.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "include/logger_interface.h"
0028 #include "../dce110/irq_service_dce110.h"
0029
0030
0031 #include "yellow_carp_offset.h"
0032 #include "dcn/dcn_3_1_2_offset.h"
0033 #include "dcn/dcn_3_1_2_sh_mask.h"
0034
0035 #include "irq_service_dcn31.h"
0036
0037 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0038
0039 static enum dc_irq_source to_dal_irq_source_dcn31(struct irq_service *irq_service,
0040                           uint32_t src_id,
0041                           uint32_t ext_id)
0042 {
0043     switch (src_id) {
0044     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0045         return DC_IRQ_SOURCE_VBLANK1;
0046     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0047         return DC_IRQ_SOURCE_VBLANK2;
0048     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0049         return DC_IRQ_SOURCE_VBLANK3;
0050     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0051         return DC_IRQ_SOURCE_VBLANK4;
0052     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0053         return DC_IRQ_SOURCE_VBLANK5;
0054     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0055         return DC_IRQ_SOURCE_VBLANK6;
0056     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0057         return DC_IRQ_SOURCE_DC1_VLINE0;
0058     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0059         return DC_IRQ_SOURCE_DC2_VLINE0;
0060     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0061         return DC_IRQ_SOURCE_DC3_VLINE0;
0062     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0063         return DC_IRQ_SOURCE_DC4_VLINE0;
0064     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0065         return DC_IRQ_SOURCE_DC5_VLINE0;
0066     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0067         return DC_IRQ_SOURCE_DC6_VLINE0;
0068     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0069         return DC_IRQ_SOURCE_PFLIP1;
0070     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0071         return DC_IRQ_SOURCE_PFLIP2;
0072     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0073         return DC_IRQ_SOURCE_PFLIP3;
0074     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0075         return DC_IRQ_SOURCE_PFLIP4;
0076     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0077         return DC_IRQ_SOURCE_PFLIP5;
0078     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0079         return DC_IRQ_SOURCE_PFLIP6;
0080     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0081         return DC_IRQ_SOURCE_VUPDATE1;
0082     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0083         return DC_IRQ_SOURCE_VUPDATE2;
0084     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0085         return DC_IRQ_SOURCE_VUPDATE3;
0086     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0087         return DC_IRQ_SOURCE_VUPDATE4;
0088     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0089         return DC_IRQ_SOURCE_VUPDATE5;
0090     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0091         return DC_IRQ_SOURCE_VUPDATE6;
0092     case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
0093         return DC_IRQ_SOURCE_DMCUB_OUTBOX;
0094     case DCN_1_0__SRCID__DC_HPD1_INT:
0095         /* generic src_id for all HPD and HPDRX interrupts */
0096         switch (ext_id) {
0097         case DCN_1_0__CTXID__DC_HPD1_INT:
0098             return DC_IRQ_SOURCE_HPD1;
0099         case DCN_1_0__CTXID__DC_HPD2_INT:
0100             return DC_IRQ_SOURCE_HPD2;
0101         case DCN_1_0__CTXID__DC_HPD3_INT:
0102             return DC_IRQ_SOURCE_HPD3;
0103         case DCN_1_0__CTXID__DC_HPD4_INT:
0104             return DC_IRQ_SOURCE_HPD4;
0105         case DCN_1_0__CTXID__DC_HPD5_INT:
0106             return DC_IRQ_SOURCE_HPD5;
0107         case DCN_1_0__CTXID__DC_HPD6_INT:
0108             return DC_IRQ_SOURCE_HPD6;
0109         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0110             return DC_IRQ_SOURCE_HPD1RX;
0111         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0112             return DC_IRQ_SOURCE_HPD2RX;
0113         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0114             return DC_IRQ_SOURCE_HPD3RX;
0115         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0116             return DC_IRQ_SOURCE_HPD4RX;
0117         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0118             return DC_IRQ_SOURCE_HPD5RX;
0119         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0120             return DC_IRQ_SOURCE_HPD6RX;
0121         default:
0122             return DC_IRQ_SOURCE_INVALID;
0123         }
0124         break;
0125
0126     default:
0127         return DC_IRQ_SOURCE_INVALID;
0128     }
0129 }
0130
0131 static bool hpd_ack(
0132     struct irq_service *irq_service,
0133     const struct irq_source_info *info)
0134 {
0135     uint32_t addr = info->status_reg;
0136     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0137     uint32_t current_status =
0138         get_reg_field_value(
0139             value,
0140             HPD0_DC_HPD_INT_STATUS,
0141             DC_HPD_SENSE_DELAYED);
0142
0143     dal_irq_service_ack_generic(irq_service, info);
0144
0145     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0146
0147     set_reg_field_value(
0148         value,
0149         current_status ? 0 : 1,
0150         HPD0_DC_HPD_INT_CONTROL,
0151         DC_HPD_INT_POLARITY);
0152
0153     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0154
0155     return true;
0156 }
0157
0158 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0159     .set = NULL,
0160     .ack = hpd_ack
0161 };
0162
0163 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0164     .set = NULL,
0165     .ack = NULL
0166 };
0167
0168 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0169     .set = NULL,
0170     .ack = NULL
0171 };
0172
0173 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0174     .set = NULL,
0175     .ack = NULL
0176 };
0177
0178 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0179     .set = NULL,
0180     .ack = NULL
0181 };
0182
0183 static const struct irq_source_info_funcs outbox_irq_info_funcs = {
0184     .set = NULL,
0185     .ack = NULL
0186 };
0187
0188 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0189     .set = NULL,
0190     .ack = NULL
0191 };
0192
0193 #undef BASE_INNER
0194 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0195
0196 /* compile time expand base address. */
0197 #define BASE(seg) \
0198     BASE_INNER(seg)
0199
0200 #define SRI(reg_name, block, id)\
0201     BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0202             reg ## block ## id ## _ ## reg_name
0203
0204 #define SRI_DMUB(reg_name)\
0205     BASE(reg ## reg_name ## _BASE_IDX) + \
0206             reg ## reg_name
0207
0208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0209     .enable_reg = SRI(reg1, block, reg_num),\
0210     .enable_mask = \
0211         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0212     .enable_value = {\
0213         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0214         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0215     },\
0216     .ack_reg = SRI(reg2, block, reg_num),\
0217     .ack_mask = \
0218         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0219     .ack_value = \
0220         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0221
0222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0223     .enable_reg = SRI_DMUB(reg1),\
0224     .enable_mask = \
0225         reg1 ## __ ## mask1 ## _MASK,\
0226     .enable_value = {\
0227         reg1 ## __ ## mask1 ## _MASK,\
0228         ~reg1 ## __ ## mask1 ## _MASK \
0229     },\
0230     .ack_reg = SRI_DMUB(reg2),\
0231     .ack_mask = \
0232         reg2 ## __ ## mask2 ## _MASK,\
0233     .ack_value = \
0234         reg2 ## __ ## mask2 ## _MASK \
0235
0236 #define hpd_int_entry(reg_num)\
0237     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0238         IRQ_REG_ENTRY(HPD, reg_num,\
0239             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0240             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0241         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0242         .funcs = &hpd_irq_info_funcs\
0243     }
0244
0245 #define hpd_rx_int_entry(reg_num)\
0246     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0247         IRQ_REG_ENTRY(HPD, reg_num,\
0248             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0249             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0250         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0251         .funcs = &hpd_rx_irq_info_funcs\
0252     }
0253 #define pflip_int_entry(reg_num)\
0254     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0255         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0256             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0257             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0258         .funcs = &pflip_irq_info_funcs\
0259     }
0260
0261 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0262  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0263  */
0264 #define vupdate_no_lock_int_entry(reg_num)\
0265     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0266         IRQ_REG_ENTRY(OTG, reg_num,\
0267             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0268             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0269         .funcs = &vupdate_no_lock_irq_info_funcs\
0270     }
0271
0272 #define vblank_int_entry(reg_num)\
0273     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0274         IRQ_REG_ENTRY(OTG, reg_num,\
0275             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0276             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0277         .funcs = &vblank_irq_info_funcs\
0278     }
0279
0280 #define vline0_int_entry(reg_num)\
0281     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0282         IRQ_REG_ENTRY(OTG, reg_num,\
0283             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0284             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0285         .funcs = &vline0_irq_info_funcs\
0286     }
0287 #define dmub_outbox_int_entry()\
0288     [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
0289         IRQ_REG_ENTRY_DMUB(\
0290             DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
0291             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
0292         .funcs = &outbox_irq_info_funcs\
0293     }
0294
0295 #define dummy_irq_entry() \
0296     {\
0297         .funcs = &dummy_irq_info_funcs\
0298     }
0299
0300 #define i2c_int_entry(reg_num) \
0301     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0302
0303 #define dp_sink_int_entry(reg_num) \
0304     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0305
0306 #define gpio_pad_int_entry(reg_num) \
0307     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0308
0309 #define dc_underflow_int_entry(reg_num) \
0310     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0311
0312 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0313     .set = dal_irq_service_dummy_set,
0314     .ack = dal_irq_service_dummy_ack
0315 };
0316
0317 static const struct irq_source_info
0318 irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = {
0319     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0320     hpd_int_entry(0),
0321     hpd_int_entry(1),
0322     hpd_int_entry(2),
0323     hpd_int_entry(3),
0324     hpd_int_entry(4),
0325     hpd_rx_int_entry(0),
0326     hpd_rx_int_entry(1),
0327     hpd_rx_int_entry(2),
0328     hpd_rx_int_entry(3),
0329     hpd_rx_int_entry(4),
0330     i2c_int_entry(1),
0331     i2c_int_entry(2),
0332     i2c_int_entry(3),
0333     i2c_int_entry(4),
0334     i2c_int_entry(5),
0335     i2c_int_entry(6),
0336     dp_sink_int_entry(1),
0337     dp_sink_int_entry(2),
0338     dp_sink_int_entry(3),
0339     dp_sink_int_entry(4),
0340     dp_sink_int_entry(5),
0341     dp_sink_int_entry(6),
0342     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0343     pflip_int_entry(0),
0344     pflip_int_entry(1),
0345     pflip_int_entry(2),
0346     pflip_int_entry(3),
0347     [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
0348     [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
0349     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0350     gpio_pad_int_entry(0),
0351     gpio_pad_int_entry(1),
0352     gpio_pad_int_entry(2),
0353     gpio_pad_int_entry(3),
0354     gpio_pad_int_entry(4),
0355     gpio_pad_int_entry(5),
0356     gpio_pad_int_entry(6),
0357     gpio_pad_int_entry(7),
0358     gpio_pad_int_entry(8),
0359     gpio_pad_int_entry(9),
0360     gpio_pad_int_entry(10),
0361     gpio_pad_int_entry(11),
0362     gpio_pad_int_entry(12),
0363     gpio_pad_int_entry(13),
0364     gpio_pad_int_entry(14),
0365     gpio_pad_int_entry(15),
0366     gpio_pad_int_entry(16),
0367     gpio_pad_int_entry(17),
0368     gpio_pad_int_entry(18),
0369     gpio_pad_int_entry(19),
0370     gpio_pad_int_entry(20),
0371     gpio_pad_int_entry(21),
0372     gpio_pad_int_entry(22),
0373     gpio_pad_int_entry(23),
0374     gpio_pad_int_entry(24),
0375     gpio_pad_int_entry(25),
0376     gpio_pad_int_entry(26),
0377     gpio_pad_int_entry(27),
0378     gpio_pad_int_entry(28),
0379     gpio_pad_int_entry(29),
0380     gpio_pad_int_entry(30),
0381     dc_underflow_int_entry(1),
0382     dc_underflow_int_entry(2),
0383     dc_underflow_int_entry(3),
0384     dc_underflow_int_entry(4),
0385     dc_underflow_int_entry(5),
0386     dc_underflow_int_entry(6),
0387     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0388     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0389     vupdate_no_lock_int_entry(0),
0390     vupdate_no_lock_int_entry(1),
0391     vupdate_no_lock_int_entry(2),
0392     vupdate_no_lock_int_entry(3),
0393     vblank_int_entry(0),
0394     vblank_int_entry(1),
0395     vblank_int_entry(2),
0396     vblank_int_entry(3),
0397     vline0_int_entry(0),
0398     vline0_int_entry(1),
0399     vline0_int_entry(2),
0400     vline0_int_entry(3),
0401     [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
0402     [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
0403     dmub_outbox_int_entry(),
0404 };
0405
0406 static const struct irq_service_funcs irq_service_funcs_dcn31 = {
0407         .to_dal_irq_source = to_dal_irq_source_dcn31
0408 };
0409
0410 static void dcn31_irq_construct(
0411     struct irq_service *irq_service,
0412     struct irq_service_init_data *init_data)
0413 {
0414     dal_irq_service_construct(irq_service, init_data);
0415
0416     irq_service->info = irq_source_info_dcn31;
0417     irq_service->funcs = &irq_service_funcs_dcn31;
0418 }
0419
0420 struct irq_service *dal_irq_service_dcn31_create(
0421     struct irq_service_init_data *init_data)
0422 {
0423     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0424                           GFP_KERNEL);
0425
0426     if (!irq_service)
0427         return NULL;
0428
0429     dcn31_irq_construct(irq_service, init_data);
0430     return irq_service;
0431 }