irq/dcn303/irq_service_dcn303.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * Copyright (C) 2021 Advanced Micro Devices, Inc.
0004  *
0005  * Authors: AMD
0006  */
0007
0008 #include "dm_services.h"
0009 #include "irq_service_dcn303.h"
0010 #include "../dce110/irq_service_dce110.h"
0011
0012 #include "sienna_cichlid_ip_offset.h"
0013 #include "dcn/dcn_3_0_3_offset.h"
0014 #include "dcn/dcn_3_0_3_sh_mask.h"
0015
0016 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0017
0018 static enum dc_irq_source to_dal_irq_source_dcn303(struct irq_service *irq_service,
0019                            uint32_t src_id,
0020                            uint32_t ext_id)
0021 {
0022     switch (src_id) {
0023     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0024         return DC_IRQ_SOURCE_VBLANK1;
0025     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0026         return DC_IRQ_SOURCE_VBLANK2;
0027     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0028         return DC_IRQ_SOURCE_DC1_VLINE0;
0029     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0030         return DC_IRQ_SOURCE_DC2_VLINE0;
0031     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0032         return DC_IRQ_SOURCE_PFLIP1;
0033     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0034         return DC_IRQ_SOURCE_PFLIP2;
0035     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0036         return DC_IRQ_SOURCE_VUPDATE1;
0037     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0038         return DC_IRQ_SOURCE_VUPDATE2;
0039
0040     case DCN_1_0__SRCID__DC_HPD1_INT:
0041         /* generic src_id for all HPD and HPDRX interrupts */
0042         switch (ext_id) {
0043         case DCN_1_0__CTXID__DC_HPD1_INT:
0044             return DC_IRQ_SOURCE_HPD1;
0045         case DCN_1_0__CTXID__DC_HPD2_INT:
0046             return DC_IRQ_SOURCE_HPD2;
0047         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0048             return DC_IRQ_SOURCE_HPD1RX;
0049         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0050             return DC_IRQ_SOURCE_HPD2RX;
0051         default:
0052             return DC_IRQ_SOURCE_INVALID;
0053         }
0054         break;
0055
0056     default:
0057         return DC_IRQ_SOURCE_INVALID;
0058     }
0059 }
0060
0061 static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
0062 {
0063     uint32_t addr = info->status_reg;
0064     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0065     uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
0066
0067     dal_irq_service_ack_generic(irq_service, info);
0068
0069     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0070
0071     set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
0072
0073     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0074
0075     return true;
0076 }
0077
0078 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0079         .set = NULL,
0080         .ack = hpd_ack
0081 };
0082
0083 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0084         .set = NULL,
0085         .ack = NULL
0086 };
0087
0088 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0089         .set = NULL,
0090         .ack = NULL
0091 };
0092
0093 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0094     .set = NULL,
0095     .ack = NULL
0096 };
0097
0098 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0099         .set = NULL,
0100         .ack = NULL
0101 };
0102
0103 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0104     .set = NULL,
0105     .ack = NULL
0106 };
0107
0108 #undef BASE_INNER
0109 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0110
0111 /* compile time expand base address. */
0112 #define BASE(seg) BASE_INNER(seg)
0113
0114 #define SRI(reg_name, block, id)\
0115         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0116         mm ## block ## id ## _ ## reg_name
0117
0118
0119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0120         .enable_reg = SRI(reg1, block, reg_num),\
0121         .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0122         .enable_value = {\
0123                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0124                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0125         },\
0126         .ack_reg = SRI(reg2, block, reg_num),\
0127         .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0128         .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0129
0130
0131
0132 #define hpd_int_entry(reg_num)\
0133         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0134                 IRQ_REG_ENTRY(HPD, reg_num,\
0135                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0136                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0137                         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0138                         .funcs = &hpd_irq_info_funcs\
0139 }
0140
0141 #define hpd_rx_int_entry(reg_num)\
0142         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0143                 IRQ_REG_ENTRY(HPD, reg_num,\
0144                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0145                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0146                         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0147                         .funcs = &hpd_rx_irq_info_funcs\
0148 }
0149 #define pflip_int_entry(reg_num)\
0150         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0151                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0152                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0153                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0154                         .funcs = &pflip_irq_info_funcs\
0155 }
0156
0157 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0158  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0159  */
0160 #define vupdate_no_lock_int_entry(reg_num)\
0161     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0162         IRQ_REG_ENTRY(OTG, reg_num,\
0163             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0164             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0165         .funcs = &vupdate_no_lock_irq_info_funcs\
0166     }
0167
0168 #define vblank_int_entry(reg_num)\
0169     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0170         IRQ_REG_ENTRY(OTG, reg_num,\
0171             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0172             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0173         .funcs = &vblank_irq_info_funcs\
0174     }
0175
0176 #define vline0_int_entry(reg_num)\
0177     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0178         IRQ_REG_ENTRY(OTG, reg_num,\
0179             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0180             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0181         .funcs = &vline0_irq_info_funcs\
0182     }
0183
0184 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
0185
0186 #define i2c_int_entry(reg_num) \
0187         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0188
0189 #define dp_sink_int_entry(reg_num) \
0190         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0191
0192 #define gpio_pad_int_entry(reg_num) \
0193         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0194
0195 #define dc_underflow_int_entry(reg_num) \
0196         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0197
0198 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0199         .set = dal_irq_service_dummy_set,
0200         .ack = dal_irq_service_dummy_ack
0201 };
0202
0203 static const struct irq_source_info irq_source_info_dcn303[DAL_IRQ_SOURCES_NUMBER] = {
0204         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0205         hpd_int_entry(0),
0206         hpd_int_entry(1),
0207         hpd_rx_int_entry(0),
0208         hpd_rx_int_entry(1),
0209         i2c_int_entry(1),
0210         i2c_int_entry(2),
0211         dp_sink_int_entry(1),
0212         dp_sink_int_entry(2),
0213         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0214         pflip_int_entry(0),
0215         pflip_int_entry(1),
0216         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0217         gpio_pad_int_entry(0),
0218         gpio_pad_int_entry(1),
0219         gpio_pad_int_entry(2),
0220         gpio_pad_int_entry(3),
0221         gpio_pad_int_entry(4),
0222         gpio_pad_int_entry(5),
0223         gpio_pad_int_entry(6),
0224         gpio_pad_int_entry(7),
0225         gpio_pad_int_entry(8),
0226         gpio_pad_int_entry(9),
0227         gpio_pad_int_entry(10),
0228         gpio_pad_int_entry(11),
0229         gpio_pad_int_entry(12),
0230         gpio_pad_int_entry(13),
0231         gpio_pad_int_entry(14),
0232         gpio_pad_int_entry(15),
0233         gpio_pad_int_entry(16),
0234         gpio_pad_int_entry(17),
0235         gpio_pad_int_entry(18),
0236         gpio_pad_int_entry(19),
0237         gpio_pad_int_entry(20),
0238         gpio_pad_int_entry(21),
0239         gpio_pad_int_entry(22),
0240         gpio_pad_int_entry(23),
0241         gpio_pad_int_entry(24),
0242         gpio_pad_int_entry(25),
0243         gpio_pad_int_entry(26),
0244         gpio_pad_int_entry(27),
0245         gpio_pad_int_entry(28),
0246         gpio_pad_int_entry(29),
0247         gpio_pad_int_entry(30),
0248         dc_underflow_int_entry(1),
0249         dc_underflow_int_entry(2),
0250         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0251         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0252         vupdate_no_lock_int_entry(0),
0253         vupdate_no_lock_int_entry(1),
0254         vblank_int_entry(0),
0255         vblank_int_entry(1),
0256         vline0_int_entry(0),
0257         vline0_int_entry(1),
0258 };
0259
0260 static const struct irq_service_funcs irq_service_funcs_dcn303 = {
0261         .to_dal_irq_source = to_dal_irq_source_dcn303
0262 };
0263
0264 static void dcn303_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
0265 {
0266     dal_irq_service_construct(irq_service, init_data);
0267
0268     irq_service->info = irq_source_info_dcn303;
0269     irq_service->funcs = &irq_service_funcs_dcn303;
0270 }
0271
0272 struct irq_service *dal_irq_service_dcn303_create(struct irq_service_init_data *init_data)
0273 {
0274     struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
0275
0276     if (!irq_service)
0277         return NULL;
0278
0279     dcn303_irq_construct(irq_service, init_data);
0280     return irq_service;
0281 }