irq/dcn302/irq_service_dcn302.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "irq_service_dcn302.h"
0029
0030 #include "../dce110/irq_service_dce110.h"
0031
0032 #include "dimgrey_cavefish_ip_offset.h"
0033 #include "dcn/dcn_3_0_0_offset.h"
0034 #include "dcn/dcn_3_0_0_sh_mask.h"
0035
0036 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0037
0038 static enum dc_irq_source to_dal_irq_source_dcn302(struct irq_service *irq_service, uint32_t src_id, uint32_t ext_id)
0039 {
0040     switch (src_id) {
0041     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0042         return DC_IRQ_SOURCE_VBLANK1;
0043     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0044         return DC_IRQ_SOURCE_VBLANK2;
0045     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0046         return DC_IRQ_SOURCE_VBLANK3;
0047     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0048         return DC_IRQ_SOURCE_VBLANK4;
0049     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0050         return DC_IRQ_SOURCE_VBLANK5;
0051     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0052         return DC_IRQ_SOURCE_VBLANK6;
0053     case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
0054         return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
0055     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0056         return DC_IRQ_SOURCE_DC1_VLINE0;
0057     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0058         return DC_IRQ_SOURCE_DC2_VLINE0;
0059     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0060         return DC_IRQ_SOURCE_DC3_VLINE0;
0061     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0062         return DC_IRQ_SOURCE_DC4_VLINE0;
0063     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0064         return DC_IRQ_SOURCE_DC5_VLINE0;
0065     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0066         return DC_IRQ_SOURCE_DC6_VLINE0;
0067     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0068         return DC_IRQ_SOURCE_PFLIP1;
0069     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0070         return DC_IRQ_SOURCE_PFLIP2;
0071     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0072         return DC_IRQ_SOURCE_PFLIP3;
0073     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0074         return DC_IRQ_SOURCE_PFLIP4;
0075     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0076         return DC_IRQ_SOURCE_PFLIP5;
0077     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0078         return DC_IRQ_SOURCE_PFLIP6;
0079     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0080         return DC_IRQ_SOURCE_VUPDATE1;
0081     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0082         return DC_IRQ_SOURCE_VUPDATE2;
0083     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0084         return DC_IRQ_SOURCE_VUPDATE3;
0085     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0086         return DC_IRQ_SOURCE_VUPDATE4;
0087     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0088         return DC_IRQ_SOURCE_VUPDATE5;
0089     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0090         return DC_IRQ_SOURCE_VUPDATE6;
0091
0092     case DCN_1_0__SRCID__DC_HPD1_INT:
0093         /* generic src_id for all HPD and HPDRX interrupts */
0094         switch (ext_id) {
0095         case DCN_1_0__CTXID__DC_HPD1_INT:
0096             return DC_IRQ_SOURCE_HPD1;
0097         case DCN_1_0__CTXID__DC_HPD2_INT:
0098             return DC_IRQ_SOURCE_HPD2;
0099         case DCN_1_0__CTXID__DC_HPD3_INT:
0100             return DC_IRQ_SOURCE_HPD3;
0101         case DCN_1_0__CTXID__DC_HPD4_INT:
0102             return DC_IRQ_SOURCE_HPD4;
0103         case DCN_1_0__CTXID__DC_HPD5_INT:
0104             return DC_IRQ_SOURCE_HPD5;
0105         case DCN_1_0__CTXID__DC_HPD6_INT:
0106             return DC_IRQ_SOURCE_HPD6;
0107         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0108             return DC_IRQ_SOURCE_HPD1RX;
0109         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0110             return DC_IRQ_SOURCE_HPD2RX;
0111         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0112             return DC_IRQ_SOURCE_HPD3RX;
0113         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0114             return DC_IRQ_SOURCE_HPD4RX;
0115         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0116             return DC_IRQ_SOURCE_HPD5RX;
0117         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0118             return DC_IRQ_SOURCE_HPD6RX;
0119         default:
0120             return DC_IRQ_SOURCE_INVALID;
0121         }
0122         break;
0123
0124     default:
0125         return DC_IRQ_SOURCE_INVALID;
0126     }
0127 }
0128
0129 static bool hpd_ack(struct irq_service *irq_service, const struct irq_source_info *info)
0130 {
0131     uint32_t addr = info->status_reg;
0132     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0133     uint32_t current_status = get_reg_field_value(value, HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED);
0134
0135     dal_irq_service_ack_generic(irq_service, info);
0136
0137     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0138
0139     set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
0140
0141     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0142
0143     return true;
0144 }
0145
0146 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0147         .set = NULL,
0148         .ack = hpd_ack
0149 };
0150
0151 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0152         .set = NULL,
0153         .ack = NULL
0154 };
0155
0156 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0157         .set = NULL,
0158         .ack = NULL
0159 };
0160
0161 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0162     .set = NULL,
0163     .ack = NULL
0164 };
0165
0166 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0167         .set = NULL,
0168         .ack = NULL
0169 };
0170
0171 static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
0172     .set = NULL,
0173     .ack = NULL
0174 };
0175
0176 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0177     .set = NULL,
0178     .ack = NULL
0179 };
0180
0181 #undef BASE_INNER
0182 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0183
0184 /* compile time expand base address. */
0185 #define BASE(seg) BASE_INNER(seg)
0186
0187 #define SRI(reg_name, block, id)\
0188         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0189         mm ## block ## id ## _ ## reg_name
0190
0191 #define SRI_DMUB(reg_name)\
0192         BASE(mm ## reg_name ## _BASE_IDX) + \
0193             mm ## reg_name
0194
0195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0196         .enable_reg = SRI(reg1, block, reg_num),\
0197         .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0198         .enable_value = {\
0199                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0200                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0201         },\
0202         .ack_reg = SRI(reg2, block, reg_num),\
0203         .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0204         .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0205
0206 #define dmub_trace_int_entry()\
0207     [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
0208         IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
0209             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
0210         .funcs = &dmub_trace_irq_info_funcs\
0211     }
0212
0213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0214     .enable_reg = SRI_DMUB(reg1),\
0215     .enable_mask = \
0216         reg1 ## __ ## mask1 ## _MASK,\
0217     .enable_value = {\
0218         reg1 ## __ ## mask1 ## _MASK,\
0219         ~reg1 ## __ ## mask1 ## _MASK \
0220     },\
0221     .ack_reg = SRI_DMUB(reg2),\
0222     .ack_mask = \
0223         reg2 ## __ ## mask2 ## _MASK,\
0224     .ack_value = \
0225         reg2 ## __ ## mask2 ## _MASK \
0226
0227 #define hpd_int_entry(reg_num)\
0228         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0229                 IRQ_REG_ENTRY(HPD, reg_num,\
0230                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0231                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0232                         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0233                         .funcs = &hpd_irq_info_funcs\
0234 }
0235
0236 #define hpd_rx_int_entry(reg_num)\
0237         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0238                 IRQ_REG_ENTRY(HPD, reg_num,\
0239                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0240                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0241                         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0242                         .funcs = &hpd_rx_irq_info_funcs\
0243 }
0244 #define pflip_int_entry(reg_num)\
0245         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0246                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0247                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0248                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0249                         .funcs = &pflip_irq_info_funcs\
0250 }
0251
0252 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0253  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0254  */
0255 #define vupdate_no_lock_int_entry(reg_num)\
0256     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0257         IRQ_REG_ENTRY(OTG, reg_num,\
0258             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0259             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0260         .funcs = &vupdate_no_lock_irq_info_funcs\
0261     }
0262
0263 #define vblank_int_entry(reg_num)\
0264     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0265         IRQ_REG_ENTRY(OTG, reg_num,\
0266             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0267             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0268         .funcs = &vblank_irq_info_funcs\
0269     }
0270
0271 #define vline0_int_entry(reg_num)\
0272     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0273         IRQ_REG_ENTRY(OTG, reg_num,\
0274             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0275             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0276         .funcs = &vline0_irq_info_funcs\
0277     }
0278
0279 #define dummy_irq_entry() { .funcs = &dummy_irq_info_funcs }
0280
0281 #define i2c_int_entry(reg_num) \
0282         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0283
0284 #define dp_sink_int_entry(reg_num) \
0285         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0286
0287 #define gpio_pad_int_entry(reg_num) \
0288         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0289
0290 #define dc_underflow_int_entry(reg_num) \
0291         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0292
0293 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0294         .set = dal_irq_service_dummy_set,
0295         .ack = dal_irq_service_dummy_ack
0296 };
0297
0298 static const struct irq_source_info irq_source_info_dcn302[DAL_IRQ_SOURCES_NUMBER] = {
0299         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0300         hpd_int_entry(0),
0301         hpd_int_entry(1),
0302         hpd_int_entry(2),
0303         hpd_int_entry(3),
0304         hpd_int_entry(4),
0305         hpd_rx_int_entry(0),
0306         hpd_rx_int_entry(1),
0307         hpd_rx_int_entry(2),
0308         hpd_rx_int_entry(3),
0309         hpd_rx_int_entry(4),
0310         i2c_int_entry(1),
0311         i2c_int_entry(2),
0312         i2c_int_entry(3),
0313         i2c_int_entry(4),
0314         i2c_int_entry(5),
0315         dp_sink_int_entry(1),
0316         dp_sink_int_entry(2),
0317         dp_sink_int_entry(3),
0318         dp_sink_int_entry(4),
0319         dp_sink_int_entry(5),
0320         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0321         pflip_int_entry(0),
0322         pflip_int_entry(1),
0323         pflip_int_entry(2),
0324         pflip_int_entry(3),
0325         pflip_int_entry(4),
0326         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0327         gpio_pad_int_entry(0),
0328         gpio_pad_int_entry(1),
0329         gpio_pad_int_entry(2),
0330         gpio_pad_int_entry(3),
0331         gpio_pad_int_entry(4),
0332         gpio_pad_int_entry(5),
0333         gpio_pad_int_entry(6),
0334         gpio_pad_int_entry(7),
0335         gpio_pad_int_entry(8),
0336         gpio_pad_int_entry(9),
0337         gpio_pad_int_entry(10),
0338         gpio_pad_int_entry(11),
0339         gpio_pad_int_entry(12),
0340         gpio_pad_int_entry(13),
0341         gpio_pad_int_entry(14),
0342         gpio_pad_int_entry(15),
0343         gpio_pad_int_entry(16),
0344         gpio_pad_int_entry(17),
0345         gpio_pad_int_entry(18),
0346         gpio_pad_int_entry(19),
0347         gpio_pad_int_entry(20),
0348         gpio_pad_int_entry(21),
0349         gpio_pad_int_entry(22),
0350         gpio_pad_int_entry(23),
0351         gpio_pad_int_entry(24),
0352         gpio_pad_int_entry(25),
0353         gpio_pad_int_entry(26),
0354         gpio_pad_int_entry(27),
0355         gpio_pad_int_entry(28),
0356         gpio_pad_int_entry(29),
0357         gpio_pad_int_entry(30),
0358         dc_underflow_int_entry(1),
0359         dc_underflow_int_entry(2),
0360         dc_underflow_int_entry(3),
0361         dc_underflow_int_entry(4),
0362         dc_underflow_int_entry(5),
0363         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0364         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0365         vupdate_no_lock_int_entry(0),
0366         vupdate_no_lock_int_entry(1),
0367         vupdate_no_lock_int_entry(2),
0368         vupdate_no_lock_int_entry(3),
0369         vupdate_no_lock_int_entry(4),
0370         vblank_int_entry(0),
0371         vblank_int_entry(1),
0372         vblank_int_entry(2),
0373         vblank_int_entry(3),
0374         vblank_int_entry(4),
0375         vline0_int_entry(0),
0376         vline0_int_entry(1),
0377         vline0_int_entry(2),
0378         vline0_int_entry(3),
0379         vline0_int_entry(4),
0380         dmub_trace_int_entry(),
0381 };
0382
0383 static const struct irq_service_funcs irq_service_funcs_dcn302 = {
0384         .to_dal_irq_source = to_dal_irq_source_dcn302
0385 };
0386
0387 static void dcn302_irq_construct(struct irq_service *irq_service, struct irq_service_init_data *init_data)
0388 {
0389     dal_irq_service_construct(irq_service, init_data);
0390
0391     irq_service->info = irq_source_info_dcn302;
0392     irq_service->funcs = &irq_service_funcs_dcn302;
0393 }
0394
0395 struct irq_service *dal_irq_service_dcn302_create(struct irq_service_init_data *init_data)
0396 {
0397     struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL);
0398
0399     if (!irq_service)
0400         return NULL;
0401
0402     dcn302_irq_construct(irq_service, init_data);
0403     return irq_service;
0404 }