irq/dcn30/irq_service_dcn30.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #include "dm_services.h"
0026
0027 #include "include/logger_interface.h"
0028
0029 #include "../dce110/irq_service_dce110.h"
0030
0031
0032 #include "sienna_cichlid_ip_offset.h"
0033 #include "dcn/dcn_3_0_0_offset.h"
0034 #include "dcn/dcn_3_0_0_sh_mask.h"
0035
0036 #include "nbio/nbio_7_4_offset.h"
0037
0038 #include "dpcs/dpcs_3_0_0_offset.h"
0039 #include "dpcs/dpcs_3_0_0_sh_mask.h"
0040
0041 #include "mmhub/mmhub_2_0_0_offset.h"
0042 #include "mmhub/mmhub_2_0_0_sh_mask.h"
0043
0044 #include "irq_service_dcn30.h"
0045
0046 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
0047
0048 static enum dc_irq_source to_dal_irq_source_dcn30(
0049         struct irq_service *irq_service,
0050         uint32_t src_id,
0051         uint32_t ext_id)
0052 {
0053     switch (src_id) {
0054     case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
0055         return DC_IRQ_SOURCE_VBLANK1;
0056     case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
0057         return DC_IRQ_SOURCE_VBLANK2;
0058     case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
0059         return DC_IRQ_SOURCE_VBLANK3;
0060     case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
0061         return DC_IRQ_SOURCE_VBLANK4;
0062     case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
0063         return DC_IRQ_SOURCE_VBLANK5;
0064     case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
0065         return DC_IRQ_SOURCE_VBLANK6;
0066     case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
0067         return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
0068     case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
0069         return DC_IRQ_SOURCE_DC1_VLINE0;
0070     case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
0071         return DC_IRQ_SOURCE_DC2_VLINE0;
0072     case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
0073         return DC_IRQ_SOURCE_DC3_VLINE0;
0074     case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
0075         return DC_IRQ_SOURCE_DC4_VLINE0;
0076     case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
0077         return DC_IRQ_SOURCE_DC5_VLINE0;
0078     case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
0079         return DC_IRQ_SOURCE_DC6_VLINE0;
0080     case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
0081         return DC_IRQ_SOURCE_PFLIP1;
0082     case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
0083         return DC_IRQ_SOURCE_PFLIP2;
0084     case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
0085         return DC_IRQ_SOURCE_PFLIP3;
0086     case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
0087         return DC_IRQ_SOURCE_PFLIP4;
0088     case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
0089         return DC_IRQ_SOURCE_PFLIP5;
0090     case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
0091         return DC_IRQ_SOURCE_PFLIP6;
0092     case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0093         return DC_IRQ_SOURCE_VUPDATE1;
0094     case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0095         return DC_IRQ_SOURCE_VUPDATE2;
0096     case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0097         return DC_IRQ_SOURCE_VUPDATE3;
0098     case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0099         return DC_IRQ_SOURCE_VUPDATE4;
0100     case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0101         return DC_IRQ_SOURCE_VUPDATE5;
0102     case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
0103         return DC_IRQ_SOURCE_VUPDATE6;
0104
0105     case DCN_1_0__SRCID__DC_HPD1_INT:
0106         /* generic src_id for all HPD and HPDRX interrupts */
0107         switch (ext_id) {
0108         case DCN_1_0__CTXID__DC_HPD1_INT:
0109             return DC_IRQ_SOURCE_HPD1;
0110         case DCN_1_0__CTXID__DC_HPD2_INT:
0111             return DC_IRQ_SOURCE_HPD2;
0112         case DCN_1_0__CTXID__DC_HPD3_INT:
0113             return DC_IRQ_SOURCE_HPD3;
0114         case DCN_1_0__CTXID__DC_HPD4_INT:
0115             return DC_IRQ_SOURCE_HPD4;
0116         case DCN_1_0__CTXID__DC_HPD5_INT:
0117             return DC_IRQ_SOURCE_HPD5;
0118         case DCN_1_0__CTXID__DC_HPD6_INT:
0119             return DC_IRQ_SOURCE_HPD6;
0120         case DCN_1_0__CTXID__DC_HPD1_RX_INT:
0121             return DC_IRQ_SOURCE_HPD1RX;
0122         case DCN_1_0__CTXID__DC_HPD2_RX_INT:
0123             return DC_IRQ_SOURCE_HPD2RX;
0124         case DCN_1_0__CTXID__DC_HPD3_RX_INT:
0125             return DC_IRQ_SOURCE_HPD3RX;
0126         case DCN_1_0__CTXID__DC_HPD4_RX_INT:
0127             return DC_IRQ_SOURCE_HPD4RX;
0128         case DCN_1_0__CTXID__DC_HPD5_RX_INT:
0129             return DC_IRQ_SOURCE_HPD5RX;
0130         case DCN_1_0__CTXID__DC_HPD6_RX_INT:
0131             return DC_IRQ_SOURCE_HPD6RX;
0132         default:
0133             return DC_IRQ_SOURCE_INVALID;
0134         }
0135         break;
0136
0137     default:
0138         return DC_IRQ_SOURCE_INVALID;
0139     }
0140 }
0141
0142 static bool hpd_ack(
0143     struct irq_service *irq_service,
0144     const struct irq_source_info *info)
0145 {
0146     uint32_t addr = info->status_reg;
0147     uint32_t value = dm_read_reg(irq_service->ctx, addr);
0148     uint32_t current_status =
0149         get_reg_field_value(
0150             value,
0151             HPD0_DC_HPD_INT_STATUS,
0152             DC_HPD_SENSE_DELAYED);
0153
0154     dal_irq_service_ack_generic(irq_service, info);
0155
0156     value = dm_read_reg(irq_service->ctx, info->enable_reg);
0157
0158     set_reg_field_value(
0159         value,
0160         current_status ? 0 : 1,
0161         HPD0_DC_HPD_INT_CONTROL,
0162         DC_HPD_INT_POLARITY);
0163
0164     dm_write_reg(irq_service->ctx, info->enable_reg, value);
0165
0166     return true;
0167 }
0168
0169 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
0170     .set = NULL,
0171     .ack = hpd_ack
0172 };
0173
0174 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
0175     .set = NULL,
0176     .ack = NULL
0177 };
0178
0179 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
0180     .set = NULL,
0181     .ack = NULL
0182 };
0183
0184 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
0185     .set = NULL,
0186     .ack = NULL
0187 };
0188
0189 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
0190     .set = NULL,
0191     .ack = NULL
0192 };
0193
0194 static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
0195     .set = NULL,
0196     .ack = NULL
0197 };
0198
0199 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
0200     .set = NULL,
0201     .ack = NULL
0202 };
0203
0204 #undef BASE_INNER
0205 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
0206
0207 /* compile time expand base address. */
0208 #define BASE(seg) \
0209     BASE_INNER(seg)
0210
0211
0212 #define SRI(reg_name, block, id)\
0213     BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0214             mm ## block ## id ## _ ## reg_name
0215
0216 #define SRI_DMUB(reg_name)\
0217     BASE(mm ## reg_name ## _BASE_IDX) + \
0218             mm ## reg_name
0219
0220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
0221     .enable_reg = SRI(reg1, block, reg_num),\
0222     .enable_mask = \
0223         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0224     .enable_value = {\
0225         block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
0226         ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
0227     },\
0228     .ack_reg = SRI(reg2, block, reg_num),\
0229     .ack_mask = \
0230         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
0231     .ack_value = \
0232         block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
0233
0234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
0235     .enable_reg = SRI_DMUB(reg1),\
0236     .enable_mask = \
0237         reg1 ## __ ## mask1 ## _MASK,\
0238     .enable_value = {\
0239         reg1 ## __ ## mask1 ## _MASK,\
0240         ~reg1 ## __ ## mask1 ## _MASK \
0241     },\
0242     .ack_reg = SRI_DMUB(reg2),\
0243     .ack_mask = \
0244         reg2 ## __ ## mask2 ## _MASK,\
0245     .ack_value = \
0246         reg2 ## __ ## mask2 ## _MASK \
0247
0248 #define hpd_int_entry(reg_num)\
0249     [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
0250         IRQ_REG_ENTRY(HPD, reg_num,\
0251             DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
0252             DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
0253         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0254         .funcs = &hpd_irq_info_funcs\
0255     }
0256
0257 #define hpd_rx_int_entry(reg_num)\
0258     [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
0259         IRQ_REG_ENTRY(HPD, reg_num,\
0260             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
0261             DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
0262         .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
0263         .funcs = &hpd_rx_irq_info_funcs\
0264     }
0265 #define pflip_int_entry(reg_num)\
0266     [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
0267         IRQ_REG_ENTRY(HUBPREQ, reg_num,\
0268             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
0269             DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
0270         .funcs = &pflip_irq_info_funcs\
0271     }
0272
0273 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
0274  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
0275  */
0276 #define vupdate_no_lock_int_entry(reg_num)\
0277     [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
0278         IRQ_REG_ENTRY(OTG, reg_num,\
0279             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
0280             OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
0281         .funcs = &vupdate_no_lock_irq_info_funcs\
0282     }
0283
0284 #define vblank_int_entry(reg_num)\
0285     [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
0286         IRQ_REG_ENTRY(OTG, reg_num,\
0287             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
0288             OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
0289         .funcs = &vblank_irq_info_funcs\
0290     }
0291
0292 #define dmub_trace_int_entry()\
0293     [DC_IRQ_SOURCE_DMCUB_OUTBOX0] = {\
0294         IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX0_READY_INT_EN,\
0295             DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK),\
0296         .funcs = &dmub_trace_irq_info_funcs\
0297     }
0298
0299 #define vline0_int_entry(reg_num)\
0300     [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
0301         IRQ_REG_ENTRY(OTG, reg_num,\
0302             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
0303             OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
0304         .funcs = &vline0_irq_info_funcs\
0305     }
0306
0307 #define dummy_irq_entry() \
0308     {\
0309         .funcs = &dummy_irq_info_funcs\
0310     }
0311
0312 #define i2c_int_entry(reg_num) \
0313     [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
0314
0315 #define dp_sink_int_entry(reg_num) \
0316     [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
0317
0318 #define gpio_pad_int_entry(reg_num) \
0319     [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
0320
0321 #define dc_underflow_int_entry(reg_num) \
0322     [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
0323
0324 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
0325     .set = dal_irq_service_dummy_set,
0326     .ack = dal_irq_service_dummy_ack
0327 };
0328
0329 static const struct irq_source_info
0330 irq_source_info_dcn30[DAL_IRQ_SOURCES_NUMBER] = {
0331     [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
0332     hpd_int_entry(0),
0333     hpd_int_entry(1),
0334     hpd_int_entry(2),
0335     hpd_int_entry(3),
0336     hpd_int_entry(4),
0337     hpd_int_entry(5),
0338     hpd_rx_int_entry(0),
0339     hpd_rx_int_entry(1),
0340     hpd_rx_int_entry(2),
0341     hpd_rx_int_entry(3),
0342     hpd_rx_int_entry(4),
0343     hpd_rx_int_entry(5),
0344     i2c_int_entry(1),
0345     i2c_int_entry(2),
0346     i2c_int_entry(3),
0347     i2c_int_entry(4),
0348     i2c_int_entry(5),
0349     i2c_int_entry(6),
0350     dp_sink_int_entry(1),
0351     dp_sink_int_entry(2),
0352     dp_sink_int_entry(3),
0353     dp_sink_int_entry(4),
0354     dp_sink_int_entry(5),
0355     dp_sink_int_entry(6),
0356     [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
0357     pflip_int_entry(0),
0358     pflip_int_entry(1),
0359     pflip_int_entry(2),
0360     pflip_int_entry(3),
0361     pflip_int_entry(4),
0362     pflip_int_entry(5),
0363     [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
0364     gpio_pad_int_entry(0),
0365     gpio_pad_int_entry(1),
0366     gpio_pad_int_entry(2),
0367     gpio_pad_int_entry(3),
0368     gpio_pad_int_entry(4),
0369     gpio_pad_int_entry(5),
0370     gpio_pad_int_entry(6),
0371     gpio_pad_int_entry(7),
0372     gpio_pad_int_entry(8),
0373     gpio_pad_int_entry(9),
0374     gpio_pad_int_entry(10),
0375     gpio_pad_int_entry(11),
0376     gpio_pad_int_entry(12),
0377     gpio_pad_int_entry(13),
0378     gpio_pad_int_entry(14),
0379     gpio_pad_int_entry(15),
0380     gpio_pad_int_entry(16),
0381     gpio_pad_int_entry(17),
0382     gpio_pad_int_entry(18),
0383     gpio_pad_int_entry(19),
0384     gpio_pad_int_entry(20),
0385     gpio_pad_int_entry(21),
0386     gpio_pad_int_entry(22),
0387     gpio_pad_int_entry(23),
0388     gpio_pad_int_entry(24),
0389     gpio_pad_int_entry(25),
0390     gpio_pad_int_entry(26),
0391     gpio_pad_int_entry(27),
0392     gpio_pad_int_entry(28),
0393     gpio_pad_int_entry(29),
0394     gpio_pad_int_entry(30),
0395     dc_underflow_int_entry(1),
0396     dc_underflow_int_entry(2),
0397     dc_underflow_int_entry(3),
0398     dc_underflow_int_entry(4),
0399     dc_underflow_int_entry(5),
0400     dc_underflow_int_entry(6),
0401     [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
0402     [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
0403     vupdate_no_lock_int_entry(0),
0404     vupdate_no_lock_int_entry(1),
0405     vupdate_no_lock_int_entry(2),
0406     vupdate_no_lock_int_entry(3),
0407     vupdate_no_lock_int_entry(4),
0408     vupdate_no_lock_int_entry(5),
0409     vblank_int_entry(0),
0410     vblank_int_entry(1),
0411     vblank_int_entry(2),
0412     vblank_int_entry(3),
0413     vblank_int_entry(4),
0414     vblank_int_entry(5),
0415     vline0_int_entry(0),
0416     vline0_int_entry(1),
0417     vline0_int_entry(2),
0418     vline0_int_entry(3),
0419     vline0_int_entry(4),
0420     vline0_int_entry(5),
0421     dmub_trace_int_entry(),
0422 };
0423
0424 static const struct irq_service_funcs irq_service_funcs_dcn30 = {
0425         .to_dal_irq_source = to_dal_irq_source_dcn30
0426 };
0427
0428 static void dcn30_irq_construct(
0429     struct irq_service *irq_service,
0430     struct irq_service_init_data *init_data)
0431 {
0432     dal_irq_service_construct(irq_service, init_data);
0433
0434     irq_service->info = irq_source_info_dcn30;
0435     irq_service->funcs = &irq_service_funcs_dcn30;
0436 }
0437
0438 struct irq_service *dal_irq_service_dcn30_create(
0439     struct irq_service_init_data *init_data)
0440 {
0441     struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
0442                           GFP_KERNEL);
0443
0444     if (!irq_service)
0445         return NULL;
0446
0447     dcn30_irq_construct(irq_service, init_data);
0448     return irq_service;
0449 }
0450